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Commit d50d0a20 authored by Luis Horacio Arnaldi's avatar Luis Horacio Arnaldi
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Agrgeo el ip sts para saber el estado de la escritura. Cambio el código en c en concordancia

parent 6b9f2236
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...@@ -237,5 +237,16 @@ cell labdpr:user:axis_ram_writer writer_0 { ...@@ -237,5 +237,16 @@ cell labdpr:user:axis_ram_writer writer_0 {
aresetn slice_2/dout aresetn slice_2/dout
} }
# Create axi_sts_register
cell labdpr:user:axi_sts_register sts_0 {
STS_DATA_WIDTH 32
AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
} {
sts_data writer_0/sts_data
}
addr 0x40001000 4K cfg_0/S_AXI /ps_0/M_AXI_GP0 addr 0x40001000 4K cfg_0/S_AXI /ps_0/M_AXI_GP0
addr 0x40002000 4K sts_0/S_AXI /ps_0/M_AXI_GP0
...@@ -8,7 +8,7 @@ int main(int argc, char *argv[]) ...@@ -8,7 +8,7 @@ int main(int argc, char *argv[])
uint32_t wo; uint32_t wo;
int16_t ch[2]; int16_t ch[2];
printf("ADC RECORDER test\n"); //printf("ADC RECORDER test\n");
//initialize devices. TODO: add error checking //initialize devices. TODO: add error checking
//intc_init(); //intc_init();
...@@ -20,45 +20,45 @@ int main(int argc, char *argv[]) ...@@ -20,45 +20,45 @@ int main(int argc, char *argv[])
// set writer address // set writer address
// *(uint32_t *)(cfg + 4) = size; // *(uint32_t *)(cfg + 4) = size;
// //
printf("Set writer address...\n"); //printf("Set writer address...\n");
val=rd_reg_value(1, CFG_WR_ADDR_OFFSET); val=rd_reg_value(1, CFG_WR_ADDR_OFFSET,0);
printf("dev_size es: %d ...\n",dev_size); //printf("dev_size es: %d ...\n",dev_size);
wr_reg_value(1, CFG_WR_ADDR_OFFSET, dev_size); wr_reg_value(1, CFG_WR_ADDR_OFFSET, dev_size,0);
// set number of samples // set number of samples
// *(uint32_t *)(cfg + 8) = 1024 * 1024 - 1; // *(uint32_t *)(cfg + 8) = 1024 * 1024 - 1;
// //
printf("Set number of samples...\n"); //printf("Set number of samples...\n");
val=rd_reg_value(1, CFG_NSAMPLES_OFFSET); val=rd_reg_value(1, CFG_NSAMPLES_OFFSET,0);
wr_reg_value(1, CFG_NSAMPLES_OFFSET, 1024 * 1024 - 1); wr_reg_value(1, CFG_NSAMPLES_OFFSET, 1024 * 1024 - 1,0);
// reset writer // reset writer
//*((uint32_t *)(cfg + 0)) &= ~4; //*((uint32_t *)(cfg + 0)) &= ~4;
printf("Reseting writer...\n"); //printf("Reseting writer...\n");
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET); val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~4); wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~4,0);
//*((uint32_t *)(cfg + 0)) |= 4; //*((uint32_t *)(cfg + 0)) |= 4;
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET); val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 4); wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 4,0);
// printf("Reseting writer %d ...\n",val); // printf("Reseting writer %d ...\n",val);
printf("Reseting fifo and filters...\n"); //printf("Reseting fifo and filters...\n");
// // reset fifo and filters // // reset fifo and filters
//*((uint32_t *)(cfg + 0)) &= ~1; //*((uint32_t *)(cfg + 0)) &= ~1;
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET); val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~1); wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~1,0);
// //*((uint32_t *)(cfg + 0)) |= 1; // //*((uint32_t *)(cfg + 0)) |= 1;
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET); val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=1); wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=1,0);
// printf("Reseting fifo and filters %d ...\n",val); // printf("Reseting fifo and filters %d ...\n",val);
// //
// // wait 1 second // // wait 1 second
sleep(1); sleep(1);
// //
printf("Reseting packetizer...\n"); //printf("Reseting packetizer...\n");
// enter reset mode for packetizer // enter reset mode for packetizer
//*((uint32_t *)(cfg + 0)) &= ~2; //*((uint32_t *)(cfg + 0)) &= ~2;
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET); val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~2); wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~2,0);
// set number of samples // set number of samples
//*((uint32_t *)(cfg + 4)) = 1024 * 1024 - 1; //*((uint32_t *)(cfg + 4)) = 1024 * 1024 - 1;
...@@ -66,8 +66,8 @@ int main(int argc, char *argv[]) ...@@ -66,8 +66,8 @@ int main(int argc, char *argv[])
// enter normal mode // enter normal mode
// //*((uint32_t *)(cfg + 0)) |= 2; // //*((uint32_t *)(cfg + 0)) |= 2;
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET); val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=2); wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=2,0);
// printf("Reseting packetizer %d ...\n",val); // printf("Reseting packetizer %d ...\n",val);
// //
// // wait 1 second // // wait 1 second
...@@ -75,9 +75,11 @@ int main(int argc, char *argv[]) ...@@ -75,9 +75,11 @@ int main(int argc, char *argv[])
// print IN1 and IN2 samples // print IN1 and IN2 samples
for(i = 0; i < 1024 * 1024; ++i){ for(i = 0; i < 1024 * 1024; ++i){
ch[0] = *((int16_t *)(cma_ptr + 2*i + 0)); ch[0] = cma_ptr[2*i + 0];
ch[1] = *((int16_t *)(cma_ptr + 2*i + 1)); ch[1] = cma_ptr[2*i + 1];
wo = *((uint32_t *)(cma_ptr + i)); //ch[0] = *((int16_t *)(cma_ptr + 2*i + 0));
//ch[1] = *((int16_t *)(cma_ptr + 2*i + 1));
wo = *((uint32_t *)(cma_ptr + 2*i));
printf("%5d %5d %10d\n", ch[0], ch[1], wo); printf("%5d %5d %10d\n", ch[0], ch[1], wo);
// ch[0] = cma_ptr[2 * i + 0]; // ch[0] = cma_ptr[2 * i + 0];
// ch[1] = cma_ptr[2 * i + 1]; // ch[1] = cma_ptr[2 * i + 1];
...@@ -96,7 +98,7 @@ int main(int argc, char *argv[]) ...@@ -96,7 +98,7 @@ int main(int argc, char *argv[])
close(cfg_fd); close(cfg_fd);
//close(sts_fd); //close(sts_fd);
//close(xadc_fd); //close(xadc_fd);
printf("Saliendo ...\n"); //printf("Saliendo ...\n");
return 0; return 0;
......
...@@ -129,7 +129,7 @@ ...@@ -129,7 +129,7 @@
extern int intc_fd, cfg_fd, sts_fd, xadc_fd, mem_fd, hst0_fd, hst1_fd, cma_fd; extern int intc_fd, cfg_fd, sts_fd, xadc_fd, mem_fd, hst0_fd, hst1_fd, cma_fd;
extern void *intc_ptr, *cfg_ptr, *sts_ptr, *xadc_ptr, *mem_ptr, *hst0_ptr, *hst1_ptr; extern void *intc_ptr, *cfg_ptr, *sts_ptr, *xadc_ptr, *mem_ptr, *hst0_ptr, *hst1_ptr;
extern int16_t *cma_ptr; extern volatile int16_t *cma_ptr;
extern uint32_t dev_size; extern uint32_t dev_size;
void dev_write(void *dev_base, uint32_t offset, int32_t value); void dev_write(void *dev_base, uint32_t offset, int32_t value);
......
...@@ -27,6 +27,7 @@ int main(int argc, char *argv[]) ...@@ -27,6 +27,7 @@ int main(int argc, char *argv[])
printf("Set writer address...\n"); printf("Set writer address...\n");
val=rd_reg_value(1, CFG_WR_ADDR_OFFSET,0); val=rd_reg_value(1, CFG_WR_ADDR_OFFSET,0);
printf("val es: %d ...\n",val);
printf("dev_size es: %d ...\n",dev_size); printf("dev_size es: %d ...\n",dev_size);
wr_reg_value(1, CFG_WR_ADDR_OFFSET, dev_size,0); wr_reg_value(1, CFG_WR_ADDR_OFFSET, dev_size,0);
...@@ -44,6 +45,8 @@ int main(int argc, char *argv[]) ...@@ -44,6 +45,8 @@ int main(int argc, char *argv[])
//writer //writer
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0); val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=4,0); wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=4,0);
// wait 1 second
sleep(2);
//counters //counters
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0); val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 1,0); wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 1,0);
...@@ -51,19 +54,22 @@ int main(int argc, char *argv[]) ...@@ -51,19 +54,22 @@ int main(int argc, char *argv[])
//val=rd_reg_value(1, STS_STATUS_OFFSET,1); //val=rd_reg_value(1, STS_STATUS_OFFSET,1);
//printf("%5d\n", val); //printf("%5d\n", val);
// wait 1 second // wait 1 second
sleep(1); //sleep(1);
// print IN1 and IN2 samples // print IN1 and IN2 samples
for(i = 0; i < 2*65536; ++i){ for(i = 0; i < 2*65536; ++i){
//for(i = 0; i < 65536; i+=4){ //for(i = 0; i < 65536; i+=2){
ch[0] = *(cma_ptr + 2*i + 0); //ch[0] = *(cma_ptr + 2*i + 0);
ch[1] = *(cma_ptr + 2*i + 1); //ch[1] = *(cma_ptr + 2*i + 1);
ch[2] = *((int16_t *)(cma_ptr2 + i)); ch[0] = cma_ptr[2*i + 0];
ch[3] = *((int16_t *)(cma_ptr2 + 2*i)); ch[1] = cma_ptr[2*i + 1];
//ch[2] = *((uint16_t *)(cma_ptr2 + i));
//ch[3] = *((uint16_t *)(cma_ptr2 + 2*i));
wo = *((uint32_t *)(cma_ptr + 2*i)); wo = *((uint32_t *)(cma_ptr + 2*i));
wo2 = *((uint32_t *)(cma_ptr2 + i)); wo2 = *((uint32_t *)(cma_ptr2 + i));
// printf("%5d %5d %10d\n", ch[0], ch[1], wo); //printf("%5d %5d %10d\n", ch[0], ch[1], wo);
printf("%5d %5d %10d %5d %5d %10d\n", ch[1], ch[2], wo, (int16_t)(wo&0xFFFF), (int16_t)(wo>>16), wo2); //printf("%5d %5d %10d\n", ch[2], ch[3], wo2);
printf("%5d %5d %10d %5d %5d %10d\n", ch[0], ch[1], wo, (int16_t)(wo&0xFFFF), (int16_t)(wo>>16), wo2);
// printf("%5d %5d %10d %5d %5d %10d\n", ch[0], ch[1], wo, ch[2], ch[3], wo2); // printf("%5d %5d %10d %5d %5d %10d\n", ch[0], ch[1], wo, ch[2], ch[3], wo2);
//printf("%5d %5d %10d\n", ch[2], ch[3], wo2); //printf("%5d %5d %10d\n", ch[2], ch[3], wo2);
//val=rd_reg_value(1, STS_STATUS_OFFSET,1); //val=rd_reg_value(1, STS_STATUS_OFFSET,1);
......
source projects/base_system/block_design.tcl source projects/base_system/block_design.tcl
# Create proc_sys_reset # Create proc_sys_reset
cell xilinx.com:ip:proc_sys_reset:5.0 rst_0 cell xilinx.com:ip:proc_sys_reset rst_0
# Create axi_cfg_register # Create axi_cfg_register
cell labdpr:user:axi_cfg_register:1.0 cfg_0 { cell labdpr:user:axi_cfg_register cfg_0 {
CFG_DATA_WIDTH 96 CFG_DATA_WIDTH 96
AXI_ADDR_WIDTH 32 AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32 AXI_DATA_WIDTH 32
} }
# Create xlslice # Create xlslice
cell xilinx.com:ip:xlslice:1.0 slice_1 { cell xilinx.com:ip:xlslice slice_1 {
DIN_WIDTH 96 DIN_FROM 0 DIN_TO 0 DOUT_WIDTH 1 DIN_WIDTH 96 DIN_FROM 0 DIN_TO 0 DOUT_WIDTH 1
} { } {
Din cfg_0/cfg_data Din cfg_0/cfg_data
} }
# Create xlslice. Change the frequency # Create xlslice. Change the frequency
cell xilinx.com:ip:xlslice:1.0 slice_2 { cell xilinx.com:ip:xlslice slice_2 {
DIN_WIDTH 96 DIN_FROM 47 DIN_TO 32 DOUT_WIDTH 16 DIN_WIDTH 96 DIN_FROM 47 DIN_TO 32 DOUT_WIDTH 16
} { } {
Din cfg_0/cfg_data Din cfg_0/cfg_data
} }
#Create PWM generator #Create PWM generator
cell labdpr:user:ramp_gen:1.0 ramp_gen_0 { cell labdpr:user:ramp_gen ramp_gen_0 {
COUNT_NBITS 20 COUNT_NBITS 20
COUNT_MOD 5000 COUNT_MOD 5000
DATA_BITS 16 DATA_BITS 16
......
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