From d50d0a2060639520528e2d82cb8576d252fad1e2 Mon Sep 17 00:00:00 2001
From: lharnaldi <lharnaldi@gmail.com>
Date: Fri, 26 Aug 2022 09:25:38 -0300
Subject: [PATCH] =?UTF-8?q?Agrgeo=20el=20ip=20sts=20para=20saber=20el=20es?=
=?UTF-8?q?tado=20de=20la=20escritura.=20Cambio=20el=20c=C3=B3digo=20en=20?=
=?UTF-8?q?c=20en=20concordancia?=
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---
projects/adc_recorder_uio/block_design.tcl | 11 ++++
.../adc_recorder_uio/uio_src/adc_recorder.c | 56 ++++++++++---------
projects/adc_recorder_uio/uio_src/zynq_io.h | 2 +-
projects/counter_test/uio_src/counter_test.c | 22 +++++---
projects/ramp_test/block_design.tcl | 10 ++--
5 files changed, 60 insertions(+), 41 deletions(-)
diff --git a/projects/adc_recorder_uio/block_design.tcl b/projects/adc_recorder_uio/block_design.tcl
index 55c74e0..127e56c 100644
--- a/projects/adc_recorder_uio/block_design.tcl
+++ b/projects/adc_recorder_uio/block_design.tcl
@@ -237,5 +237,16 @@ cell labdpr:user:axis_ram_writer writer_0 {
aresetn slice_2/dout
}
+# Create axi_sts_register
+cell labdpr:user:axi_sts_register sts_0 {
+ STS_DATA_WIDTH 32
+ AXI_ADDR_WIDTH 32
+ AXI_DATA_WIDTH 32
+} {
+ sts_data writer_0/sts_data
+
+}
+
addr 0x40001000 4K cfg_0/S_AXI /ps_0/M_AXI_GP0
+addr 0x40002000 4K sts_0/S_AXI /ps_0/M_AXI_GP0
diff --git a/projects/adc_recorder_uio/uio_src/adc_recorder.c b/projects/adc_recorder_uio/uio_src/adc_recorder.c
index fb87b1a..62fdb06 100644
--- a/projects/adc_recorder_uio/uio_src/adc_recorder.c
+++ b/projects/adc_recorder_uio/uio_src/adc_recorder.c
@@ -8,7 +8,7 @@ int main(int argc, char *argv[])
uint32_t wo;
int16_t ch[2];
- printf("ADC RECORDER test\n");
+ //printf("ADC RECORDER test\n");
//initialize devices. TODO: add error checking
//intc_init();
@@ -20,45 +20,45 @@ int main(int argc, char *argv[])
// set writer address
// *(uint32_t *)(cfg + 4) = size;
//
- printf("Set writer address...\n");
- val=rd_reg_value(1, CFG_WR_ADDR_OFFSET);
- printf("dev_size es: %d ...\n",dev_size);
- wr_reg_value(1, CFG_WR_ADDR_OFFSET, dev_size);
+ //printf("Set writer address...\n");
+ val=rd_reg_value(1, CFG_WR_ADDR_OFFSET,0);
+ //printf("dev_size es: %d ...\n",dev_size);
+ wr_reg_value(1, CFG_WR_ADDR_OFFSET, dev_size,0);
// set number of samples
// *(uint32_t *)(cfg + 8) = 1024 * 1024 - 1;
//
- printf("Set number of samples...\n");
- val=rd_reg_value(1, CFG_NSAMPLES_OFFSET);
- wr_reg_value(1, CFG_NSAMPLES_OFFSET, 1024 * 1024 - 1);
+ //printf("Set number of samples...\n");
+ val=rd_reg_value(1, CFG_NSAMPLES_OFFSET,0);
+ wr_reg_value(1, CFG_NSAMPLES_OFFSET, 1024 * 1024 - 1,0);
// reset writer
//*((uint32_t *)(cfg + 0)) &= ~4;
- printf("Reseting writer...\n");
- val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
- wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~4);
+ //printf("Reseting writer...\n");
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~4,0);
//*((uint32_t *)(cfg + 0)) |= 4;
- val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
- wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 4);
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 4,0);
// printf("Reseting writer %d ...\n",val);
- printf("Reseting fifo and filters...\n");
+ //printf("Reseting fifo and filters...\n");
// // reset fifo and filters
//*((uint32_t *)(cfg + 0)) &= ~1;
- val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
- wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~1);
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~1,0);
// //*((uint32_t *)(cfg + 0)) |= 1;
- val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
- wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=1);
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=1,0);
// printf("Reseting fifo and filters %d ...\n",val);
//
// // wait 1 second
sleep(1);
//
- printf("Reseting packetizer...\n");
+ //printf("Reseting packetizer...\n");
// enter reset mode for packetizer
//*((uint32_t *)(cfg + 0)) &= ~2;
- val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
- wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~2);
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~2,0);
// set number of samples
//*((uint32_t *)(cfg + 4)) = 1024 * 1024 - 1;
@@ -66,8 +66,8 @@ int main(int argc, char *argv[])
// enter normal mode
// //*((uint32_t *)(cfg + 0)) |= 2;
- val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
- wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=2);
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=2,0);
// printf("Reseting packetizer %d ...\n",val);
//
// // wait 1 second
@@ -75,9 +75,11 @@ int main(int argc, char *argv[])
// print IN1 and IN2 samples
for(i = 0; i < 1024 * 1024; ++i){
- ch[0] = *((int16_t *)(cma_ptr + 2*i + 0));
- ch[1] = *((int16_t *)(cma_ptr + 2*i + 1));
- wo = *((uint32_t *)(cma_ptr + i));
+ ch[0] = cma_ptr[2*i + 0];
+ ch[1] = cma_ptr[2*i + 1];
+ //ch[0] = *((int16_t *)(cma_ptr + 2*i + 0));
+ //ch[1] = *((int16_t *)(cma_ptr + 2*i + 1));
+ wo = *((uint32_t *)(cma_ptr + 2*i));
printf("%5d %5d %10d\n", ch[0], ch[1], wo);
// ch[0] = cma_ptr[2 * i + 0];
// ch[1] = cma_ptr[2 * i + 1];
@@ -96,7 +98,7 @@ int main(int argc, char *argv[])
close(cfg_fd);
//close(sts_fd);
//close(xadc_fd);
- printf("Saliendo ...\n");
+ //printf("Saliendo ...\n");
return 0;
diff --git a/projects/adc_recorder_uio/uio_src/zynq_io.h b/projects/adc_recorder_uio/uio_src/zynq_io.h
index e691292..42620d5 100644
--- a/projects/adc_recorder_uio/uio_src/zynq_io.h
+++ b/projects/adc_recorder_uio/uio_src/zynq_io.h
@@ -129,7 +129,7 @@
extern int intc_fd, cfg_fd, sts_fd, xadc_fd, mem_fd, hst0_fd, hst1_fd, cma_fd;
extern void *intc_ptr, *cfg_ptr, *sts_ptr, *xadc_ptr, *mem_ptr, *hst0_ptr, *hst1_ptr;
-extern int16_t *cma_ptr;
+extern volatile int16_t *cma_ptr;
extern uint32_t dev_size;
void dev_write(void *dev_base, uint32_t offset, int32_t value);
diff --git a/projects/counter_test/uio_src/counter_test.c b/projects/counter_test/uio_src/counter_test.c
index 1310cc6..f2091da 100644
--- a/projects/counter_test/uio_src/counter_test.c
+++ b/projects/counter_test/uio_src/counter_test.c
@@ -27,6 +27,7 @@ int main(int argc, char *argv[])
printf("Set writer address...\n");
val=rd_reg_value(1, CFG_WR_ADDR_OFFSET,0);
+ printf("val es: %d ...\n",val);
printf("dev_size es: %d ...\n",dev_size);
wr_reg_value(1, CFG_WR_ADDR_OFFSET, dev_size,0);
@@ -44,6 +45,8 @@ int main(int argc, char *argv[])
//writer
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=4,0);
+ // wait 1 second
+ sleep(2);
//counters
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 1,0);
@@ -51,19 +54,22 @@ int main(int argc, char *argv[])
//val=rd_reg_value(1, STS_STATUS_OFFSET,1);
//printf("%5d\n", val);
// wait 1 second
- sleep(1);
+ //sleep(1);
// print IN1 and IN2 samples
for(i = 0; i < 2*65536; ++i){
- //for(i = 0; i < 65536; i+=4){
- ch[0] = *(cma_ptr + 2*i + 0);
- ch[1] = *(cma_ptr + 2*i + 1);
- ch[2] = *((int16_t *)(cma_ptr2 + i));
- ch[3] = *((int16_t *)(cma_ptr2 + 2*i));
+ //for(i = 0; i < 65536; i+=2){
+ //ch[0] = *(cma_ptr + 2*i + 0);
+ //ch[1] = *(cma_ptr + 2*i + 1);
+ ch[0] = cma_ptr[2*i + 0];
+ ch[1] = cma_ptr[2*i + 1];
+ //ch[2] = *((uint16_t *)(cma_ptr2 + i));
+ //ch[3] = *((uint16_t *)(cma_ptr2 + 2*i));
wo = *((uint32_t *)(cma_ptr + 2*i));
wo2 = *((uint32_t *)(cma_ptr2 + i));
- // printf("%5d %5d %10d\n", ch[0], ch[1], wo);
- printf("%5d %5d %10d %5d %5d %10d\n", ch[1], ch[2], wo, (int16_t)(wo&0xFFFF), (int16_t)(wo>>16), wo2);
+ //printf("%5d %5d %10d\n", ch[0], ch[1], wo);
+ //printf("%5d %5d %10d\n", ch[2], ch[3], wo2);
+ printf("%5d %5d %10d %5d %5d %10d\n", ch[0], ch[1], wo, (int16_t)(wo&0xFFFF), (int16_t)(wo>>16), wo2);
// printf("%5d %5d %10d %5d %5d %10d\n", ch[0], ch[1], wo, ch[2], ch[3], wo2);
//printf("%5d %5d %10d\n", ch[2], ch[3], wo2);
//val=rd_reg_value(1, STS_STATUS_OFFSET,1);
diff --git a/projects/ramp_test/block_design.tcl b/projects/ramp_test/block_design.tcl
index de9b64b..ff3d050 100644
--- a/projects/ramp_test/block_design.tcl
+++ b/projects/ramp_test/block_design.tcl
@@ -1,31 +1,31 @@
source projects/base_system/block_design.tcl
# Create proc_sys_reset
-cell xilinx.com:ip:proc_sys_reset:5.0 rst_0
+cell xilinx.com:ip:proc_sys_reset rst_0
# Create axi_cfg_register
-cell labdpr:user:axi_cfg_register:1.0 cfg_0 {
+cell labdpr:user:axi_cfg_register cfg_0 {
CFG_DATA_WIDTH 96
AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
}
# Create xlslice
-cell xilinx.com:ip:xlslice:1.0 slice_1 {
+cell xilinx.com:ip:xlslice slice_1 {
DIN_WIDTH 96 DIN_FROM 0 DIN_TO 0 DOUT_WIDTH 1
} {
Din cfg_0/cfg_data
}
# Create xlslice. Change the frequency
-cell xilinx.com:ip:xlslice:1.0 slice_2 {
+cell xilinx.com:ip:xlslice slice_2 {
DIN_WIDTH 96 DIN_FROM 47 DIN_TO 32 DOUT_WIDTH 16
} {
Din cfg_0/cfg_data
}
#Create PWM generator
-cell labdpr:user:ramp_gen:1.0 ramp_gen_0 {
+cell labdpr:user:ramp_gen ramp_gen_0 {
COUNT_NBITS 20
COUNT_MOD 5000
DATA_BITS 16
--
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