Pequeños cambios para hacer que compilen algunos proyectos. Nada importante

cores/axis_rp_dac_v1_0/axis_rp_dac.vhd

@@ -13,9 +13,9 @@ entity axis_rp_dac is
 );
 port (
   -- PLL signals
-  aclk : in std_logic;
+  aclk    : in std_logic;
   ddr_clk : in std_logic;
-  locked : in std_logic;
+  locked  : in std_logic;
 
   -- DAC signals
   dac_clk : out std_logic;

projects/adc_recorder_uio/block_design.tcl

-# Create clk_wiz
-cell xilinx.com:ip:clk_wiz pll_0 {
-  PRIMITIVE PLL
-  PRIM_IN_FREQ.VALUE_SRC USER
-  PRIM_IN_FREQ 125.0
-  PRIM_SOURCE Differential_clock_capable_pin
-  CLKOUT1_USED true
-  CLKOUT1_REQUESTED_OUT_FREQ 125.0
-  USE_RESET false
-} {
-  clk_in1_p adc_clk_p_i
-  clk_in1_n adc_clk_n_i
-}
-
-# Create processing_system7
-cell xilinx.com:ip:processing_system7 ps_0 {
-  PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
-  PCW_USE_S_AXI_ACP 1
-  PCW_USE_DEFAULT_ACP_USER_VAL 1
-} {
-  M_AXI_GP0_ACLK pll_0/clk_out1
-  S_AXI_ACP_ACLK pll_0/clk_out1
-}
-
-# Create all required interconnections
-apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
-  make_external {FIXED_IO, DDR}
-  Master Disable
-  Slave Disable
-} [get_bd_cells ps_0]
+source projects/base_system/block_design.tcl
 
 # Create xlconstant
 cell xilinx.com:ip:xlconstant const_0
@@ -37,16 +8,6 @@ cell xilinx.com:ip:proc_sys_reset rst_0 {} {
   ext_reset_in const_0/dout
 }
 
-# GPIO
-
-# Delete input/output port
-delete_bd_objs [get_bd_ports exp_p_tri_io]
-
-# Create output port
-create_bd_port -dir O -from 7 -to 0 exp_p_tri_io
-
-# ADC
-
 # Create axis_red_pitaya_adc
 cell labdpr:user:axis_rp_adc adc_0 {
   ADC_DATA_WIDTH 14

projects/counter_test/block_design.tcl

@@ -119,10 +119,10 @@ cell labdpr:user:axis_tlast_gen tlast_gen_0 {
   AXIS_TDATA_WIDTH 32
   PKT_CNTR_BITS 32
 } {
-  S_AXIS comb_0/M_AXIS
-  pkt_length slice_4/dout
   aclk pll_0/clk_out1
   aresetn slice_1/dout
+  pkt_length slice_4/dout
+  S_AXIS comb_0/M_AXIS
 }
 
 # Create axis_dwidth_converter
@@ -131,9 +131,9 @@ cell xilinx.com:ip:axis_dwidth_converter conv_0 {
   S_TDATA_NUM_BYTES 4
   M_TDATA_NUM_BYTES 8
 } {
-  S_AXIS tlast_gen_0/M_AXIS
   aclk pll_0/clk_out1
   aresetn slice_2/dout
+  S_AXIS tlast_gen_0/M_AXIS
 }
 
 # Create axis_ram_writer

projects/counter_test/uio_src/counter_test.c

@@ -20,10 +20,10 @@ int main(int argc, char *argv[])
 	wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~1,0);
 	printf("Reseting tlast_gen core...\n");
 	val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
-	wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~4,0);
+	wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~2,0);
 	printf("Reseting writer...\n");
 	val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
-	wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~2,0);
+	wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~4,0);
 
 	printf("Set writer address...\n");
 	val=rd_reg_value(1, CFG_WR_ADDR_OFFSET,0);
@@ -44,7 +44,7 @@ int main(int argc, char *argv[])
 	wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 2,0);
   //writer
 	val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
-	wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=4,0);
+	wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 4,0);
 	// wait 1 second
 	sleep(2);
 	//counters

scripts/debian.sh

@@ -36,8 +36,10 @@ mount $root_dev $root_dir
 
 # Copy files to the boot file system
 
+cd ..
 cp boot.bin devicetree.dtb uImage $boot_dir
 cp uEnv-ext4.txt $boot_dir/uEnv.txt
+cd -
 
 # Install Debian base system to the root file system
 

scripts/project.tcl

@@ -3,7 +3,7 @@ set project_name [lindex $argv 0]
 
 set part_name [lindex $argv 1]
 
-file delete -force tmp/$project_name.cache tmp/$project_name.hw tmp/$project_name.srcs tmp/$project_name.runs tmp/$project_name.sim tmp/$project_name.ip_user_files tmp/$project_name.xpr
+file delete -force tmp/$project_name.cache tmp/$project_name.hw tmp/$project_name.srcs tmp/$project_name.runs tmp/$project_name.sim tmp/$project_name.ip_user_files tmp/$project_name.xpr tmp/$project_name.gen
 
 create_project -part $part_name $project_name tmp