diff --git a/cores/axis_rp_dac_v1_0/axis_rp_dac.vhd b/cores/axis_rp_dac_v1_0/axis_rp_dac.vhd
index 55d0535a83c1f35db6a6c5a9c588fa6b1410e00a..8d08cd0a8c452ce6d47a57517a967baa92120946 100644
--- a/cores/axis_rp_dac_v1_0/axis_rp_dac.vhd
+++ b/cores/axis_rp_dac_v1_0/axis_rp_dac.vhd
@@ -13,9 +13,9 @@ entity axis_rp_dac is
);
port (
-- PLL signals
- aclk : in std_logic;
+ aclk : in std_logic;
ddr_clk : in std_logic;
- locked : in std_logic;
+ locked : in std_logic;
-- DAC signals
dac_clk : out std_logic;
diff --git a/projects/adc_recorder_uio/block_design.tcl b/projects/adc_recorder_uio/block_design.tcl
index 127e56c009bc60f59b7c7f5527a4a4abb576ae21..f55a85517bc3e4b668dc3d6dddd5b1d77f9d8f14 100644
--- a/projects/adc_recorder_uio/block_design.tcl
+++ b/projects/adc_recorder_uio/block_design.tcl
@@ -1,33 +1,4 @@
-# Create clk_wiz
-cell xilinx.com:ip:clk_wiz pll_0 {
- PRIMITIVE PLL
- PRIM_IN_FREQ.VALUE_SRC USER
- PRIM_IN_FREQ 125.0
- PRIM_SOURCE Differential_clock_capable_pin
- CLKOUT1_USED true
- CLKOUT1_REQUESTED_OUT_FREQ 125.0
- USE_RESET false
-} {
- clk_in1_p adc_clk_p_i
- clk_in1_n adc_clk_n_i
-}
-
-# Create processing_system7
-cell xilinx.com:ip:processing_system7 ps_0 {
- PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
- PCW_USE_S_AXI_ACP 1
- PCW_USE_DEFAULT_ACP_USER_VAL 1
-} {
- M_AXI_GP0_ACLK pll_0/clk_out1
- S_AXI_ACP_ACLK pll_0/clk_out1
-}
-
-# Create all required interconnections
-apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
- make_external {FIXED_IO, DDR}
- Master Disable
- Slave Disable
-} [get_bd_cells ps_0]
+source projects/base_system/block_design.tcl
# Create xlconstant
cell xilinx.com:ip:xlconstant const_0
@@ -37,16 +8,6 @@ cell xilinx.com:ip:proc_sys_reset rst_0 {} {
ext_reset_in const_0/dout
}
-# GPIO
-
-# Delete input/output port
-delete_bd_objs [get_bd_ports exp_p_tri_io]
-
-# Create output port
-create_bd_port -dir O -from 7 -to 0 exp_p_tri_io
-
-# ADC
-
# Create axis_red_pitaya_adc
cell labdpr:user:axis_rp_adc adc_0 {
ADC_DATA_WIDTH 14
diff --git a/projects/counter_test/block_design.tcl b/projects/counter_test/block_design.tcl
index 4a54b2ae9a4e897898397cecdb502362c0d64330..59e81896f9a28cc050691a17185d9567ef772e5a 100644
--- a/projects/counter_test/block_design.tcl
+++ b/projects/counter_test/block_design.tcl
@@ -119,10 +119,10 @@ cell labdpr:user:axis_tlast_gen tlast_gen_0 {
AXIS_TDATA_WIDTH 32
PKT_CNTR_BITS 32
} {
- S_AXIS comb_0/M_AXIS
- pkt_length slice_4/dout
aclk pll_0/clk_out1
aresetn slice_1/dout
+ pkt_length slice_4/dout
+ S_AXIS comb_0/M_AXIS
}
# Create axis_dwidth_converter
@@ -131,9 +131,9 @@ cell xilinx.com:ip:axis_dwidth_converter conv_0 {
S_TDATA_NUM_BYTES 4
M_TDATA_NUM_BYTES 8
} {
- S_AXIS tlast_gen_0/M_AXIS
aclk pll_0/clk_out1
aresetn slice_2/dout
+ S_AXIS tlast_gen_0/M_AXIS
}
# Create axis_ram_writer
diff --git a/projects/counter_test/uio_src/counter_test.c b/projects/counter_test/uio_src/counter_test.c
index f2091da614fb1bcdfe6ed0e57a15d496b3652c3f..1bd5bcfd7ad00ab81c3585eac345fc416ab4c7df 100644
--- a/projects/counter_test/uio_src/counter_test.c
+++ b/projects/counter_test/uio_src/counter_test.c
@@ -20,10 +20,10 @@ int main(int argc, char *argv[])
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~1,0);
printf("Reseting tlast_gen core...\n");
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
- wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~4,0);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~2,0);
printf("Reseting writer...\n");
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
- wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~2,0);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~4,0);
printf("Set writer address...\n");
val=rd_reg_value(1, CFG_WR_ADDR_OFFSET,0);
@@ -44,7 +44,7 @@ int main(int argc, char *argv[])
wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 2,0);
//writer
val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET,0);
- wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=4,0);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 4,0);
// wait 1 second
sleep(2);
//counters
diff --git a/scripts/debian.sh b/scripts/debian.sh
index 8e30075b8cfe5d5a9424aab50bc8063443cc5def..efe2b95f2638e1e732714b910cb4e76af8f1c06d 100755
--- a/scripts/debian.sh
+++ b/scripts/debian.sh
@@ -36,8 +36,10 @@ mount $root_dev $root_dir
# Copy files to the boot file system
+cd ..
cp boot.bin devicetree.dtb uImage $boot_dir
cp uEnv-ext4.txt $boot_dir/uEnv.txt
+cd -
# Install Debian base system to the root file system
diff --git a/scripts/project.tcl b/scripts/project.tcl
index 5d1a181b6b6d92c7ae00ffd279ef708b97751cd7..1b105e74d9f5e53d2172ee7edd1325e55f415fee 100644
--- a/scripts/project.tcl
+++ b/scripts/project.tcl
@@ -3,7 +3,7 @@ set project_name [lindex $argv 0]
set part_name [lindex $argv 1]
-file delete -force tmp/$project_name.cache tmp/$project_name.hw tmp/$project_name.srcs tmp/$project_name.runs tmp/$project_name.sim tmp/$project_name.ip_user_files tmp/$project_name.xpr
+file delete -force tmp/$project_name.cache tmp/$project_name.hw tmp/$project_name.srcs tmp/$project_name.runs tmp/$project_name.sim tmp/$project_name.ip_user_files tmp/$project_name.xpr tmp/$project_name.gen
create_project -part $part_name $project_name tmp