Agrego los cores interpolador y decimador. También el lfsr

Makefile

@@ -26,16 +26,19 @@ CORES = axi_axis_reader_v1_0 \
 				axis_constant_v1_0 \
 				axis_counter_v1_0 \
 				axis_dc_removal_v1_0 \
+				axis_decimator_v1_0 \
 				axis_fifo_v1_0 \
 				axis_generator_v1_0 \
 				axis_gpio_reader_i_v1_0 \
 				axis_gpio_reader_v1_0 \
 				axis_histogram_v1_0 \
 				axis_histogram_v1_1 \
+				axis_interpolator_v1_0 \
 				axis_lago_trigger_v1_0 \
 				axis_lago_trigger_v1_1 \
 				axis_lago_trigger_v1_2 \
 				axis_lago_trigger_v1_3 \
+				axis_lfsr_v1_0 \
 				axis_lpf_v1_0 \
 				axis_packetizer_v1_0 \
 				axis_ram_writer_v1_0 \
@@ -61,7 +64,7 @@ CORES = axi_axis_reader_v1_0 \
 				pwm_gen_v1_0 \
 				ramp_gen_v1_0 \
 				selector_v1_0 \
-				time_trig_gen_v1_0
+				time_trig_gen_v1_0 
 
 VIVADO = vivado -nolog -nojournal -mode batch
 XSCT = xsct

cores/axis_decimator_v1_0/axis_decimator.vhd

+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axis_decimator is
+  generic (
+    AXIS_TDATA_WIDTH : natural  := 32;
+    CNTR_WIDTH       : natural  := 32
+);
+port (
+  -- System signals
+  aclk           : in std_logic;
+  aresetn        : in std_logic;
+
+  cfg_data       : in std_logic_vector(CNTR_WIDTH-1 downto 0);
+
+  -- Slave side
+  s_axis_tready  : out std_logic;
+  s_axis_tdata   : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+  s_axis_tvalid  : in std_logic;
+
+  -- Master side
+  m_axis_tready  : in std_logic;
+  m_axis_tdata   : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+  m_axis_tvalid  : out std_logic
+);
+end axis_decimator;
+
+architecture rtl of axis_decimator is
+
+  signal int_tdata_reg, int_tdata_next : std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+  signal int_cntr_reg, int_cntr_next: unsigned(CNTR_WIDTH-1 downto 0);
+  signal int_tvalid_reg, int_tvalid_next: std_logic;
+  signal int_tready_reg, int_tready_next: std_logic;
+
+  signal int_comp_wire, int_tvalid_wire: std_logic;
+
+begin
+
+  int_comp_wire <= '1' when (int_cntr_reg < unsigned(cfg_data)) else '0';
+  int_tvalid_wire <= int_tready_reg and s_axis_tvalid;
+
+  process(aclk)
+  begin
+  if (rising_edge(aclk)) then
+  if (aresetn = '0') then
+    int_tdata_reg <= (others => '0');
+    int_tvalid_reg <= '0';
+    int_tready_reg <= '0';
+    int_cntr_reg <= (others => '0');
+  else
+    int_tdata_reg <= int_tdata_next;
+    int_tvalid_reg <= int_tvalid_next;
+    int_tready_reg <= int_tready_next;
+    int_cntr_reg <= int_cntr_next;
+  end if;
+  end if;
+  end process;
+
+
+  int_tready_next <= '1' when (int_tready_reg = '0') and (int_comp_wire = '1') else
+                     int_tready_reg;
+
+  int_cntr_next <= int_cntr_reg + 1 when (int_tvalid_wire = '1') and (int_comp_wire = '1') else
+                   (others => '0') when (int_tvalid_wire = '1') and (int_comp_wire = '0') else
+                   int_cntr_reg;
+
+  int_tdata_next <= s_axis_tdata when (int_tvalid_wire = '1') and (int_comp_wire = '0') else
+                        int_tdata_reg;
+
+  int_tvalid_next <= '1' when (int_tvalid_wire = '1') and (int_comp_wire = '0') else
+                    '0' when (m_axis_tready = '1') and (int_tvalid_reg = '1') else
+                    int_tvalid_reg;
+
+  s_axis_tready <= int_tready_reg;
+  m_axis_tdata <= int_tdata_reg;
+  m_axis_tvalid <= int_tvalid_reg;
+
+end rtl;

cores/axis_decimator_v1_0/core_config.tcl

+set display_name {AXI4-Stream Decimator}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the M_AXIS and S_AXIS data buses.}
+core_parameter CNTR_WIDTH {CNTR WIDTH} {Width of the counter register.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core m_axis]
+set_property NAME M_AXIS $bus
+set_property INTERFACE_MODE master $bus
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axis]
+set_property NAME S_AXIS $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE M_AXIS:S_AXIS $parameter

cores/axis_interpolator_v1_0/axis_interpolator.vhd

+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axis_interpolator is
+  generic (
+    AXIS_TDATA_WIDTH : natural  := 32;
+    CNTR_WIDTH : natural  := 32
+);
+port (
+  -- System signals
+  aclk : in std_logic;
+  aresetn : in std_logic;
+
+  cfg_data : in std_logic_vector(CNTR_WIDTH-1 downto 0);
+
+  -- Slave side
+  s_axis_tready : out std_logic;
+  s_axis_tdata : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+  s_axis_tvalid : in std_logic;
+
+  -- Master side
+  m_axis_tready : in std_logic;
+  m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+  m_axis_tvalid : out std_logic
+);
+end axis_interpolator;
+
+architecture rtl of axis_interpolator is
+
+  signal int_tdata_reg, int_tdata_next : std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+  signal int_cntr_reg, int_cntr_next: unsigned(CNTR_WIDTH-1 downto 0);
+  signal int_tvalid_reg, int_tvalid_next: std_logic;
+
+begin
+
+  process(aclk)
+  begin
+  if (rising_edge(aclk)) then
+  if (aresetn = '0') then
+    int_tdata_reg <= (others => '0');
+    int_tvalid_reg <= '0';
+    int_cntr_reg <= (others => '0');
+  else
+    int_tdata_reg <= int_tdata_next;
+    int_tvalid_reg <= int_tvalid_next;
+    int_cntr_reg <= int_cntr_next;
+  end if;
+  end if;
+  end process;
+
+  int_tdata_next <= s_axis_tdata when (s_axis_tvalid = '1') and (int_tvalid_reg = '0') else
+                        int_tdata_reg;
+
+  int_cntr_next <= int_cntr_reg + 1 when (m_axis_tready = '1') and (int_tvalid_reg = '1') and (int_cntr_reg < unsigned(cfg_data)) else
+                   (others => '0') when (m_axis_tready = '1') and (int_tvalid_reg = '1') and not(int_cntr_reg < unsigned(cfg_data)) else
+                   int_cntr_reg;
+
+  int_tvalid_next <= '1' when (s_axis_tvalid = '1') and (int_tvalid_reg = '0') else
+                    '0' when (m_axis_tready = '1') and (int_tvalid_reg = '1') and not(int_cntr_reg < unsigned(cfg_data)) else
+                    int_tvalid_reg;
+
+  s_axis_tready <= not(int_tvalid_reg);
+  m_axis_tdata <= int_tdata_reg;
+  m_axis_tvalid <= int_tvalid_reg;
+
+end rtl;

cores/axis_interpolator_v1_0/core_config.tcl

+set display_name {AXI4-Stream Interpolator}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the M_AXIS and S_AXIS data buses.}
+core_parameter CNTR_WIDTH {CNTR WIDTH} {Width of the counter register.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core m_axis]
+set_property NAME M_AXIS $bus
+set_property INTERFACE_MODE master $bus
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axis]
+set_property NAME S_AXIS $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE M_AXIS:S_AXIS $parameter

cores/axis_lfsr_v1_0/axis_lfsr.vhd

+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axis_lfsr is
+  generic (
+            HAS_TREADY      : boolean := FALSE;
+            AXIS_TDATA_WIDTH: natural := 64
+          );
+  port (
+         -- System signals
+         aclk          : in std_logic;
+         aresetn       : in std_logic;
+
+         -- Master side
+         m_axis_tready : in std_logic;
+         m_axis_tvalid : out std_logic;
+         m_axis_tdata  : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0)
+       );
+end axis_lfsr;
+
+architecture rtl of axis_lfsr is
+  signal int_lfsr_reg, int_lfsr_next : std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+  signal int_enbl_reg, int_enbl_next : std_logic;
+  signal tmp_sig                     : std_logic;
+
+begin
+
+  process(aclk)
+  begin
+    if rising_edge(aclk) then 
+      if aresetn = '0' then
+        int_lfsr_reg <= std_logic_vector(to_unsigned(16#5#, AXIS_TDATA_WIDTH));
+        int_enbl_reg <= '0';
+      else 
+        int_lfsr_reg <= int_lfsr_next;
+        int_enbl_reg <= int_enbl_next;
+      end if;
+      end if;
+    end process;
+    
+    tmp_sig <= int_lfsr_reg(AXIS_TDATA_WIDTH-2) xnor int_lfsr_reg(AXIS_TDATA_WIDTH-3);
+
+    WITH_TREADY: if (HAS_TREADY) generate
+      int_lfsr_next <= int_lfsr_reg(AXIS_TDATA_WIDTH-2 downto 0) & tmp_sig when (int_enbl_reg = '1' and m_axis_tready = '1') else 
+                       int_lfsr_reg;
+      int_enbl_next <= '1' when (int_enbl_reg = '0') else 
+                       int_enbl_reg;
+    end generate;
+    NO_TREADY: if (not HAS_TREADY) generate
+      int_lfsr_next <= int_lfsr_reg(AXIS_TDATA_WIDTH-2 downto 0) & tmp_sig when (int_enbl_reg = '1') else 
+                       int_lfsr_reg;
+      int_enbl_next <= '1' when (int_enbl_reg = '0') else 
+                       int_enbl_reg;
+    end generate;
+
+  m_axis_tdata <= int_lfsr_reg;
+  m_axis_tvalid <= int_enbl_reg;
+end rtl;

cores/axis_lfsr_v1_0/core_config.tcl

+set display_name {AXI4-Stream Linear Feedback Shift-Register}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the M_AXIS data bus.}
+core_parameter HAS_TREADY {HAS TREADY} {If TRUE, use m_axis_tready.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core m_axis]
+set_property NAME M_AXIS $bus
+set_property INTERFACE_MODE master $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE M_AXIS $parameter