Makefile

README.md

cfg/ports.tcl

cfg/ports.xdc

cfg/red_pitaya.xml

cores/axi_bram_reader_v1_0/axi_bram_reader.vhd

cores/axi_bram_reader_v1_0/core_config.tcl

cores/axi_time_trig_gen_v1_0/axi_cfg_register.vhd

cores/axi_time_trig_gen_v1_0/axi_time_trig_gen.vhd

cores/axi_time_trig_gen_v1_0/core_config.tcl

cores/axi_time_trig_gen_v1_0/shift_reg.vhd

cores/axis_avgr16bits_v1_0/asym_ram_sdp_write_wider.vhd

cores/axis_avgr16bits_v1_0/avg_ntoone.vhd

cores/axis_avgr16bits_v1_0/avg_scope.vhd

cores/axis_avgr16bits_v1_0/axis_averager.vhd

cores/axis_avgr16bits_v1_0/axis_signal_mux.vhd

cores/axis_avgr16bits_v1_0/axis_signal_selector.vhd

cores/axis_avgr16bits_v1_0/bram_reader.vhd

cores/axis_avgr16bits_v1_0/core_config.tcl

cores/axis_avgr16bits_v1_0/edge_det.vhd