Skip to content
Snippets Groups Projects
Commit 7c20eae3 authored by Luis Horacio Arnaldi's avatar Luis Horacio Arnaldi
Browse files

Agrego los cores axi_axis_reader y writer para trabajar con LAGO

parent 94b5793a
No related branches found
No related tags found
No related merge requests found
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_axis_writer is
generic (
AXI_DATA_WIDTH : natural := 32;
AXI_ADDR_WIDTH : natural := 32
);
port (
-- System signals
aclk : in std_logic;
aresetn : in std_logic;
-- Slave side
s_axi_awaddr : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); -- AXI4-Lite slave: Write address
s_axi_awvalid : in std_logic; -- AXI4-Lite slave: Write address valid
s_axi_awready : out std_logic; -- AXI4-Lite slave: Write address ready
s_axi_wdata : in std_logic_vector(AXI_DATA_WIDTH-1 downto 0); -- AXI4-Lite slave: Write data
s_axi_wvalid : in std_logic; -- AXI4-Lite slave: Write data valid
s_axi_wready : out std_logic; -- AXI4-Lite slave: Write data ready
s_axi_bresp : out std_logic_vector(1 downto 0); -- AXI4-Lite slave: Write response
s_axi_bvalid : out std_logic; -- AXI4-Lite slave: Write response valid
s_axi_bready : in std_logic; -- AXI4-Lite slave: Write response ready
s_axi_araddr : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); -- AXI4-Lite slave: Read address
s_axi_arvalid : in std_logic; -- AXI4-Lite slave: Read address valid
s_axi_arready : out std_logic; -- AXI4-Lite slave: Read address ready
s_axi_rdata : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0); -- AXI4-Lite slave: Read data
s_axi_rresp : out std_logic_vector(1 downto 0); -- AXI4-Lite slave: Read data response
s_axi_rvalid : in std_logic; -- AXI4-Lite slave: Read data valid
s_axi_rready : in std_logic; -- AXI4-Lite slave: Read data ready
-- Master side
m_axis_tdata : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
m_axis_tvalid : out std_logic
);
end axi_axis_writer;
architecture rtl of axi_axis_writer is
signal int_ready_reg, int_ready_next : std_logic;
signal int_valid_reg, int_valid_next : std_logic;
signal int_tdata_reg, int_tdata_next : std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
begin
process(aclk)
begin
if rising_edge(aclk) then
if (aresetn = '0') then
int_valid_reg <= '0';
else
int_valid_reg <= int_valid_next;
end if;
end if;
end process;
int_valid_next <= '1' when (s_axi_wvalid = '1') else
'0' when (s_axi_bready = '1') and (int_valid_reg = '1') else
int_valid_reg;
s_axi_bresp <= (others => '0');
s_axi_awready <= '1';
s_axi_wready <= '1';
s_axi_bvalid <= int_valid_reg;
m_axis_tdata <= s_axi_wdata;
m_axis_tvalid <= s_axi_wvalid;
end rtl;
set display_name {AXI AXI4-Stream Writer}
set core [ipx::current_core]
set_property DISPLAY_NAME $display_name $core
set_property DESCRIPTION $display_name $core
core_parameter AXI_DATA_WIDTH {AXI DATA WIDTH} {Width of the AXI data bus.}
core_parameter AXI_ADDR_WIDTH {AXI ADDR WIDTH} {Width of the AXI address bus.}
set bus [ipx::get_bus_interfaces -of_objects $core s_axi]
set_property NAME S_AXI $bus
set_property INTERFACE_MODE slave $bus
set bus [ipx::get_bus_interfaces -of_objects $core m_axis]
set_property NAME M_AXIS $bus
set_property INTERFACE_MODE master $bus
set bus [ipx::get_bus_interfaces aclk]
set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
set_property VALUE M_AXIS:S_AXI $parameter
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_bram_reader is
generic (
AXI_DATA_WIDTH : natural := 32;
AXI_ADDR_WIDTH : natural := 16;
BRAM_ADDR_WIDTH : natural := 10;
BRAM_DATA_WIDTH : natural := 32
);
port (
-- System signals
aclk : in std_logic;
aresetn : in std_logic;
-- Slave side
s_axi_awaddr : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); -- AXI4-Lite slave: Write address
s_axi_awvalid : in std_logic; -- AXI4-Lite slave: Write address valid
s_axi_awready : out std_logic; -- AXI4-Lite slave: Write address ready
s_axi_wdata : in std_logic_vector(AXI_DATA_WIDTH-1 downto 0); -- AXI4-Lite slave: Write data
s_axi_wvalid : in std_logic; -- AXI4-Lite slave: Write data valid
s_axi_wready : out std_logic; -- AXI4-Lite slave: Write data ready
s_axi_bresp : out std_logic_vector(1 downto 0); -- AXI4-Lite slave: Write response
s_axi_bvalid : out std_logic; -- AXI4-Lite slave: Write response valid
s_axi_bready : in std_logic; -- AXI4-Lite slave: Write response ready
s_axi_araddr : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); -- AXI4-Lite slave: Read address
s_axi_arvalid : in std_logic; -- AXI4-Lite slave: Read address valid
s_axi_arready : out std_logic; -- AXI4-Lite slave: Read address ready
s_axi_rdata : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0); -- AXI4-Lite slave: Read data
s_axi_rresp : out std_logic_vector(1 downto 0); -- AXI4-Lite slave: Read data response
s_axi_rvalid : out std_logic; -- AXI4-Lite slave: Read data valid
s_axi_rready : in std_logic; -- AXI4-Lite slave: Read data ready
-- BRAM port
bram_porta_clk : out std_logic;
bram_porta_rst : out std_logic;
bram_porta_addr: out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
bram_porta_rddata : in std_logic_vector(BRAM_DATA_WIDTH-1 downto 0)
);
end axi_bram_reader;
architecture rtl of axi_bram_reader is
function clogb2 (value: natural) return natural is
variable temp : natural := value;
variable ret_val : natural := 1;
begin
while temp > 1 loop
ret_val := ret_val + 1;
temp := temp / 2;
end loop;
return ret_val;
end function;
constant ADDR_LSB : natural := clogb2((AXI_DATA_WIDTH/8) - 1);
signal int_rvalid_reg, int_rvalid_next : std_logic;
begin
process(aclk)
begin
if rising_edge(aclk) then
if (aresetn = '0') then
int_rvalid_reg <= '0';
else
int_rvalid_reg <= int_rvalid_next;
end if;
end if;
end process;
-- Next state logic
int_rvalid_next <= '1' when (s_axi_arvalid = '1') else
'0' when (s_axi_rready = '1' and int_rvalid_reg = '1') else
int_rvalid_reg;
s_axi_rresp <= (others => '0');
s_axi_arready <= '1';
s_axi_rdata <= bram_porta_rddata;
s_axi_rvalid <= int_rvalid_reg;
bram_porta_clk <= aclk;
bram_porta_rst <= not aresetn;
bram_porta_addr <= s_axi_araddr(ADDR_LSB+BRAM_ADDR_WIDTH-1 downto ADDR_LSB);
end rtl;
set display_name {AXI Block RAM Reader}
set core [ipx::current_core]
set_property DISPLAY_NAME $display_name $core
set_property DESCRIPTION $display_name $core
core_parameter AXI_DATA_WIDTH {AXI DATA WIDTH} {Width of the AXI data bus.}
core_parameter AXI_ADDR_WIDTH {AXI ADDR WIDTH} {Width of the AXI address bus.}
core_parameter BRAM_DATA_WIDTH {BRAM DATA WIDTH} {Width of the BRAM data port.}
core_parameter BRAM_ADDR_WIDTH {BRAM ADDR WIDTH} {Width of the BRAM address port.}
set bus [ipx::get_bus_interfaces -of_objects $core s_axi]
set_property NAME S_AXI $bus
set_property INTERFACE_MODE slave $bus
set bus [ipx::get_bus_interfaces aclk]
set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
set_property VALUE S_AXI $parameter
set bus [ipx::add_bus_interface BRAM_PORTA $core]
set_property ABSTRACTION_TYPE_VLNV xilinx.com:interface:bram_rtl:1.0 $bus
set_property BUS_TYPE_VLNV xilinx.com:interface:bram:1.0 $bus
set_property INTERFACE_MODE master $bus
foreach {logical physical} {
RST bram_porta_rst
CLK bram_porta_clk
ADDR bram_porta_addr
DOUT bram_porta_rddata
} {
set_property PHYSICAL_NAME $physical [ipx::add_port_map $logical $bus]
}
set bus [ipx::get_bus_interfaces bram_porta_clk]
set parameter [ipx::add_bus_parameter ASSOCIATED_BUSIF $bus]
set_property VALUE BRAM_PORTA $parameter
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment