From f92b0069d9fc853a7b36d002c1941d09277d1a9d Mon Sep 17 00:00:00 2001 From: lharnaldi <lharnaldi@gmail.com> Date: Fri, 5 Aug 2022 09:42:10 -0300 Subject: [PATCH] Agrgeo el core axis_constant --- cores/axis_constant_v1_0/axis_constant.vhd | 29 ++++++++++ cores/axis_constant_v1_0/core_config.tcl | 16 ++++++ scripts/fpga-bit-to-bin.py | 65 ++++++++++++++++++++++ 3 files changed, 110 insertions(+) create mode 100644 cores/axis_constant_v1_0/axis_constant.vhd create mode 100644 cores/axis_constant_v1_0/core_config.tcl create mode 100644 scripts/fpga-bit-to-bin.py diff --git a/cores/axis_constant_v1_0/axis_constant.vhd b/cores/axis_constant_v1_0/axis_constant.vhd new file mode 100644 index 0000000..96a1ab1 --- /dev/null +++ b/cores/axis_constant_v1_0/axis_constant.vhd @@ -0,0 +1,29 @@ +library ieee; + +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axis_constant is + generic ( + AXIS_TDATA_WIDTH: natural := 32 + ); + port ( + -- System signals + aclk : in std_logic; + + cfg_data : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0); + + -- Master side + m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0); + m_axis_tvalid : out std_logic + ); +end axis_constant; + +architecture rtl of axis_constant is + +begin + + m_axis_tdata <= cfg_data; + m_axis_tvalid <= '1'; + +end rtl; diff --git a/cores/axis_constant_v1_0/core_config.tcl b/cores/axis_constant_v1_0/core_config.tcl new file mode 100644 index 0000000..195c4d9 --- /dev/null +++ b/cores/axis_constant_v1_0/core_config.tcl @@ -0,0 +1,16 @@ +set display_name {AXI4-Stream Constant} + +set core [ipx::current_core] + +set_property DISPLAY_NAME $display_name $core +set_property DESCRIPTION $display_name $core + +core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the M_AXIS data bus.} + +set bus [ipx::get_bus_interfaces -of_objects $core m_axis] +set_property NAME M_AXIS $bus +set_property INTERFACE_MODE master $bus + +set bus [ipx::get_bus_interfaces aclk] +set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF] +set_property VALUE M_AXIS $parameter diff --git a/scripts/fpga-bit-to-bin.py b/scripts/fpga-bit-to-bin.py new file mode 100644 index 0000000..607f4e3 --- /dev/null +++ b/scripts/fpga-bit-to-bin.py @@ -0,0 +1,65 @@ +#!/usr/bin/python + +# copied from https://github.com/topic-embedded-products/meta-topic/blob/master/recipes-bsp/fpga/fpga-bit-to-bin/fpga-bit-to-bin.py + +import sys +import os +import struct + +def flip32(data): + sl = struct.Struct('<I') + sb = struct.Struct('>I') + b = buffer(data) + d = bytearray(len(data)) + for offset in xrange(0, len(data), 4): + sb.pack_into(d, offset, sl.unpack_from(b, offset)[0]) + return d + +import argparse +parser = argparse.ArgumentParser(description='Convert FPGA bit files to raw bin format suitable for flashing') +parser.add_argument('-f', '--flip', dest='flip', action='store_true', default=False, help='Flip 32-bit endianess (needed for Zynq)') +parser.add_argument("bitfile", help="Input bit file name") +parser.add_argument("binfile", help="Output bin file name") +args = parser.parse_args() + +short = struct.Struct('>H') +ulong = struct.Struct('>I') + +bitfile = open(args.bitfile, 'rb') + +l = short.unpack(bitfile.read(2))[0] +if l != 9: + raise Exception, "Missing <0009> header (0x%x), not a bit file" % l +bitfile.read(l) +l = short.unpack(bitfile.read(2))[0] +d = bitfile.read(l) +if d != 'a': + raise Exception, "Missing <a> header, not a bit file" + +l = short.unpack(bitfile.read(2))[0] +d = bitfile.read(l) +print "Design name:", d + +KEYNAMES = {'b': "Partname", 'c': "Date", 'd': "Time"} + +while 1: + k = bitfile.read(1) + if not k: + raise Exception, "unexpected EOF" + elif k == 'e': + l = ulong.unpack(bitfile.read(4))[0] + print "found binary data:", l + d = bitfile.read(l) + if args.flip: + d = flip32(d) + open(args.binfile, 'wb').write(d) + break + elif k in KEYNAMES: + l = short.unpack(bitfile.read(2))[0] + d = bitfile.read(l) + print KEYNAMES[k], d + else: + print "Unexpected key: ", k + l = short.unpack(bitfile.read(2))[0] + d = bitfile.read(l) + -- GitLab