From cb6ed535dde1962a5a13849293361024e527b855 Mon Sep 17 00:00:00 2001
From: Horacio Arnaldi <lharnaldi@gmail.com>
Date: Sat, 11 Mar 2023 11:34:49 -0300
Subject: [PATCH] Paso el branch develop de lago_ecosystem al branch con el
mismo nombre en rp_ecosystem
---
Makefile | 118 ++----
README.md | 12 +-
cfg/ports.tcl | 4 +-
cfg/ports.xdc | 79 ++--
cfg/red_pitaya.xml | 97 ++++-
.../axis_bram_reader.vhd | 135 ++++---
cores/axis_bram_reader_v1_0/core_config.tcl | 7 +-
.../axis_bram_writer.vhd | 77 ++--
cores/axis_constant_v1_0/axis_constant.vhd | 26 +-
cores/axis_counter_v1_0/axis_counter.vhd | 54 +--
.../axis_gpio_reader.vhd | 42 +-
cores/axis_lago_trigger_v1_0/core_config.tcl | 2 +-
cores/axis_lago_trigger_v1_1/core_config.tcl | 2 +-
.../axis_ram_writer_v1_0/axis_ram_writer.vhd | 162 ++++----
cores/axis_trigger_v1_0/axis_trigger.vhd | 48 +--
cores/pps_gen_v1_0/pps_gen.vhd | 2 +-
patches/devicetree.patch | 8 +
patches/xilinx_zynq_defconfig | 14 +-
patches/zynq-red-pitaya.dts | 2 +-
patches/zynq_red_pitaya_defconfig | 56 ++-
projects/adc_recorder/adc-recorder.c | 71 ++--
projects/adc_recorder/block_design.tcl | 198 ++++-----
projects/adc_test/block_design.tcl | 343 ++++++----------
.../adc_test/client/adc-test-client_lnx.c | 45 +--
projects/adc_test/server/adc-test-server.c | 184 ++++-----
.../base_system/base_system/block_design.tcl | 29 ++
projects/base_system/block_design.tcl | 40 +-
projects/cfg_test/block_design.tcl | 46 ++-
projects/gpio_led_test/block_design.tcl | 50 +--
projects/gpio_led_test/gpio_led_test.c | 379 +++++++++---------
projects/led_blinker/block_design.tcl | 9 +-
projects/xadc_test/xadc_test.c | 192 ++++-----
scripts/core.tcl | 2 +-
scripts/debian.sh | 86 ++--
scripts/devicetree.tcl | 20 +-
scripts/fsbl.tcl | 14 +-
scripts/hwdef.tcl | 7 +-
scripts/image.sh | 2 +-
scripts/project.tcl | 15 +-
scripts/ubuntu.sh | 58 ++-
settings.sh | 4 +-
uEnv.txt | 8 +-
42 files changed, 1368 insertions(+), 1381 deletions(-)
create mode 100644 projects/base_system/base_system/block_design.tcl
mode change 100755 => 100644 scripts/debian.sh
mode change 100755 => 100644 scripts/image.sh
mode change 100644 => 100755 uEnv.txt
diff --git a/Makefile b/Makefile
index 483a549..7e084a2 100644
--- a/Makefile
+++ b/Makefile
@@ -12,91 +12,48 @@ NAME = led_blinker
PART = xc7z010clg400-1
PROC = ps7_cortexa9_0
-CORES = axi_axis_reader_v1_0 \
- axi_axis_writer_v1_0 \
- axi_bram_reader_v1_0 \
- axi_cfg_register_v1_0 \
- axi_sts_register_v1_0 \
- axi_time_trig_gen_v1_0 \
- axis_avgr16bits_v1_0 \
- axis_avgr32bits_v1_0 \
- axis_avgr_v1_0 \
- axis_bram_reader_v1_0 \
- axis_bram_writer_v1_0 \
- axis_constant_v1_0 \
- axis_counter_v1_0 \
- axis_dc_removal_v1_0 \
- axis_decimator_v1_0 \
- axis_fifo_v1_0 \
- axis_generator_v1_0 \
- axis_gpio_reader_i_v1_0 \
- axis_gpio_reader_v1_0 \
- axis_histogram_v1_0 \
- axis_histogram_v1_1 \
- axis_interpolator_v1_0 \
- axis_lago_trigger_v1_0 \
- axis_lago_trigger_v1_1 \
- axis_lago_trigger_v1_2 \
- axis_lago_trigger_v1_3 \
- axis_lfsr_v1_0 \
- axis_lpf_v1_0 \
- axis_oscilloscope_v1_0 \
- axis_packetizer_v1_0 \
- axis_phase_generator_v1_0 \
- axis_ram_writer_v1_0 \
- axis_rp_adc_v1_0 \
- axis_rp_adc_v3_0 \
- axis_rp_dac_v1_0 \
- axis_rp_dac_v2_0 \
- axis_tlast_gen_v1_0 \
- axis_trigger_v1_0 \
- axis_validator_v1_0 \
- axis_variable_v1_0 \
- axis_zero_crossing_det_v1_0 \
- axis_zeroer_v1_0 \
- bram_counter_v1_0 \
- bram_selector_v1_0 \
- dc_removal_v1_0 \
- dna_reader_v1_0 \
- int_counter_v1_0 \
- port_selector_v1_0 \
- port_slicer_v1_0 \
- pps_gen_v1_0 \
- pps_gen_v1_1 \
- pwm_gen_v1_0 \
- ramp_gen_v1_0 \
- selector_v1_0 \
- time_trig_gen_v1_0
+CORES = axis_rp_adc_v1_0 axis_rp_dac_v1_0 dna_reader_v1_0 axi_sts_register_v1_0 \
+ axi_cfg_register_v1_0 axi_axis_reader_v1_0 axi_axis_writer_v1_0 \
+ axis_constant_v1_0 axis_counter_v1_0 axis_decimator_v1_0 \
+ axis_interpolator_v1_0 axis_packetizer_v1_0 axis_zeroer_v1_0 \
+ axis_ram_writer_v1_0 axis_gpio_reader_v1_0 axis_oscilloscope_v1_0 \
+ axis_trigger_v1_0 axis_variable_v1_0 axis_lago_trigger_v1_0 axis_tlast_gen_v1_0 \
+ pps_gen_v1_0 ramp_gen_v1_0 axis_bram_writer_v1_0 axis_bram_reader_v1_0 \
+ axis_gpio_reader_i_v1_0 axis_lago_trigger_v1_1 int_counter_v1_0
VIVADO = vivado -nolog -nojournal -mode batch
-XSCT = xsct
+HSI = hsi -nolog -nojournal -mode batch
RM = rm -rf
-UBOOT_TAG = 2021.04
-LINUX_TAG = 5.10
-DTREE_TAG = xilinx-v2020.2
+UBOOT_TAG = xilinx-v2019.2
+LINUX_TAG = 5.4
+DTREE_TAG = xilinx-v2019.2
-UBOOT_DIR = tmp/u-boot-$(UBOOT_TAG)
+UBOOT_DIR = tmp/u-boot-xlnx-$(UBOOT_TAG)
LINUX_DIR = tmp/linux-$(LINUX_TAG)
DTREE_DIR = tmp/device-tree-xlnx-$(DTREE_TAG)
-UBOOT_TAR = tmp/u-boot-$(UBOOT_TAG).tar.bz2
+UBOOT_TAR = tmp/u-boot-xlnx-$(UBOOT_TAG).tar.gz
LINUX_TAR = tmp/linux-$(LINUX_TAG).tar.xz
DTREE_TAR = tmp/device-tree-xlnx-$(DTREE_TAG).tar.gz
-UBOOT_URL = https://ftp.denx.de/pub/u-boot/u-boot-$(UBOOT_TAG).tar.bz2
-LINUX_URL = https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-$(LINUX_TAG).46.tar.xz
+UBOOT_URL = https://github.com/Xilinx/u-boot-xlnx/archive/$(UBOOT_TAG).tar.gz
+LINUX_URL = https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-$(LINUX_TAG).80.tar.xz
DTREE_URL = https://github.com/Xilinx/device-tree-xlnx/archive/$(DTREE_TAG).tar.gz
+LINUX_CFLAGS = "-O2 -march=armv7-a -mtune=cortex-a9 -mfpu=neon -mfloat-abi=hard"
+UBOOT_CFLAGS = "-O2 -march=armv7-a -mtune=cortex-a9 -mfpu=neon -mfloat-abi=hard"
+ARMHF_CFLAGS = "-O2 -march=armv7-a -mtune=cortex-a9 -mfpu=neon -mfloat-abi=hard"
+
RTL8188_TAR = tmp/rtl8188eu-v5.2.2.4.tar.gz
RTL8188_URL = https://github.com/lwfinger/rtl8188eu/archive/v5.2.2.4.tar.gz
RTL8192_TAR = tmp/rtl8192cu-fixes-master.tar.gz
RTL8192_URL = https://github.com/pvaret/rtl8192cu-fixes/archive/master.tar.gz
-.PRECIOUS: tmp/cores/% tmp/%.xpr tmp/%.xsa tmp/%.bit tmp/%.fsbl/executable.elf tmp/%.tree/system-top.dts
+.PRECIOUS: tmp/cores/% tmp/%.xpr tmp/%.hwdef tmp/%.bit tmp/%.fsbl/executable.elf tmp/%.tree/system-top.dts
-all: tmp/$(NAME).bit boot.bin uImage devicetree.dtb
+all: boot.bin uImage devicetree.dtb
cores: $(addprefix tmp/cores/, $(CORES))
@@ -126,10 +83,12 @@ $(RTL8192_TAR):
$(UBOOT_DIR): $(UBOOT_TAR)
mkdir -p $@
- tar -jxf $< --strip-components=1 --directory=$@
- patch -d tmp -p 0 < patches/u-boot-$(UBOOT_TAG).patch
+ tar -zxf $< --strip-components=1 --directory=$@
+ patch -d tmp -p 0 < patches/u-boot-xlnx-$(UBOOT_TAG).patch
cp patches/zynq_red_pitaya_defconfig $@/configs
cp patches/zynq-red-pitaya.dts $@/arch/arm/dts
+ cp patches/zynq_red_pitaya.h $@/include/configs
+ cp patches/u-boot-lantiq.c $@/drivers/net/phy/lantiq.c
$(LINUX_DIR): $(LINUX_TAR) $(RTL8188_TAR) $(RTL8192_TAR)
mkdir -p $@
@@ -140,7 +99,6 @@ $(LINUX_DIR): $(LINUX_TAR) $(RTL8188_TAR) $(RTL8192_TAR)
tar -zxf $(RTL8192_TAR) --strip-components=1 --directory=$@/drivers/net/wireless/realtek/rtl8192cu
patch -d tmp -p 0 < patches/linux-$(LINUX_TAG).patch
cp patches/zynq_ocm.c $@/arch/arm/mach-zynq
- cp patches/cma.c $@/drivers/char
cp patches/xilinx_devcfg.c $@/drivers/char
cp patches/xilinx_zynq_defconfig $@/arch/arm/configs
@@ -151,20 +109,22 @@ $(DTREE_DIR): $(DTREE_TAR)
uImage: $(LINUX_DIR)
make -C $< mrproper
make -C $< ARCH=arm xilinx_zynq_defconfig
- make -C $< ARCH=arm -j $(shell nproc 2> /dev/null || echo 1) \
+ make -C $< ARCH=arm CFLAGS=$(LINUX_CFLAGS) \
+ -j $(shell nproc 2> /dev/null || echo 1) \
CROSS_COMPILE=arm-linux-gnueabihf- UIMAGE_LOADADDR=0x8000 \
uImage modules
cp $</arch/arm/boot/uImage $@
-$(UBOOT_DIR)/u-boot.bin: $(UBOOT_DIR)
+tmp/u-boot.elf: $(UBOOT_DIR)
mkdir -p $(@D)
make -C $< mrproper
make -C $< ARCH=arm zynq_red_pitaya_defconfig
- make -C $< ARCH=arm -j $(shell nproc 2> /dev/null || echo 1) \
+ make -C $< ARCH=arm CFLAGS=$(UBOOT_CFLAGS)
CROSS_COMPILE=arm-linux-gnueabihf- all
+ cp $</u-boot $@
-boot.bin: tmp/$(NAME).fsbl/executable.elf $(UBOOT_DIR)/u-boot.bin
- echo "img:{[bootloader] tmp/$(NAME).fsbl/executable.elf [load=0x4000000,startup=0x4000000] $(UBOOT_DIR)/u-boot.bin}" > tmp/boot.bif
+boot.bin: tmp/$(NAME).fsbl/executable.elf tmp/$(NAME).bit tmp/u-boot.elf
+ echo "img:{[bootloader] $^}" > tmp/boot.bif
bootgen -image tmp/boot.bif -w -o i $@
devicetree.dtb: uImage tmp/$(NAME).tree/system-top.dts
@@ -179,7 +139,7 @@ tmp/%.xpr: projects/% $(addprefix tmp/cores/, $(CORES))
mkdir -p $(@D)
$(VIVADO) -source scripts/project.tcl -tclargs $* $(PART)
-tmp/%.xsa: tmp/%.xpr
+tmp/%.hwdef: tmp/%.xpr
mkdir -p $(@D)
$(VIVADO) -source scripts/hwdef.tcl -tclargs $*
@@ -187,13 +147,13 @@ tmp/%.bit: tmp/%.xpr
mkdir -p $(@D)
$(VIVADO) -source scripts/bitstream.tcl -tclargs $*
-tmp/%.fsbl/executable.elf: tmp/%.xsa
+tmp/%.fsbl/executable.elf: tmp/%.hwdef
mkdir -p $(@D)
- $(XSCT) scripts/fsbl.tcl $* $(PROC)
-
-tmp/%.tree/system-top.dts: tmp/%.xsa $(DTREE_DIR)
+ $(HSI) -source scripts/fsbl.tcl -tclargs $* $(PROC)
+#
+tmp/%.tree/system-top.dts: tmp/%.hwdef $(DTREE_DIR)
mkdir -p $(@D)
- $(XSCT) scripts/devicetree.tcl $* $(PROC) $(DTREE_DIR)
+ $(HSI) -source scripts/devicetree.tcl -tclargs $* $(PROC) $(DTREE_DIR)
sed -i 's|#include|/include/|' $@
patch -d $(@D) < patches/devicetree.patch
diff --git a/README.md b/README.md
index 1fd12a4..f65cb1f 100644
--- a/README.md
+++ b/README.md
@@ -6,11 +6,11 @@ Lago Ecosystem is a build system for quick prototyping and working with the Zynq
## Quickstart with the [Red Pitaya](http://redpitaya.com)
-### 1. Requirements for Ubuntu 20.04 Focal Fossa
+### 1. Requirements for Ubuntu 16.04
-#### 1.1. Download and install [`Vitis Core Development Kit 2020.2`](https://www.xilinx.com/products/design-tools/vitis.html).
+#### 1.1. Download [`Vivado HLx 2016.4: All OS Installer Single-File Download`](https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2016-4.html).
-<!--#### 1.2 Run
+#### 1.2 Run
```bash
$ sudo apt-get install curl
@@ -18,8 +18,8 @@ $ cd ~/Downloads
$ curl https://raw.githubusercontent.com/lagoprojectrp/lago_ecosystem/master/scripts/install_vivado.sh | sudo /bin/bash /dev/stdin
$ sudo ln -s make /usr/bin/gmake # tells Vivado to use make instead of gmake
```
--->
-#### 1.2. Install requirements
+
+#### 1.3. Install requirements
```bash
$ sudo apt-get update
@@ -36,7 +36,7 @@ $ git clone https://github.com/lagoprojectrp/lago_ecosystem
$ cd lago_ecosystem
```
-### 2. Install LAGO Linux for Red Pitaya ([Download SD card image](https://mega.nz/file/1x500SzQ#I-k3LtOxLmN-VBHQXgzCrJ10x1OFs9E7NEM5Rpq72pM))
+### 2. Install LAGO Linux for Red Pitaya ([Download SD card image](https://mega.nz/#!BxZgmLjY!I8BuaMg53Kzo_eZQKRjOMfJlu95qR2zWT_BbRXjgNVQ))
### 3. Build and run the minimal instrument
diff --git a/cfg/ports.tcl b/cfg/ports.tcl
index 9a7319b..5823941 100644
--- a/cfg/ports.tcl
+++ b/cfg/ports.tcl
@@ -1,8 +1,8 @@
### ADC
-create_bd_port -dir I -from 15 -to 0 adc_dat_a_i
-create_bd_port -dir I -from 15 -to 0 adc_dat_b_i
+create_bd_port -dir I -from 13 -to 0 adc_dat_a_i
+create_bd_port -dir I -from 13 -to 0 adc_dat_b_i
create_bd_port -dir I adc_clk_p_i
create_bd_port -dir I adc_clk_n_i
diff --git a/cfg/ports.xdc b/cfg/ports.xdc
index f0703c5..790160c 100644
--- a/cfg/ports.xdc
+++ b/cfg/ports.xdc
@@ -9,42 +9,38 @@
set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_a_i[*]}]
set_property IOB TRUE [get_ports {adc_dat_a_i[*]}]
-set_property PACKAGE_PIN V17 [get_ports {adc_dat_a_i[0]}]
-set_property PACKAGE_PIN U17 [get_ports {adc_dat_a_i[1]}]
-set_property PACKAGE_PIN Y17 [get_ports {adc_dat_a_i[2]}]
-set_property PACKAGE_PIN W16 [get_ports {adc_dat_a_i[3]}]
-set_property PACKAGE_PIN Y16 [get_ports {adc_dat_a_i[4]}]
-set_property PACKAGE_PIN W15 [get_ports {adc_dat_a_i[5]}]
-set_property PACKAGE_PIN W14 [get_ports {adc_dat_a_i[6]}]
-set_property PACKAGE_PIN Y14 [get_ports {adc_dat_a_i[7]}]
-set_property PACKAGE_PIN W13 [get_ports {adc_dat_a_i[8]}]
-set_property PACKAGE_PIN V12 [get_ports {adc_dat_a_i[9]}]
-set_property PACKAGE_PIN V13 [get_ports {adc_dat_a_i[10]}]
-set_property PACKAGE_PIN T14 [get_ports {adc_dat_a_i[11]}]
-set_property PACKAGE_PIN T15 [get_ports {adc_dat_a_i[12]}]
-set_property PACKAGE_PIN V15 [get_ports {adc_dat_a_i[13]}]
-set_property PACKAGE_PIN T16 [get_ports {adc_dat_a_i[14]}]
-set_property PACKAGE_PIN V16 [get_ports {adc_dat_a_i[15]}]
+set_property PACKAGE_PIN Y17 [get_ports {adc_dat_a_i[0]}]
+set_property PACKAGE_PIN W16 [get_ports {adc_dat_a_i[1]}]
+set_property PACKAGE_PIN Y16 [get_ports {adc_dat_a_i[2]}]
+set_property PACKAGE_PIN W15 [get_ports {adc_dat_a_i[3]}]
+set_property PACKAGE_PIN W14 [get_ports {adc_dat_a_i[4]}]
+set_property PACKAGE_PIN Y14 [get_ports {adc_dat_a_i[5]}]
+set_property PACKAGE_PIN W13 [get_ports {adc_dat_a_i[6]}]
+set_property PACKAGE_PIN V12 [get_ports {adc_dat_a_i[7]}]
+set_property PACKAGE_PIN V13 [get_ports {adc_dat_a_i[8]}]
+set_property PACKAGE_PIN T14 [get_ports {adc_dat_a_i[9]}]
+set_property PACKAGE_PIN T15 [get_ports {adc_dat_a_i[10]}]
+set_property PACKAGE_PIN V15 [get_ports {adc_dat_a_i[11]}]
+set_property PACKAGE_PIN T16 [get_ports {adc_dat_a_i[12]}]
+set_property PACKAGE_PIN V16 [get_ports {adc_dat_a_i[13]}]
set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_b_i[*]}]
set_property IOB TRUE [get_ports {adc_dat_b_i[*]}]
-set_property PACKAGE_PIN T17 [get_ports {adc_dat_b_i[0]}]
-set_property PACKAGE_PIN R16 [get_ports {adc_dat_b_i[1]}]
-set_property PACKAGE_PIN R18 [get_ports {adc_dat_b_i[2]}]
-set_property PACKAGE_PIN P16 [get_ports {adc_dat_b_i[3]}]
-set_property PACKAGE_PIN P18 [get_ports {adc_dat_b_i[4]}]
-set_property PACKAGE_PIN N17 [get_ports {adc_dat_b_i[5]}]
-set_property PACKAGE_PIN R19 [get_ports {adc_dat_b_i[6]}]
-set_property PACKAGE_PIN T20 [get_ports {adc_dat_b_i[7]}]
-set_property PACKAGE_PIN T19 [get_ports {adc_dat_b_i[8]}]
-set_property PACKAGE_PIN U20 [get_ports {adc_dat_b_i[9]}]
-set_property PACKAGE_PIN V20 [get_ports {adc_dat_b_i[10]}]
-set_property PACKAGE_PIN W20 [get_ports {adc_dat_b_i[11]}]
-set_property PACKAGE_PIN W19 [get_ports {adc_dat_b_i[12]}]
-set_property PACKAGE_PIN Y19 [get_ports {adc_dat_b_i[13]}]
-set_property PACKAGE_PIN W18 [get_ports {adc_dat_b_i[14]}]
-set_property PACKAGE_PIN Y18 [get_ports {adc_dat_b_i[15]}]
+set_property PACKAGE_PIN R18 [get_ports {adc_dat_b_i[0]}]
+set_property PACKAGE_PIN P16 [get_ports {adc_dat_b_i[1]}]
+set_property PACKAGE_PIN P18 [get_ports {adc_dat_b_i[2]}]
+set_property PACKAGE_PIN N17 [get_ports {adc_dat_b_i[3]}]
+set_property PACKAGE_PIN R19 [get_ports {adc_dat_b_i[4]}]
+set_property PACKAGE_PIN T20 [get_ports {adc_dat_b_i[5]}]
+set_property PACKAGE_PIN T19 [get_ports {adc_dat_b_i[6]}]
+set_property PACKAGE_PIN U20 [get_ports {adc_dat_b_i[7]}]
+set_property PACKAGE_PIN V20 [get_ports {adc_dat_b_i[8]}]
+set_property PACKAGE_PIN W20 [get_ports {adc_dat_b_i[9]}]
+set_property PACKAGE_PIN W19 [get_ports {adc_dat_b_i[10]}]
+set_property PACKAGE_PIN Y19 [get_ports {adc_dat_b_i[11]}]
+set_property PACKAGE_PIN W18 [get_ports {adc_dat_b_i[12]}]
+set_property PACKAGE_PIN Y18 [get_ports {adc_dat_b_i[13]}]
# clock input
@@ -154,6 +150,8 @@ set_property SLEW FAST [get_ports {exp_p_tri_io[*]}]
set_property SLEW FAST [get_ports {exp_n_tri_io[*]}]
set_property DRIVE 8 [get_ports {exp_p_tri_io[*]}]
set_property DRIVE 8 [get_ports {exp_n_tri_io[*]}]
+set_property PULLTYPE PULLUP [get_ports {exp_p_tri_io[*]}]
+set_property PULLTYPE PULLUP [get_ports {exp_n_tri_io[*]}]
set_property PACKAGE_PIN G17 [get_ports {exp_p_tri_io[0]}]
set_property PACKAGE_PIN G18 [get_ports {exp_n_tri_io[0]}]
@@ -172,6 +170,21 @@ set_property PACKAGE_PIN J16 [get_ports {exp_n_tri_io[6]}]
set_property PACKAGE_PIN M14 [get_ports {exp_p_tri_io[7]}]
set_property PACKAGE_PIN M15 [get_ports {exp_n_tri_io[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports exp_p_trg]
+set_property SLEW FAST [get_ports exp_p_trg]
+set_property DRIVE 8 [get_ports exp_p_trg]
+
+set_property PACKAGE_PIN M14 [get_ports exp_p_trg]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_alex[*]}]
+set_property SLEW FAST [get_ports {exp_n_alex[*]}]
+set_property DRIVE 8 [get_ports {exp_n_alex[*]}]
+
+set_property PACKAGE_PIN L15 [get_ports {exp_n_alex[0]}]
+set_property PACKAGE_PIN L17 [get_ports {exp_n_alex[1]}]
+set_property PACKAGE_PIN J16 [get_ports {exp_n_alex[2]}]
+set_property PACKAGE_PIN M15 [get_ports {exp_n_alex[3]}]
+
### SATA connector
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_o[*]]
@@ -196,7 +209,7 @@ set_property PACKAGE_PIN P19 [get_ports {daisy_n_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_o[*]}]
set_property SLEW SLOW [get_ports {led_o[*]}]
-set_property DRIVE 4 [get_ports {led_o[*]}]
+set_property DRIVE 8 [get_ports {led_o[*]}]
set_property PACKAGE_PIN F16 [get_ports {led_o[0]}]
set_property PACKAGE_PIN F17 [get_ports {led_o[1]}]
diff --git a/cfg/red_pitaya.xml b/cfg/red_pitaya.xml
index c48ea19..1a54655 100644
--- a/cfg/red_pitaya.xml
+++ b/cfg/red_pitaya.xml
@@ -1,15 +1,18 @@
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE project PUBLIC "project" "project.dtd" >
<project version="1.0" >
+ <description >
+ </description>
+ <Projinfo Part="xc7z010clg400-1" DeviceSize="xc7z010" Package="clg400" Speed="-1" />
<set param="PCW::ENET0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::ENET0::GRP_MDIO::ENABLE" value="1" />
<set param="PCW::ENET0::ENET0::IO" value="MIO 16 .. 27" />
- <set param="PCW::ENET0::GRP_MDIO::IO" value="MIO 52 .. 53" />
<set param="PCW::GPIO::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::GPIO::MIO_GPIO::ENABLE" value="1" />
<set param="PCW::GPIO::EMIO_GPIO::ENABLE" value="1" />
<set param="PCW::I2C0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::I2C0::I2C0::IO" value="MIO 50 .. 51" />
+ <set param="PCW::I2C1::PERIPHERAL::ENABLE" value="0" />
<set param="PCW::UART0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::UART0::UART0::IO" value="MIO 14 .. 15" />
<set param="PCW::UART1::PERIPHERAL::ENABLE" value="1" />
@@ -17,8 +20,11 @@
<set param="PCW::USB0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::USB0::RESET::ENABLE" value="1" />
<set param="PCW::USB0::RESET::IO" value="MIO 48" />
+ <set param="PCW::USB1::PERIPHERAL::ENABLE" value="0" />
+ <set param="PCW::QSPI::PERIPHERAL::ENABLE" value="1" />
+ <set param="PCW::QSPI::GRP_SS1::ENABLE" value="0" />
+ <set param="PCW::QSPI::GRP_FBCLK::ENABLE" value="0" />
<set param="PCW::SD0::PERIPHERAL::ENABLE" value="1" />
- <set param="PCW::SD0::SD0::IO" value="MIO 40 .. 45" />
<set param="PCW::SD0::GRP_CD::ENABLE" value="1" />
<set param="PCW::SD0::GRP_WP::ENABLE" value="1" />
<set param="PCW::SD0::GRP_CD::IO" value="MIO 46" />
@@ -26,45 +32,132 @@
<set param="PCW::SPI0::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::SPI1::PERIPHERAL::ENABLE" value="1" />
<set param="PCW::SPI1::SPI1::IO" value="MIO 10 .. 15" />
+ <set param="PCW::TTC0::PERIPHERAL::ENABLE" value="1" />
+ <set param="PCW::FPGA0::PERIPHERAL::FREQMHZ" value="125" />
+ <set param="PCW::CAN::PERIPHERAL::FREQMHZ" value="100" />
+ <set param="PCW::QSPI::PERIPHERAL::FREQMHZ" value="125" />
+ <set param="PCW::ENET0::PERIPHERAL::FREQMHZ" value="1000 Mbps" />
+ <set param="PCW::PRESET::FPGA::PARTNUMBER" value="xc7z010clg400-1" />
+ <set param="PCW::PRESET::FPGA::SPEED" value="-1" />
<set param="PCW::PRESET::BANK0::VOLTAGE" value="LVCMOS 3.3V" />
<set param="PCW::PRESET::BANK1::VOLTAGE" value="LVCMOS 2.5V" />
+ <set param="PCW::PRESET::GLOBAL::CONFIG" value="Default" />
+ <set param="PCW::PRESET::GLOBAL::DEFAULT" value="powerup" />
<set param="PCW::UIPARAM::DDR::PARTNO" value="MT41J256M16 RE-125" />
<set param="PCW::UIPARAM::DDR::BUS_WIDTH" value="16 Bit" />
+ <set param="PCW::UIPARAM::DDR::DRAM_WIDTH" value="16 Bits" />
+ <set param="PCW::UIPARAM::DDR::DEVICE_CAPACITY" value="4096 MBits" />
+ <set param="PCW::UIPARAM::DDR::SPEED_BIN" value="DDR3_1066F" />
+ <set param="PCW::UIPARAM::DDR::ROW_ADDR_COUNT" value="15" />
+ <set param="PCW::UIPARAM::DDR::CWL" value="6" />
+ <set param="PCW::UIPARAM::DDR::T_RC" value="48.91" />
+ <set param="PCW::UIPARAM::DDR::T_RAS_MIN" value="35.0" />
+ <set param="PCW::UIPARAM::DDR::T_FAW" value="40.0" />
+ <set param="PCW::MIO::MIO[0]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[0]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[1]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[2]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[3]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[4]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[5]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[6]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[7]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[8]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[8]::DIRECTION" value="out" />
+ <set param="PCW::MIO::MIO[9]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[9]::DIRECTION" value="in" />
+ <set param="PCW::MIO::MIO[10]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[11]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[12]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[13]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[14]::IOTYPE" value="LVCMOS 3.3V" />
+ <set param="PCW::MIO::MIO[15]::IOTYPE" value="LVCMOS 3.3V" />
<set param="PCW::MIO::MIO[16]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[16]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[16]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[16]::DIRECTION" value="out" />
<set param="PCW::MIO::MIO[17]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[17]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[17]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[17]::DIRECTION" value="out" />
<set param="PCW::MIO::MIO[18]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[18]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[18]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[18]::DIRECTION" value="out" />
<set param="PCW::MIO::MIO[19]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[19]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[19]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[19]::DIRECTION" value="out" />
<set param="PCW::MIO::MIO[20]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[20]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[20]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[20]::DIRECTION" value="out" />
<set param="PCW::MIO::MIO[21]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[21]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[21]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[21]::DIRECTION" value="out" />
<set param="PCW::MIO::MIO[22]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[22]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[22]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[22]::DIRECTION" value="in" />
<set param="PCW::MIO::MIO[23]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[23]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[23]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[23]::DIRECTION" value="in" />
<set param="PCW::MIO::MIO[24]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[24]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[24]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[24]::DIRECTION" value="in" />
<set param="PCW::MIO::MIO[25]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[25]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[25]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[25]::DIRECTION" value="in" />
<set param="PCW::MIO::MIO[26]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[26]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[26]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[26]::DIRECTION" value="in" />
<set param="PCW::MIO::MIO[27]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[27]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[27]::PULLUP" value="disabled" />
+ <set param="PCW::MIO::MIO[27]::DIRECTION" value="in" />
<set param="PCW::MIO::MIO[28]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[28]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[29]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[29]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[30]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[30]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[31]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[31]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[32]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[32]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[33]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[33]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[34]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[34]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[35]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[35]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[36]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[36]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[37]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[37]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[38]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[38]::IOTYPE" value="LVCMOS 2.5V" />
<set param="PCW::MIO::MIO[39]::SLEW" value="fast" />
+ <set param="PCW::MIO::MIO[39]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[40]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[41]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[42]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[43]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[44]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[45]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[46]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[47]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[48]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[49]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[50]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[51]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[52]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[52]::DIRECTION" value="out" />
+ <set param="PCW::MIO::MIO[53]::IOTYPE" value="LVCMOS 2.5V" />
+ <set param="PCW::MIO::MIO[53]::DIRECTION" value="inout" />
</project>
diff --git a/cores/axis_bram_reader_v1_0/axis_bram_reader.vhd b/cores/axis_bram_reader_v1_0/axis_bram_reader.vhd
index 54ca5a9..4235060 100644
--- a/cores/axis_bram_reader_v1_0/axis_bram_reader.vhd
+++ b/cores/axis_bram_reader_v1_0/axis_bram_reader.vhd
@@ -5,86 +5,107 @@ use ieee.numeric_std.all;
entity axis_bram_reader is
generic (
- BRAM_ADDR_WIDTH : natural := 10;
- BRAM_DATA_WIDTH : natural := 32;
- AXIS_TDATA_WIDTH : natural := 32
- );
+ CONTINUOUS : string := "FALSE";
+ BRAM_ADDR_WIDTH : natural := 10;
+ BRAM_DATA_WIDTH : natural := 32;
+ AXIS_TDATA_WIDTH : natural := 32
+ );
port (
- -- System signals
- aclk : in std_logic;
- aresetn : in std_logic;
-
- cfg_data : in std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
- sts_data : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
-
- -- Master side
- m_axis_tready : in std_logic;
- m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
- m_axis_tvalid : out std_logic;
- m_axis_tlast : out std_logic;
-
- --m_axis_config_tready : in std_logic;
- --m_axis_config_tvalid : out std_logic;
-
- -- BRAM port
- bram_porta_clk : out std_logic;
- bram_porta_rst : out std_logic;
- bram_porta_addr : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
- bram_porta_rddata: in std_logic_vector(BRAM_DATA_WIDTH-1 downto 0)
- );
+ -- System signals
+ aclk : in std_logic;
+ aresetn : in std_logic;
+
+ cfg_data : in std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+ sts_data : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+
+ -- Master side
+ m_axis_tready : in std_logic;
+ m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+ m_axis_tvalid : out std_logic;
+ m_axis_tlast : out std_logic;
+
+ m_axis_config_tready : in std_logic;
+ m_axis_config_tvalid : out std_logic;
+
+ -- BRAM port
+ bram_porta_clk : out std_logic;
+ bram_porta_rst : out std_logic;
+ bram_porta_addr : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+ bram_porta_rddata: in std_logic_vector(BRAM_DATA_WIDTH-1 downto 0)
+);
end axis_bram_reader;
architecture rtl of axis_bram_reader is
- signal addr_reg, addr_next : unsigned(BRAM_ADDR_WIDTH-1 downto 0);
- signal addr_dly_reg, addr_dly_next : unsigned(BRAM_ADDR_WIDTH-1 downto 0);
- signal tlast_reg, tlast_next : std_logic;
- signal comp_reg, comp_next : std_logic;
+ signal int_addr_reg,
+ int_addr_next,
+ sum_cntr_wire,
+ int_data_reg : std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+ signal int_comp_wire,
+ int_tlast_wire,
+ int_enbl_reg,
+ int_enbl_next,
+ int_conf_reg,
+ int_conf_next : std_logic;
begin
-
+
process(aclk)
begin
if rising_edge(aclk) then
if aresetn = '0' then
- addr_reg <= (others => '0');
- comp_reg <= '0';
- addr_dly_reg <= (others => '0');
- tlast_reg <= '0';
+ int_addr_reg <= (others => '0');
+ int_data_reg <= (others => '0');
+ int_enbl_reg <= '0';
+ int_conf_reg <= '0';
else
- addr_reg <= addr_next;
- comp_reg <= comp_next;
- addr_dly_reg <= addr_dly_next;
- tlast_reg <= tlast_next;
+ int_addr_reg <= int_addr_next;
+ int_data_reg <= cfg_data;
+ int_enbl_reg <= int_enbl_next;
+ int_conf_reg <= int_conf_next;
end if;
- end if;
+ end if;
end process;
-
+
-- Next state logic
- comp_next <= '0' when (addr_reg = unsigned(cfg_data)) else
- '1';
+ sum_cntr_wire <= std_logic_vector(unsigned(int_addr_reg) + 1);
+ int_comp_wire <= '1' when (unsigned(int_addr_reg) < unsigned(int_data_reg)) else '0';
+ int_tlast_wire <= not int_comp_wire;
- tlast_next <= '1' when (addr_reg = unsigned(cfg_data)-1) else
- '0';
+ CONTINUOUS_G: if (CONTINUOUS = "TRUE") generate
+ begin
+ int_addr_next <= sum_cntr_wire when (m_axis_tready = '1' and int_enbl_reg = '1' and int_comp_wire = '1') else
+ (others => '0') when (m_axis_tready = '1' and int_enbl_reg = '1' and int_tlast_wire = '1') else
+ int_addr_reg;
- addr_next <= addr_reg + 1 when (m_axis_tready = '1') and (comp_reg = '1') else
- (others => '0') when (comp_reg = '0') else
- addr_reg;
+ int_enbl_next <= '1' when (int_enbl_reg = '0' and int_comp_wire = '1') else
+ int_enbl_reg;
+ end generate;
+
+ STOP_G: if (CONTINUOUS = "FALSE") generate
+ begin
+ int_addr_next <= sum_cntr_wire when (m_axis_tready = '1' and int_enbl_reg = '1' and int_comp_wire = '1') else
+ int_addr_reg;
- addr_dly_next <= addr_reg;
+ int_enbl_next <= '1' when (int_enbl_reg = '0' and int_comp_wire = '1') else
+ '0' when (m_axis_tready = '1' and int_enbl_reg = '1' and int_tlast_wire = '1') else
+ int_enbl_reg;
+ int_conf_next <= '1' when (m_axis_tready = '1' and int_enbl_reg = '1' and int_tlast_wire = '1') else
+ '0' when (int_conf_reg = '1' and m_axis_config_tready = '1') else
+ int_conf_reg;
+ end generate;
- --tvalid_next <= '1' when (tvalid_reg = '0') and (comp_reg = '1') else
- -- '0' when
- -- tvalid_reg;
+ sts_data <= int_addr_reg;
- sts_data <= std_logic_vector(addr_dly_reg);
+ m_axis_tdata <= bram_porta_rddata;
+ m_axis_tvalid <= int_enbl_reg;
+ m_axis_tlast <= '1' when (int_enbl_reg = '1' and int_tlast_wire = '1') else '0';
- m_axis_tdata <= bram_porta_rddata;
- m_axis_tvalid <= comp_reg;
- m_axis_tlast <= tlast_reg;
+ m_axis_config_tvalid <= int_conf_reg;
bram_porta_clk <= aclk;
bram_porta_rst <= not aresetn;
- bram_porta_addr <= std_logic_vector(addr_next);
+ bram_porta_addr <= int_addr_next when (m_axis_tready = '1' and int_enbl_reg = '1') else
+ int_addr_reg;
end rtl;
diff --git a/cores/axis_bram_reader_v1_0/core_config.tcl b/cores/axis_bram_reader_v1_0/core_config.tcl
index bc9d829..a0dd860 100644
--- a/cores/axis_bram_reader_v1_0/core_config.tcl
+++ b/cores/axis_bram_reader_v1_0/core_config.tcl
@@ -8,14 +8,19 @@ set_property DESCRIPTION $display_name $core
core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the M_AXIS data bus.}
core_parameter BRAM_DATA_WIDTH {BRAM DATA WIDTH} {Width of the BRAM data port.}
core_parameter BRAM_ADDR_WIDTH {BRAM ADDR WIDTH} {Width of the BRAM address port.}
+core_parameter CONTINUOUS {CONTINUOUS} {If TRUE, reader runs continuously.}
set bus [ipx::get_bus_interfaces -of_objects $core m_axis]
set_property NAME M_AXIS $bus
set_property INTERFACE_MODE master $bus
+set bus [ipx::get_bus_interfaces -of_objects $core m_axis_config]
+set_property NAME M_AXIS_CONFIG $bus
+set_property INTERFACE_MODE master $bus
+
set bus [ipx::get_bus_interfaces aclk]
set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
-set_property VALUE M_AXIS $parameter
+set_property VALUE M_AXIS:M_AXIS_CONFIG $parameter
set bus [ipx::add_bus_interface BRAM_PORTA $core]
set_property ABSTRACTION_TYPE_VLNV xilinx.com:interface:bram_rtl:1.0 $bus
diff --git a/cores/axis_bram_writer_v1_0/axis_bram_writer.vhd b/cores/axis_bram_writer_v1_0/axis_bram_writer.vhd
index ac290e4..977cdc1 100644
--- a/cores/axis_bram_writer_v1_0/axis_bram_writer.vhd
+++ b/cores/axis_bram_writer_v1_0/axis_bram_writer.vhd
@@ -5,35 +5,35 @@ use ieee.numeric_std.all;
entity axis_bram_writer is
generic (
- BRAM_ADDR_WIDTH : natural := 10;
- BRAM_DATA_WIDTH : natural := 32;
- AXIS_TDATA_WIDTH : natural := 32
- );
+ BRAM_ADDR_WIDTH : natural := 10;
+ BRAM_DATA_WIDTH : natural := 32;
+ AXIS_TDATA_WIDTH : natural := 32
+ );
port (
- -- System signals
- aclk : in std_logic;
- aresetn : in std_logic;
+ -- System signals
+ aclk : in std_logic;
+ aresetn : in std_logic;
+
+ sts_data : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
- sts_data : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+ -- Slave side
+ s_axis_tready : out std_logic;
+ s_axis_tdata : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+ s_axis_tvalid : in std_logic;
- -- Slave side
- s_axis_tready : out std_logic;
- s_axis_tdata : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
- s_axis_tvalid : in std_logic;
-
- -- BRAM port
- bram_porta_clk : out std_logic;
- bram_porta_rst : out std_logic;
- bram_porta_addr : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
- bram_porta_wrdata: out std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
- bram_porta_we : out std_logic_vector(BRAM_DATA_WIDTH/8-1 downto 0)
- );
+ -- BRAM port
+ bram_porta_clk : out std_logic;
+ bram_porta_rst : out std_logic;
+ bram_porta_addr : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+ bram_porta_wrdata: out std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
+ bram_porta_we : out std_logic_vector(BRAM_DATA_WIDTH/8-1 downto 0)
+);
end axis_bram_writer;
architecture rtl of axis_bram_writer is
- signal addr_reg, addr_next : std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
- signal enbl_reg, enbl_next : std_logic;
- signal s_aux1 : std_logic;
+ signal int_addr_reg, int_addr_next : std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+ signal int_enbl_reg, int_enbl_next : std_logic;
+ signal s_aux1 : std_logic;
begin
@@ -41,33 +41,32 @@ begin
begin
if rising_edge(aclk) then
if (aresetn = '0') then
- addr_reg <= (others => '0');
- enbl_reg <= '0';
+ int_addr_reg <= (others => '0');
+ int_enbl_reg <= '0';
else
- addr_reg <= addr_next;
- enbl_reg <= enbl_next;
+ int_addr_reg <= int_addr_next;
+ int_enbl_reg <= int_enbl_next;
end if;
end if;
end process;
-- Next state logic
- enbl_next <= '1' when enbl_reg = '0' else
- enbl_reg;
+ int_addr_next <= std_logic_vector(unsigned(int_addr_reg)+1) when (s_axis_tvalid = '1') and (int_enbl_reg = '1') else
+ int_addr_reg;
- addr_next <= std_logic_vector(unsigned(addr_reg)+1) when (s_axis_tvalid = '1') and (enbl_reg = '1') else
- addr_reg;
+ int_enbl_next <= '1' when int_enbl_reg = '0' else
+ int_enbl_reg;
- sts_data <= addr_reg;
+ sts_data <= int_addr_reg;
- s_axis_tready <= enbl_reg;
+ s_axis_tready <= int_enbl_reg;
- s_aux1 <= '1' when (s_axis_tvalid = '1') and (enbl_reg = '1') else
- '0';
+ s_aux1 <= s_axis_tvalid and int_enbl_reg;
- bram_porta_clk <= aclk;
- bram_porta_rst <= not aresetn;
- bram_porta_addr <= addr_reg;
+ bram_porta_clk <= aclk;
+ bram_porta_rst <= not aresetn;
+ bram_porta_addr <= int_addr_reg;
bram_porta_wrdata <= s_axis_tdata;
- bram_porta_we <= ((BRAM_DATA_WIDTH/8-1) downto 0 => s_aux1);
+ bram_porta_we <= ((BRAM_DATA_WIDTH/8-1) downto 0 => s_aux1);
end rtl;
diff --git a/cores/axis_constant_v1_0/axis_constant.vhd b/cores/axis_constant_v1_0/axis_constant.vhd
index 96a1ab1..049f27e 100644
--- a/cores/axis_constant_v1_0/axis_constant.vhd
+++ b/cores/axis_constant_v1_0/axis_constant.vhd
@@ -5,24 +5,24 @@ use ieee.numeric_std.all;
entity axis_constant is
generic (
- AXIS_TDATA_WIDTH: natural := 32
- );
- port (
- -- System signals
- aclk : in std_logic;
-
- cfg_data : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
-
- -- Master side
- m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
- m_axis_tvalid : out std_logic
- );
+ AXIS_TDATA_WIDTH: natural := 32
+);
+port (
+ -- System signals
+ aclk : in std_logic;
+
+ cfg_data : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+
+ -- Master side
+ m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+ m_axis_tvalid : out std_logic
+);
end axis_constant;
architecture rtl of axis_constant is
begin
-
+
m_axis_tdata <= cfg_data;
m_axis_tvalid <= '1';
diff --git a/cores/axis_counter_v1_0/axis_counter.vhd b/cores/axis_counter_v1_0/axis_counter.vhd
index 6017cdb..7599db0 100644
--- a/cores/axis_counter_v1_0/axis_counter.vhd
+++ b/cores/axis_counter_v1_0/axis_counter.vhd
@@ -5,22 +5,22 @@ use ieee.numeric_std.all;
entity axis_counter is
generic (
- AXIS_TDATA_WIDTH : natural := 32;
- CNTR_WIDTH : natural := 32
- );
- port (
- -- System signals
- aclk : in std_logic;
- aresetn : in std_logic;
-
- cfg_data : in std_logic_vector(CNTR_WIDTH-1 downto 0);
-
- -- Master side
- m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
- m_axis_tlast : out std_logic;
- m_axis_tready : in std_logic;
- m_axis_tvalid : out std_logic
- );
+ AXIS_TDATA_WIDTH : natural := 32;
+ CNTR_WIDTH : natural := 32
+);
+port (
+ -- System signals
+ aclk : in std_logic;
+ aresetn : in std_logic;
+
+ cfg_data : in std_logic_vector(CNTR_WIDTH-1 downto 0);
+
+ -- Master side
+ m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+ m_axis_tlast : out std_logic;
+ m_axis_tready : in std_logic;
+ m_axis_tvalid : out std_logic
+);
end axis_counter;
architecture rtl of axis_counter is
@@ -34,21 +34,21 @@ begin
process(aclk)
begin
if (rising_edge(aclk)) then
- if(aresetn = '0') then
- cntr_reg <= (others => '0');
- tlast_reg <= '0';
- comp_reg <= '0';
- else
- cntr_reg <= cntr_next;
- tlast_reg <= tlast_next;
- comp_reg <= comp_next;
- end if;
+ if(aresetn = '0') then
+ cntr_reg <= (others => '0');
+ tlast_reg <= '0';
+ comp_reg <= '0';
+ else
+ cntr_reg <= cntr_next;
+ tlast_reg <= tlast_next;
+ comp_reg <= comp_next;
+ end if;
end if;
end process;
- tlast_next <= '1' when (cntr_reg = unsigned(cfg_data)-2) else '0';
+ tlast_next <= '1' when (cntr_reg = unsigned(cfg_data)-1) else '0';
- comp_next <= '0' when (cntr_reg = unsigned(cfg_data)-1) else '1';
+ comp_next <= '0' when (cntr_reg = unsigned(cfg_data)) else '1';
cntr_next <= cntr_reg + 1 when ((comp_reg = '1') and (m_axis_tready = '1')) else
(others => '0') when (comp_reg = '0') else --reset
diff --git a/cores/axis_gpio_reader_v1_0/axis_gpio_reader.vhd b/cores/axis_gpio_reader_v1_0/axis_gpio_reader.vhd
index 9b57a63..3021f70 100644
--- a/cores/axis_gpio_reader_v1_0/axis_gpio_reader.vhd
+++ b/cores/axis_gpio_reader_v1_0/axis_gpio_reader.vhd
@@ -8,18 +8,18 @@ use unisim.vcomponents.all;
entity axis_gpio_reader is
generic (
- AXIS_TDATA_WIDTH: natural := 32
- );
- port (
- -- System signals
- aclk : in std_logic;
-
- gpio_data : inout std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
-
- -- Master side
- m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
- m_axis_tvalid : out std_logic
- );
+ AXIS_TDATA_WIDTH: natural := 32
+);
+port (
+ -- System signals
+ aclk : in std_logic;
+
+ gpio_data : inout std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+
+ -- Master side
+ m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+ m_axis_tvalid : out std_logic
+);
end axis_gpio_reader;
architecture rtl of axis_gpio_reader is
@@ -31,20 +31,20 @@ architecture rtl of axis_gpio_reader is
begin
GPIO_G: for j in 0 to AXIS_TDATA_WIDTH-1 generate
- IOBUF_int: IOBUF
- port map(
- O => int_data_wire(j),
- IO => gpio_data(j),
- I => '0',
- T => '1'
- );
+ IOBUF_int: IOBUF
+ port map(
+ O => int_data_wire(j),
+ IO => gpio_data(j),
+ I => '0',
+ T => '1'
+ );
end generate;
process(aclk)
begin
if (rising_edge(aclk)) then
- int_data_reg(0) <= int_data_wire;
- int_data_reg(1) <= int_data_reg(0);
+ int_data_reg(0) <= int_data_wire;
+ int_data_reg(1) <= int_data_reg(0);
end if;
end process;
diff --git a/cores/axis_lago_trigger_v1_0/core_config.tcl b/cores/axis_lago_trigger_v1_0/core_config.tcl
index d7a1051..46daa0a 100644
--- a/cores/axis_lago_trigger_v1_0/core_config.tcl
+++ b/cores/axis_lago_trigger_v1_0/core_config.tcl
@@ -1,4 +1,4 @@
-set display_name {AXI4-Stream LAGO Trigger v1r0}
+set display_name {AXI4-Stream LAGO Trigger}
set core [ipx::current_core]
diff --git a/cores/axis_lago_trigger_v1_1/core_config.tcl b/cores/axis_lago_trigger_v1_1/core_config.tcl
index 3e7f5b3..46daa0a 100644
--- a/cores/axis_lago_trigger_v1_1/core_config.tcl
+++ b/cores/axis_lago_trigger_v1_1/core_config.tcl
@@ -1,4 +1,4 @@
-set display_name {AXI4-Stream LAGO Trigger v1r1}
+set display_name {AXI4-Stream LAGO Trigger}
set core [ipx::current_core]
diff --git a/cores/axis_ram_writer_v1_0/axis_ram_writer.vhd b/cores/axis_ram_writer_v1_0/axis_ram_writer.vhd
index 8203039..5a6e230 100644
--- a/cores/axis_ram_writer_v1_0/axis_ram_writer.vhd
+++ b/cores/axis_ram_writer_v1_0/axis_ram_writer.vhd
@@ -8,44 +8,44 @@ use unisim.vcomponents.all;
entity axis_ram_writer is
generic (
- ADDR_WIDTH : natural := 20;
- AXI_ID_WIDTH : natural := 6;
- AXI_ADDR_WIDTH : natural := 32;
- AXI_DATA_WIDTH : natural := 64;
- AXIS_TDATA_WIDTH : natural := 64
- );
+ ADDR_WIDTH : natural := 20;
+ AXI_ID_WIDTH : natural := 6;
+ AXI_ADDR_WIDTH : natural := 32;
+ AXI_DATA_WIDTH : natural := 64;
+ AXIS_TDATA_WIDTH : natural := 64
+ );
port (
- -- System signals
- aclk : in std_logic;
- aresetn : in std_logic;
-
- -- Configuration bits
- cfg_data : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);
- sts_data : out std_logic_vector(ADDR_WIDTH-1 downto 0);
-
- -- Master side
- m_axi_awid : out std_logic_vector(AXI_ID_WIDTH-1 downto 0); -- AXI master: Write address ID
- m_axi_awaddr : out std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); -- AXI master: Write address
- m_axi_awlen : out std_logic_vector(3 downto 0); -- AXI master: Write burst length
- m_axi_awsize : out std_logic_vector(2 downto 0); -- AXI master: Write burst size
- m_axi_awburst : out std_logic_vector(1 downto 0); -- AXI master: Write burst type
- m_axi_awcache : out std_logic_vector(3 downto 0); -- AXI master: Write memory type
- m_axi_awvalid : out std_logic; -- AXI master: Write address valid
- m_axi_awready : in std_logic; -- AXI master: Write address ready
- m_axi_wid : out std_logic_vector(AXI_ID_WIDTH-1 downto 0); -- AXI master: Write data ID
- m_axi_wdata : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0); -- AXI master: Write data
- m_axi_wstrb : out std_logic_vector(AXI_DATA_WIDTH/8-1 downto 0); -- AXI master: Write strobes
- m_axi_wlast : out std_logic; -- AXI master: Write last
- m_axi_wvalid : out std_logic; -- AXI master: Write valid
- m_axi_wready : in std_logic; -- AXI master: Write ready
- m_axi_bvalid : in std_logic; -- AXI master: Write response valid
- m_axi_bready : out std_logic; -- AXI master: Write response ready
-
- -- Slave side
- s_axis_tready : out std_logic;
- s_axis_tdata : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
- s_axis_tvalid : in std_logic
- );
+ -- System signals
+ aclk : in std_logic;
+ aresetn : in std_logic;
+
+ -- Configuration bits
+ cfg_data : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);
+ sts_data : out std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+ -- Master side
+ m_axi_awid : out std_logic_vector(AXI_ID_WIDTH-1 downto 0); -- AXI master: Write address ID
+ m_axi_awaddr : out std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); -- AXI master: Write address
+ m_axi_awlen : out std_logic_vector(3 downto 0); -- AXI master: Write burst length
+ m_axi_awsize : out std_logic_vector(2 downto 0); -- AXI master: Write burst size
+ m_axi_awburst : out std_logic_vector(1 downto 0); -- AXI master: Write burst type
+ m_axi_awcache : out std_logic_vector(3 downto 0); -- AXI master: Write memory type
+ m_axi_awvalid : out std_logic; -- AXI master: Write address valid
+ m_axi_awready : in std_logic; -- AXI master: Write address ready
+ m_axi_wid : out std_logic_vector(AXI_ID_WIDTH-1 downto 0); -- AXI master: Write data ID
+ m_axi_wdata : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0); -- AXI master: Write data
+ m_axi_wstrb : out std_logic_vector(AXI_DATA_WIDTH/8-1 downto 0); -- AXI master: Write strobes
+ m_axi_wlast : out std_logic; -- AXI master: Write last
+ m_axi_wvalid : out std_logic; -- AXI master: Write valid
+ m_axi_wready : in std_logic; -- AXI master: Write ready
+ m_axi_bvalid : in std_logic; -- AXI master: Write response valid
+ m_axi_bready : out std_logic; -- AXI master: Write response ready
+
+ -- Slave side
+ s_axis_tready : out std_logic;
+ s_axis_tdata : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+ s_axis_tvalid : in std_logic
+);
end axis_ram_writer;
architecture rtl of axis_ram_writer is
@@ -58,7 +58,7 @@ architecture rtl of axis_ram_writer is
ret_val := ret_val + 1;
temp := temp / 2;
end loop;
- return ret_val;
+ return ret_val;
end function;
constant ADDR_SIZE : natural := clogb2((AXI_DATA_WIDTH/8) - 1);
@@ -67,16 +67,16 @@ architecture rtl of axis_ram_writer is
signal int_wvalid_reg, int_wvalid_next : std_logic;
signal int_addr_reg, int_addr_next : unsigned(ADDR_WIDTH-1 downto 0);
signal int_wid_reg, int_wid_next : unsigned(AXI_ID_WIDTH-1 downto 0);
-
+
signal int_full_wire, int_empty_wire, int_rden_wire : std_logic;
signal int_wlast_wire, int_tready_wire : std_logic;
signal int_wdata_wire : std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
-
+
signal tmp_s2 : std_logic;
signal reset : std_logic;
begin
-
+
int_tready_wire <= not int_full_wire;
int_wlast_wire <= '1' when (int_addr_reg(3 downto 0) = "1111") else '0';
int_rden_wire <= m_axi_wready and int_wvalid_reg;
@@ -86,59 +86,59 @@ begin
FIFO36E1_inst: FIFO36E1
generic map(
- FIRST_WORD_FALL_THROUGH => TRUE,
- ALMOST_EMPTY_OFFSET => X"000F",
- DATA_WIDTH => 72,
- FIFO_MODE => "FIFO36_72"
- )
+ FIRST_WORD_FALL_THROUGH => TRUE,
+ ALMOST_EMPTY_OFFSET => X"000F",
+ DATA_WIDTH => 72,
+ FIFO_MODE => "FIFO36_72"
+ )
port map (
- ALMOSTEMPTY => int_empty_wire,
- ALMOSTFULL => open,
- EMPTY => open,
- FULL => int_full_wire,
- DOP => open,
- DO => int_wdata_wire,
- INJECTDBITERR => '0',
- INJECTSBITERR => '0',
- RDCLK => aclk,
- RDEN => int_rden_wire,
- REGCE => '1',
- RST => reset,
- RSTREG => '0',
- WRCLK => aclk,
- WREN => tmp_s2,
- DI => s_axis_tdata,
- DIP => X"00"
- );
+ ALMOSTEMPTY => int_empty_wire,
+ ALMOSTFULL => open,
+ EMPTY => open,
+ FULL => int_full_wire,
+ DOP => open,
+ DO => int_wdata_wire,
+ INJECTDBITERR => '0',
+ INJECTSBITERR => '0',
+ RDCLK => aclk,
+ RDEN => int_rden_wire,
+ REGCE => '1',
+ RST => reset,
+ RSTREG => '0',
+ WRCLK => aclk,
+ WREN => tmp_s2,
+ DI => s_axis_tdata,
+ DIP => X"00"
+ );
process(aclk)
begin
- if (rising_edge(aclk)) then
- if (reset = '1') then
- int_awvalid_reg <= '0';
- int_wvalid_reg <= '0';
- int_addr_reg <= (others => '0');
- int_wid_reg <= (others => '0');
- else
- int_awvalid_reg <= int_awvalid_next;
- int_wvalid_reg <= int_wvalid_next;
- int_addr_reg <= int_addr_next;
- int_wid_reg <= int_wid_next;
- end if;
- end if;
+ if (rising_edge(aclk)) then
+ if (reset = '1') then
+ int_awvalid_reg <= '0';
+ int_wvalid_reg <= '0';
+ int_addr_reg <= (others => '0');
+ int_wid_reg <= (others => '0');
+ else
+ int_awvalid_reg <= int_awvalid_next;
+ int_wvalid_reg <= int_wvalid_next;
+ int_addr_reg <= int_addr_next;
+ int_wid_reg <= int_wid_next;
+ end if;
+ end if;
end process;
int_awvalid_next <= '1' when ((int_empty_wire = '0') and (int_awvalid_reg = '0') and (int_wvalid_reg = '0')) or
((m_axi_wready = '1') and (int_wlast_wire = '1') and (int_empty_wire = '0')) else
- '0' when ((m_axi_awready = '1') and (int_awvalid_reg = '1')) else
- int_awvalid_reg;
+ '0' when ((m_axi_awready = '1') and (int_awvalid_reg = '1')) else
+ int_awvalid_reg;
int_wvalid_next <= '1' when ((int_empty_wire = '0') and (int_awvalid_reg = '0') and (int_wvalid_reg = '0')) else
'0' when (m_axi_wready = '1') and (int_wlast_wire = '1') and (int_empty_wire = '1') else
- int_wvalid_reg;
+ int_wvalid_reg;
int_addr_next <= int_addr_reg + 1 when (int_rden_wire = '1') else
- int_addr_reg;
+ int_addr_reg;
int_wid_next <= int_wid_reg + 1 when (m_axi_wready = '1') and (int_wlast_wire = '1') else
int_wid_reg;
diff --git a/cores/axis_trigger_v1_0/axis_trigger.vhd b/cores/axis_trigger_v1_0/axis_trigger.vhd
index 279b700..4ba83df 100644
--- a/cores/axis_trigger_v1_0/axis_trigger.vhd
+++ b/cores/axis_trigger_v1_0/axis_trigger.vhd
@@ -5,33 +5,33 @@ use ieee.numeric_std.all;
entity axis_trigger is
generic (
- AXIS_TDATA_WIDTH : natural := 32;
- AXIS_TDATA_SIGNED : string := "FALSE"
- );
- port (
- -- System signals
- aclk : in std_logic;
-
- pol_data : in std_logic;
- msk_data : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
- lvl_data : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
-
- trg_flag : out std_logic;
-
- -- Slave side
- s_axis_tready: out std_logic;
- s_axis_tdata : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
- s_axis_tvalid: in std_logic
- );
+ AXIS_TDATA_WIDTH : natural := 32;
+ AXIS_TDATA_SIGNED : string := "FALSE"
+);
+port (
+ -- System signals
+ aclk: in std_logic;
+
+ pol_data : in std_logic;
+ msk_data : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+ lvl_data : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+
+ trg_flag : out std_logic;
+
+ -- Slave side
+ s_axis_tready : out std_logic;
+ s_axis_tdata : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+ s_axis_tvalid : in std_logic
+);
end axis_trigger;
architecture rtl of axis_trigger is
signal int_comp_reg : std_logic_vector(1 downto 0);
- signal int_comp_wire: std_logic;
+ signal int_comp_wire : std_logic;
begin
-
+
SIGNED_G: if (AXIS_TDATA_SIGNED = "TRUE") generate
int_comp_wire <= '1' when signed(s_axis_tdata and msk_data) >= signed(lvl_data) else '0';
end generate;
@@ -42,11 +42,11 @@ begin
process(aclk)
begin
- if (rising_edge(aclk)) then
- if (s_axis_tvalid = '1') then
- int_comp_reg <= int_comp_reg(0) & int_comp_wire;
- end if;
+ if (rising_edge(aclk)) then
+ if (s_axis_tvalid = '1') then
+ int_comp_reg <= int_comp_reg(0) & int_comp_wire;
end if;
+ end if;
end process;
s_axis_tready <= '1';
diff --git a/cores/pps_gen_v1_0/pps_gen.vhd b/cores/pps_gen_v1_0/pps_gen.vhd
index 6e47916..9c78198 100644
--- a/cores/pps_gen_v1_0/pps_gen.vhd
+++ b/cores/pps_gen_v1_0/pps_gen.vhd
@@ -8,7 +8,7 @@ use unisim.vcomponents.all;
entity pps_gen is
generic (
- CLK_FREQ : natural := 125000000
+ CLK_FREQ : natural := 142857132
);
port (
-- System signals
diff --git a/patches/devicetree.patch b/patches/devicetree.patch
index 975e25f..eb1b0a4 100644
--- a/patches/devicetree.patch
+++ b/patches/devicetree.patch
@@ -86,3 +86,11 @@ diff -rupN system-top.dts.old system-top.dts
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
+@@ -24,6 +36,6 @@
+ };
+ memory {
+ device_type = "memory";
+- reg = <0x0 0x20000000>;
++ reg = <0x0 0x1E000000>;
+ };
+ };
diff --git a/patches/xilinx_zynq_defconfig b/patches/xilinx_zynq_defconfig
index d319f13..8cd953f 100644
--- a/patches/xilinx_zynq_defconfig
+++ b/patches/xilinx_zynq_defconfig
@@ -8,6 +8,8 @@ CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
CONFIG_BPF_SYSCALL=y
# CONFIG_BUG is not set
CONFIG_EMBEDDED=y
@@ -25,9 +27,9 @@ CONFIG_ARM_ERRATA_775420=y
CONFIG_SMP=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_SMT=y
-CONFIG_BIG_LITTLE=y
-CONFIG_BL_SWITCHER=y
CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
@@ -107,10 +109,10 @@ CONFIG_R8169=y
# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_XILINX_EMACLITE=y
CONFIG_XILINX_AXI_EMAC=y
+CONFIG_MDIO_BITBANG=y
CONFIG_MARVELL_PHY=y
CONFIG_VITESSE_PHY=y
CONFIG_INTEL_XWAY_PHY=y
-CONFIG_MDIO_BITBANG=y
CONFIG_INPUT_SPARSEKMAP=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
@@ -141,6 +143,9 @@ CONFIG_XILINX_WATCHDOG=y
CONFIG_CADENCE_WATCHDOG=y
CONFIG_REGULATOR=y
CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_V4L_PLATFORM_DRIVERS=y
CONFIG_VIDEO_XILINX=y
CONFIG_VIDEO_XILINX_CFA=y
@@ -165,7 +170,6 @@ CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
CONFIG_USB_STORAGE=y
-CONFIG_USB_UAS=m
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
CONFIG_USB_CHIPIDEA_HOST=y
@@ -197,9 +201,9 @@ CONFIG_EDAC=y
CONFIG_EDAC_SYNOPSYS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PCF8563=y
-CONFIG_DMADEVICES=y
CONFIG_PL330_DMA=y
CONFIG_XILINX_DMA=y
+CONFIG_XILINX_DMA_ENGINES=y
CONFIG_UIO=y
CONFIG_UIO_PDRV_GENIRQ=y
CONFIG_UIO_XILINX_APM=y
diff --git a/patches/zynq-red-pitaya.dts b/patches/zynq-red-pitaya.dts
index 1b40963..a3ed99c 100644
--- a/patches/zynq-red-pitaya.dts
+++ b/patches/zynq-red-pitaya.dts
@@ -18,7 +18,7 @@
memory@0 {
device_type = "memory";
- reg = <0x0 0x20000000>;
+ reg = <0x0 0x1E000000>;
};
chosen {
diff --git a/patches/zynq_red_pitaya_defconfig b/patches/zynq_red_pitaya_defconfig
index 6b6197b..13e5f92 100644
--- a/patches/zynq_red_pitaya_defconfig
+++ b/patches/zynq_red_pitaya_defconfig
@@ -1,24 +1,62 @@
CONFIG_ARM=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x4000000
+CONFIG_SPL_STACK_R_ADDR=0x200000
+CONFIG_ENV_SIZE=0x400
+CONFIG_ENV_OFFSET=0x1800
+CONFIG_SPL=y
+CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_CUSTOM_LDSCRIPT=y
CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
-CONFIG_DEFAULT_DEVICE_TREE="zynq-red-pitaya"
-CONFIG_DISTRO_DEFAULTS=y
+CONFIG_USE_PREBOOT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADFS=y
+CONFIG_CMD_FPGA_LOADMK=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
-CONFIG_ENV_OVERWRITE=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_DEFAULT_DEVICE_TREE="zynq-red-pitaya"
CONFIG_ENV_IS_IN_EEPROM=y
-CONFIG_ENV_OFFSET=0x1800
-CONFIG_ENV_SIZE=0x400
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQPL=y
+CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CADENCE=y
-CONFIG_SYS_I2C_EEPROM_ADDR=0x50
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
+CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
-CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_PHY_LANTIQ=y
+CONFIG_PHY_XILINX=y
+CONFIG_MII=y
CONFIG_ZYNQ_GEM=y
CONFIG_ZYNQ_SERIAL=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03fd
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_THOR=y
diff --git a/projects/adc_recorder/adc-recorder.c b/projects/adc_recorder/adc-recorder.c
index 388d582..c8c6e7b 100644
--- a/projects/adc_recorder/adc-recorder.c
+++ b/projects/adc_recorder/adc-recorder.c
@@ -1,70 +1,44 @@
#include <stdio.h>
#include <stdint.h>
-#include <stdlib.h>
#include <unistd.h>
-#include <fcntl.h>
#include <sys/mman.h>
-#include <sys/ioctl.h>
-
-#define CMA_ALLOC _IOWR('Z', 0, uint32_t)
+#include <fcntl.h>
int main()
{
int fd, i;
- volatile uint8_t *rst;
- volatile void *cfg;
- volatile int16_t *ram;
- uint32_t size;
int16_t value[2];
+ void *cfg, *ram;
+ char *name = "/dev/mem";
- if((fd = open("/dev/mem", O_RDWR)) < 0)
+ if((fd = open(name, O_RDWR)) < 0)
{
perror("open");
- return EXIT_FAILURE;
+ return 1;
}
cfg = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x40000000);
-
- close(fd);
-
- if((fd = open("/dev/cma", O_RDWR)) < 0)
- {
- perror("open");
- return EXIT_FAILURE;
- }
-
- size = 1024*sysconf(_SC_PAGESIZE);
-
- if(ioctl(fd, CMA_ALLOC, &size) < 0)
- {
- perror("ioctl");
- return EXIT_FAILURE;
- }
-
- ram = mmap(NULL, 1024*sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
-
- rst = (uint8_t *)(cfg + 0);
-
- // set writer address
- *(uint32_t *)(cfg + 4) = size;
-
- // set number of samples
- *(uint32_t *)(cfg + 8) = 1024 * 1024 - 1;
+ ram = mmap(NULL, 1024*sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x1E000000);
// reset writer
- *rst &= ~4;
- *rst |= 4;
+ *((uint32_t *)(cfg + 0)) &= ~4;
+ *((uint32_t *)(cfg + 0)) |= 4;
// reset fifo and filters
- *rst &= ~1;
- *rst |= 1;
+ *((uint32_t *)(cfg + 0)) &= ~1;
+ *((uint32_t *)(cfg + 0)) |= 1;
// wait 1 second
sleep(1);
- // reset packetizer
- *rst &= ~2;
- *rst |= 2;
+ // enter reset mode for packetizer
+ *((uint32_t *)(cfg + 0)) &= ~2;
+
+ // set number of samples
+ *((uint32_t *)(cfg + 4)) = 1024 * 1024 - 1;
+
+ // enter normal mode
+ *((uint32_t *)(cfg + 0)) |= 2;
// wait 1 second
sleep(1);
@@ -72,10 +46,13 @@ int main()
// print IN1 and IN2 samples
for(i = 0; i < 1024 * 1024; ++i)
{
- value[0] = ram[2 * i + 0];
- value[1] = ram[2 * i + 1];
+ value[0] = *((int16_t *)(ram + 4*i + 0));
+ value[1] = *((int16_t *)(ram + 4*i + 2));
printf("%5d %5d\n", value[0], value[1]);
}
- return EXIT_SUCCESS;
+ munmap(cfg, sysconf(_SC_PAGESIZE));
+ munmap(ram, sysconf(_SC_PAGESIZE));
+
+ return 0;
}
diff --git a/projects/adc_recorder/block_design.tcl b/projects/adc_recorder/block_design.tcl
index 083ce73..3d81dba 100644
--- a/projects/adc_recorder/block_design.tcl
+++ b/projects/adc_recorder/block_design.tcl
@@ -1,56 +1,10 @@
-# Create clk_wiz
-cell xilinx.com:ip:clk_wiz pll_0 {
- PRIMITIVE PLL
- PRIM_IN_FREQ.VALUE_SRC USER
- PRIM_IN_FREQ 125.0
- PRIM_SOURCE Differential_clock_capable_pin
- CLKOUT1_USED true
- CLKOUT1_REQUESTED_OUT_FREQ 125.0
- USE_RESET false
-} {
- clk_in1_p adc_clk_p_i
- clk_in1_n adc_clk_n_i
-}
-
-# Create processing_system7
-cell xilinx.com:ip:processing_system7 ps_0 {
- PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
- PCW_USE_S_AXI_ACP 1
- PCW_USE_DEFAULT_ACP_USER_VAL 1
-} {
- M_AXI_GP0_ACLK pll_0/clk_out1
- S_AXI_ACP_ACLK pll_0/clk_out1
-}
-
-# Create all required interconnections
-apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
- make_external {FIXED_IO, DDR}
- Master Disable
- Slave Disable
-} [get_bd_cells ps_0]
-
-# Create xlconstant
-cell xilinx.com:ip:xlconstant const_0
+source projects/base_system/block_design.tcl
# Create proc_sys_reset
-cell xilinx.com:ip:proc_sys_reset rst_0 {} {
- ext_reset_in const_0/dout
-}
+cell xilinx.com:ip:proc_sys_reset:5.0 rst_0
-# GPIO
-
-# Delete input/output port
-delete_bd_objs [get_bd_ports exp_p_tri_io]
-
-# Create output port
-create_bd_port -dir O -from 7 -to 0 exp_p_tri_io
-
-# ADC
-
-# Create axis_red_pitaya_adc
-cell labdpr:user:axis_rp_adc adc_0 {
- ADC_DATA_WIDTH 14
-} {
+# Create axis_rp_adc
+cell labdpr:user:axis_rp_adc:1.0 adc_0 {} {
aclk pll_0/clk_out1
adc_dat_a adc_dat_a_i
adc_dat_b adc_dat_b_i
@@ -58,130 +12,126 @@ cell labdpr:user:axis_rp_adc adc_0 {
}
# Create axi_cfg_register
-cell labdpr:user:axi_cfg_register cfg_0 {
- CFG_DATA_WIDTH 96
+cell labdpr:user:axi_cfg_register:1.0 cfg_0 {
+ CFG_DATA_WIDTH 64
AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
}
-# Create port_slicer
-cell labdpr:user:port_slicer slice_0 {
- DIN_WIDTH 96 DIN_FROM 0 DIN_TO 0
-} {
- din cfg_0/cfg_data
-}
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
+ Master /ps_0/M_AXI_GP0
+ Clk Auto
+} [get_bd_intf_pins cfg_0/S_AXI]
-# Create port_slicer
-cell labdpr:user:port_slicer slice_1 {
- DIN_WIDTH 96 DIN_FROM 1 DIN_TO 1
-} {
- din cfg_0/cfg_data
-}
+set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
+set_property OFFSET 0x40000000 [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
-# Create port_slicer
-cell labdpr:user:port_slicer slice_2 {
- DIN_WIDTH 96 DIN_FROM 2 DIN_TO 2
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_1 {
+ DIN_WIDTH 64 DIN_FROM 0 DIN_TO 0 DOUT_WIDTH 1
} {
- din cfg_0/cfg_data
+ Din cfg_0/cfg_data
}
-# Create port_slicer
-cell labdpr:user:port_slicer slice_3 {
- DIN_WIDTH 96 DIN_FROM 63 DIN_TO 32
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_2 {
+ DIN_WIDTH 64 DIN_FROM 1 DIN_TO 1 DOUT_WIDTH 1
} {
- din cfg_0/cfg_data
+ Din cfg_0/cfg_data
}
-# Create port_slicer
-cell labdpr:user:port_slicer slice_4 {
- DIN_WIDTH 96 DIN_FROM 95 DIN_TO 64
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_3 {
+ DIN_WIDTH 64 DIN_FROM 2 DIN_TO 2 DOUT_WIDTH 1
} {
- din cfg_0/cfg_data
+ Din cfg_0/cfg_data
}
-# Create util_vector_logic
-cell xilinx.com:ip:util_vector_logic not_0 {
- C_SIZE 1
- C_OPERATION not
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_4 {
+ DIN_WIDTH 64 DIN_FROM 63 DIN_TO 32 DOUT_WIDTH 32
} {
- Op1 slice_1/dout
+ Din cfg_0/cfg_data
}
-# Create xlconcat
-cell xilinx.com:ip:xlconcat concat_0 {
- NUM_PORTS 2
- IN0_WIDTH 1
- IN1_WIDTH 7
-} {
- In0 not_0/Res
- dout exp_p_tri_io
+# Create xlconstant
+cell xilinx.com:ip:xlconstant:1.1 const_0
+
+# Create axis_clock_converter
+cell xilinx.com:ip:axis_clock_converter:1.1 fifo_0 {} {
+ S_AXIS adc_0/M_AXIS
+ s_axis_aclk pll_0/clk_out1
+ s_axis_aresetn const_0/dout
+ m_axis_aclk ps_0/FCLK_CLK0
+ m_axis_aresetn slice_1/Dout
}
# Create axis_broadcaster
-cell xilinx.com:ip:axis_broadcaster bcast_0 {
+cell xilinx.com:ip:axis_broadcaster:1.1 bcast_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 4
M_TDATA_NUM_BYTES 2
- M00_TDATA_REMAP {tdata[15:0]}
- M01_TDATA_REMAP {tdata[31:16]}
+ M00_TDATA_REMAP {tdata[13:0],2'b00}
+ M01_TDATA_REMAP {tdata[29:16],2'b00}
} {
- S_AXIS adc_0/M_AXIS
- aclk pll_0/clk_out1
+ S_AXIS fifo_0/M_AXIS
+ aclk ps_0/FCLK_CLK0
aresetn rst_0/peripheral_aresetn
}
# Create cic_compiler
-cell xilinx.com:ip:cic_compiler cic_0 {
+cell xilinx.com:ip:cic_compiler:4.0 cic_0 {
INPUT_DATA_WIDTH.VALUE_SRC USER
FILTER_TYPE Decimation
NUMBER_OF_STAGES 6
FIXED_OR_INITIAL_RATE 32
INPUT_SAMPLE_FREQUENCY 125
CLOCK_FREQUENCY 125
- INPUT_DATA_WIDTH 14
+ INPUT_DATA_WIDTH 16
QUANTIZATION Truncation
OUTPUT_DATA_WIDTH 16
USE_XTREME_DSP_SLICE true
HAS_ARESETN true
} {
S_AXIS_DATA bcast_0/M00_AXIS
- aclk pll_0/clk_out1
- aresetn slice_0/dout
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_1/Dout
}
# Create cic_compiler
-cell xilinx.com:ip:cic_compiler cic_1 {
+cell xilinx.com:ip:cic_compiler:4.0 cic_1 {
INPUT_DATA_WIDTH.VALUE_SRC USER
FILTER_TYPE Decimation
NUMBER_OF_STAGES 6
FIXED_OR_INITIAL_RATE 32
INPUT_SAMPLE_FREQUENCY 125
CLOCK_FREQUENCY 125
- INPUT_DATA_WIDTH 14
+ INPUT_DATA_WIDTH 16
QUANTIZATION Truncation
OUTPUT_DATA_WIDTH 16
USE_XTREME_DSP_SLICE true
HAS_ARESETN true
} {
S_AXIS_DATA bcast_0/M01_AXIS
- aclk pll_0/clk_out1
- aresetn slice_0/dout
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_1/Dout
}
# Create axis_combiner
-cell xilinx.com:ip:axis_combiner comb_0 {
+cell xilinx.com:ip:axis_combiner:1.1 comb_0 {
TDATA_NUM_BYTES.VALUE_SRC USER
TDATA_NUM_BYTES 2
} {
S00_AXIS cic_0/M_AXIS_DATA
S01_AXIS cic_1/M_AXIS_DATA
- aclk pll_0/clk_out1
+ aclk ps_0/FCLK_CLK0
aresetn rst_0/peripheral_aresetn
}
# Create fir_compiler
-cell xilinx.com:ip:fir_compiler fir_0 {
+cell xilinx.com:ip:fir_compiler:7.2 fir_0 {
DATA_WIDTH.VALUE_SRC USER
DATA_WIDTH 16
COEFFICIENTVECTOR {-1.64753028794138e-08, -4.72969860103254e-08, -7.81983994864729e-10, 3.09179315378013e-08, 1.8600476137934e-08, 3.27300695910419e-08, -6.27121813377163e-09, -1.52196115352429e-07, -8.30377969926702e-08, 3.14361841397898e-07, 3.05515872274853e-07, -4.73906648324436e-07, -7.13188274738437e-07, 5.47004771774003e-07, 1.33401100809314e-06, -4.13867548024707e-07, -2.14949555259695e-06, -6.77977800948474e-08, 3.07398932714553e-06, 1.0366230107463e-06, -3.94245232963009e-06, -2.59076839821521e-06, 4.51317323767107e-06, 4.74563996488482e-06, -4.49064349142054e-06, -7.3947777960083e-06, 3.57041197419745e-06, 1.02846684426837e-05, -1.50308472093842e-06, -1.30146997163052e-05, -1.8311731233767e-06, 1.50710364353895e-05, 6.3515248701083e-06, -1.58982472678568e-05, -1.17267343142635e-05, 1.50041199296265e-05, 1.73635115814309e-05, -1.20890304109726e-05, -2.24560062957254e-05, 7.16700059796055e-06, 2.60907689345942e-05, -6.64193032293714e-07, -2.74163749798938e-05, -6.54632074532538e-06, 2.5852558776971e-05, 1.31966582845397e-05, -2.13079073598636e-05, -1.77801135294917e-05, 1.43611952054032e-05, 1.88093817512436e-05, -6.35698021047062e-06, -1.51543007857966e-05, -6.31269475321274e-07, 6.41236246473726e-06, 4.00235076480002e-06, 6.75384652715119e-06, -1.00102812372645e-06, -2.23907547607786e-05, -1.07614170164429e-05, 3.72128949266483e-05, 3.26888314865614e-05, -4.68343172264928e-05, -6.46247522446593e-05, 4.62331324663801e-05, 0.000104353987875991, -3.05204178369922e-05, -0.000147387572103254, -4.12376672483791e-06, 0.000187096070793206, 5.94492160104715e-05, -0.000215270553995213, -0.000134242574203586, 0.000223115373945588, 0.000223732063932204, -0.000202601585158347, -0.000319473722277179, 0.000148023831554525, 0.000409856470754451, -5.75319241913947e-05, -0.00048128691789378, -6.56435551088113e-05, 0.000520005389882914, 0.000212559310978688, -0.000514378040456993, -0.000368824791639381, 0.000457257636791032, 0.00051572189965271, -0.000348325111720936, -0.000632574861580132, 0.000195575644936742, 0.000699853643923955, -1.5816811333843e-05, -0.000702875004558909, -0.000166267212059945, 0.000635554670416145, 0.000320646045613507, -0.000503596369030625, -0.000416023690327203, 0.000326453158345306, 0.00042516016658693, -0.000137454215410763, -0.000330867755122004, -1.83577770104995e-05, 0.000131884375290827, 8.88732824246191e-05, 0.000152320700965935, -2.19145324792827e-05, -0.000478845867687744, -0.000226130995959082, 0.000781165284659716, 0.000680083599509367, -0.000973297239795462, -0.00133684955123469, 0.000956951103249511, 0.00215724393391554, -0.000632647805407322, -0.00306094569410801, -8.63474252426424e-05, 0.00392560461099799, 0.00125840455441931, -0.00459097537930345, -0.00289777037472875, 0.00486843895178868, 0.00496041688761007, -0.00455566278421732, -0.0073332195556104, 0.00345548961533671, 0.00982788076765724, -0.0013975392826423, -0.0121803938743171, -0.00173944634676796, 0.0140556603140014, 0.00600554245501628, -0.0150585666700821, -0.0113645359721422, 0.0147416608531572, 0.0176785888467245, -0.0126130926725902, -0.0247012339350495, 0.00812796467212303, 0.0320712315374266, -0.000646259298618774, -0.0392988478933562, -0.0106852885932714, 0.0457163887873562, 0.0272344645510023, -0.0503010855018923, -0.0516879242105393, 0.0510032995068897, 0.0905252892059647, -0.0416077244968566, -0.163677972614864, -0.0107434888500177, 0.356350050991766, 0.554721342376512, 0.356350050991766, -0.0107434888500177, -0.163677972614864, -0.0416077244968565, 0.0905252892059646, 0.0510032995068897, -0.0516879242105392, -0.0503010855018923, 0.0272344645510023, 0.0457163887873562, -0.0106852885932714, -0.0392988478933562, -0.000646259298618766, 0.0320712315374266, 0.008127964672123, -0.0247012339350495, -0.0126130926725902, 0.0176785888467245, 0.0147416608531572, -0.0113645359721422, -0.0150585666700821, 0.00600554245501627, 0.0140556603140014, -0.00173944634676796, -0.0121803938743171, -0.0013975392826423, 0.00982788076765723, 0.00345548961533672, -0.0073332195556104, -0.00455566278421732, 0.00496041688761004, 0.00486843895178868, -0.00289777037472874, -0.00459097537930345, 0.00125840455441931, 0.003925604610998, -8.6347425242651e-05, -0.00306094569410801, -0.000632647805407327, 0.00215724393391554, 0.000956951103249513, -0.00133684955123469, -0.000973297239795458, 0.00068008359950937, 0.000781165284659718, -0.000226130995959085, -0.000478845867687734, -2.19145324792814e-05, 0.000152320700965923, 8.88732824246168e-05, 0.000131884375290828, -1.83577770104952e-05, -0.000330867755122008, -0.000137454215410769, 0.000425160166586931, 0.000326453158345309, -0.000416023690327193, -0.000503596369030629, 0.000320646045613497, 0.000635554670416148, -0.000166267212059939, -0.000702875004558908, -1.58168113338674e-05, 0.000699853643923955, 0.000195575644936758, -0.000632574861580132, -0.000348325111720941, 0.000515721899652708, 0.000457257636791035, -0.000368824791639379, -0.000514378040456997, 0.000212559310978687, 0.000520005389882915, -6.56435551088096e-05, -0.000481286917893776, -5.7531924191395e-05, 0.000409856470754451, 0.000148023831554525, -0.000319473722277176, -0.000202601585158348, 0.000223732063932204, 0.000223115373945587, -0.000134242574203588, -0.000215270553995212, 5.944921601047e-05, 0.000187096070793206, -4.12376672483805e-06, -0.000147387572103254, -3.05204178369924e-05, 0.000104353987875991, 4.62331324663777e-05, -6.46247522446589e-05, -4.68343172264921e-05, 3.26888314865612e-05, 3.72128949266458e-05, -1.07614170164428e-05, -2.23907547607785e-05, -1.0010281237264e-06, 6.7538465271515e-06, 4.00235076480007e-06, 6.41236246473652e-06, -6.31269475321259e-07, -1.5154300785797e-05, -6.35698021047036e-06, 1.88093817512439e-05, 1.43611952054029e-05, -1.77801135294911e-05, -2.13079073598635e-05, 1.31966582845395e-05, 2.58525587769708e-05, -6.54632074532428e-06, -2.74163749798938e-05, -6.64193032294061e-07, 2.60907689345942e-05, 7.16700059796085e-06, -2.24560062957254e-05, -1.20890304109726e-05, 1.7363511581431e-05, 1.50041199296266e-05, -1.17267343142635e-05, -1.58982472678571e-05, 6.3515248701082e-06, 1.50710364353894e-05, -1.83117312337678e-06, -1.30146997163053e-05, -1.50308472093845e-06, 1.02846684426836e-05, 3.57041197419745e-06, -7.39477779600816e-06, -4.49064349142055e-06, 4.74563996488478e-06, 4.51317323767109e-06, -2.59076839821518e-06, -3.94245232963005e-06, 1.03662301074629e-06, 3.07398932714552e-06, -6.77977800948646e-08, -2.14949555259695e-06, -4.13867548024735e-07, 1.33401100809314e-06, 5.47004771773993e-07, -7.13188274738437e-07, -4.73906648324394e-07, 3.05515872274853e-07, 3.14361841397861e-07, -8.30377969926656e-08, -1.5219611535243e-07, -6.27121813377245e-09, 3.27300695910341e-08, 1.86004761379317e-08, 3.0917931537805e-08, -7.81983994865244e-10, -4.72969860103212e-08, -1.64753028794135e-08}
@@ -198,44 +148,48 @@ cell xilinx.com:ip:fir_compiler fir_0 {
HAS_ARESETN true
} {
S_AXIS_DATA comb_0/M_AXIS
- aclk pll_0/clk_out1
- aresetn slice_0/dout
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_1/Dout
}
# Create axis_packetizer
-cell labdpr:user:axis_packetizer pktzr_0 {
+cell labdpr:user:axis_packetizer:1.0 pktzr_0 {
AXIS_TDATA_WIDTH 32
CNTR_WIDTH 32
CONTINUOUS FALSE
} {
S_AXIS fir_0/M_AXIS_DATA
- cfg_data slice_4/dout
- aclk pll_0/clk_out1
- aresetn slice_1/dout
+ cfg_data slice_4/Dout
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_2/Dout
}
# Create axis_dwidth_converter
-cell xilinx.com:ip:axis_dwidth_converter conv_0 {
+cell xilinx.com:ip:axis_dwidth_converter:1.1 conv_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 4
M_TDATA_NUM_BYTES 8
} {
S_AXIS pktzr_0/M_AXIS
- aclk pll_0/clk_out1
- aresetn slice_2/dout
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_3/Dout
+}
+
+# Create xlconstant
+cell xilinx.com:ip:xlconstant:1.1 const_1 {
+ CONST_WIDTH 32
+ CONST_VAL 503316480
}
# Create axis_ram_writer
-cell labdpr:user:axis_ram_writer writer_0 {
+cell labdpr:user:axis_ram_writer:1.0 writer_0 {
ADDR_WIDTH 22
- AXI_ID_WIDTH 3
} {
S_AXIS conv_0/M_AXIS
- M_AXI ps_0/S_AXI_ACP
- cfg_data slice_3/dout
- aclk pll_0/clk_out1
- aresetn slice_2/dout
+ M_AXI ps_0/S_AXI_HP0
+ cfg_data const_1/dout
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_3/Dout
}
-addr 0x40000000 4K cfg_0/S_AXI /ps_0/M_AXI_GP0
-
+assign_bd_address [get_bd_addr_segs ps_0/S_AXI_HP0/HP0_DDR_LOWOCM]
diff --git a/projects/adc_test/block_design.tcl b/projects/adc_test/block_design.tcl
index 4eddd18..2d68385 100644
--- a/projects/adc_test/block_design.tcl
+++ b/projects/adc_test/block_design.tcl
@@ -1,141 +1,132 @@
-# Create clk_wiz
-cell xilinx.com:ip:clk_wiz pll_0 {
- PRIMITIVE PLL
- PRIM_IN_FREQ.VALUE_SRC USER
- PRIM_IN_FREQ 125.0
- PRIM_SOURCE Differential_clock_capable_pin
- CLKOUT1_USED true
- CLKOUT1_REQUESTED_OUT_FREQ 125.0
- CLKOUT2_USED true
- CLKOUT2_REQUESTED_OUT_FREQ 250.0
- CLKOUT2_REQUESTED_PHASE 157.5
- CLKOUT3_USED true
- CLKOUT3_REQUESTED_OUT_FREQ 250.0
- CLKOUT3_REQUESTED_PHASE 202.5
- USE_RESET false
-} {
- clk_in1_p adc_clk_p_i
- clk_in1_n adc_clk_n_i
-}
-
-# Create processing_system7
-cell xilinx.com:ip:processing_system7 ps_0 {
- PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
- PCW_USE_S_AXI_ACP 1
- PCW_USE_DEFAULT_ACP_USER_VAL 1
-} {
- M_AXI_GP0_ACLK pll_0/clk_out1
- S_AXI_ACP_ACLK pll_0/clk_out1
-}
-
-# Create all required interconnections
-apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
- make_external {FIXED_IO, DDR}
- Master Disable
- Slave Disable
-} [get_bd_cells ps_0]
-
-# Create xlconstant
-cell xilinx.com:ip:xlconstant const_0
+source projects/base_system/block_design.tcl
# Create proc_sys_reset
-cell xilinx.com:ip:proc_sys_reset rst_0 {} {
- ext_reset_in const_0/dout
-}
-
-# ADC
+cell xilinx.com:ip:proc_sys_reset:5.0 rst_0
# Create axis_rp_adc
-cell labdpr:user:axis_rp_adc adc_0 {
- ADC_DATA_WIDTH 14
-} {
+cell labdpr:user:axis_rp_adc:1.0 adc_0 {} {
aclk pll_0/clk_out1
adc_dat_a adc_dat_a_i
adc_dat_b adc_dat_b_i
adc_csn adc_csn_o
}
-# DAC
-
-# Create axis_rp_dac
-cell labdpr:user:axis_rp_dac dac_0 {
- DAC_DATA_WIDTH 14
+# Create c_counter_binary
+cell xilinx.com:ip:c_counter_binary:12.0 cntr_0 {
+ Output_Width 32
} {
- aclk pll_0/clk_out1
- ddr_clk pll_0/clk_out2
- wrt_clk pll_0/clk_out3
- locked pll_0/locked
- dac_clk dac_clk_o
- dac_rst dac_rst_o
- dac_sel dac_sel_o
- dac_wrt dac_wrt_o
- dac_dat dac_dat_o
- s_axis_tvalid const_0/dout
+ CLK pll_0/clk_out1
}
-# CFG
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_0 {
+ DIN_WIDTH 32 DIN_FROM 26 DIN_TO 26 DOUT_WIDTH 1
+} {
+ Din cntr_0/Q
+ Dout led_o
+}
# Create axi_cfg_register
-cell labdpr:user:axi_cfg_register cfg_0 {
- CFG_DATA_WIDTH 160
+cell labdpr:user:axi_cfg_register:1.0 cfg_0 {
+ CFG_DATA_WIDTH 64
AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
}
-# Create port_slicer
-cell labdpr:user:port_slicer slice_0 {
- DIN_WIDTH 160 DIN_FROM 0 DIN_TO 0
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
+ Master /ps_0/M_AXI_GP0
+ Clk Auto
+} [get_bd_intf_pins cfg_0/S_AXI]
+
+set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
+set_property OFFSET 0x40000000 [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
+
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_1 {
+ DIN_WIDTH 64 DIN_FROM 0 DIN_TO 0 DOUT_WIDTH 1
} {
- din cfg_0/cfg_data
+ Din cfg_0/cfg_data
}
-# Create port_slicer
-cell labdpr:user:port_slicer slice_1 {
- DIN_WIDTH 160 DIN_FROM 1 DIN_TO 1
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_2 {
+ DIN_WIDTH 64 DIN_FROM 1 DIN_TO 1 DOUT_WIDTH 1
} {
- din cfg_0/cfg_data
+ Din cfg_0/cfg_data
}
-# Create port_slicer
-cell labdpr:user:port_slicer slice_2 {
- DIN_WIDTH 160 DIN_FROM 31 DIN_TO 16
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_3 {
+ DIN_WIDTH 64 DIN_FROM 2 DIN_TO 2 DOUT_WIDTH 1
} {
- din cfg_0/cfg_data
+ Din cfg_0/cfg_data
}
-# Create port_slicer
-cell labdpr:user:port_slicer slice_3 {
- DIN_WIDTH 160 DIN_FROM 63 DIN_TO 32
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_4 {
+ DIN_WIDTH 64 DIN_FROM 3 DIN_TO 3 DOUT_WIDTH 1
} {
- din cfg_0/cfg_data
+ Din cfg_0/cfg_data
}
-# RX
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_5 {
+ DIN_WIDTH 64 DIN_FROM 63 DIN_TO 32 DOUT_WIDTH 64
+} {
+ Din cfg_0/cfg_data
+}
+
+# Create xlconstant
+cell xilinx.com:ip:xlconstant:1.1 const_0
+
+# Create axis_clock_converter
+cell xilinx.com:ip:axis_clock_converter:1.1 fifo_0 {} {
+ S_AXIS adc_0/M_AXIS
+ s_axis_aclk pll_0/clk_out1
+ s_axis_aresetn const_0/dout
+ m_axis_aclk ps_0/FCLK_CLK0
+ m_axis_aresetn slice_1/Dout
+}
# Create axis_subset_converter
-cell xilinx.com:ip:axis_subset_converter subset_0 {
+cell xilinx.com:ip:axis_subset_converter:1.1 subset_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
M_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 4
M_TDATA_NUM_BYTES 2
- TDATA_REMAP {tdata[15:0]}
+ TDATA_REMAP {tdata[31:16]}
} {
- S_AXIS adc_0/M_AXIS
- aclk pll_0/clk_out1
+ S_AXIS fifo_0/M_AXIS
+ aclk ps_0/FCLK_CLK0
aresetn rst_0/peripheral_aresetn
}
+# Create xlconstant
+cell xilinx.com:ip:xlconstant:1.1 const_1
+
# Create axis_constant
-cell labdpr:user:axis_variable rate_0 {
+cell labdpr:user:axis_constant:1.0 rate_0 {
AXIS_TDATA_WIDTH 16
} {
- cfg_data slice_2/dout
- aclk pll_0/clk_out1
- aresetn rst_0/peripheral_aresetn
+ cfg_data slice_5/Dout
+ aclk ps_0/FCLK_CLK0
+}
+
+# Create axis_packetizer
+cell labdpr:user:axis_packetizer:1.0 pktzr_0 {
+ AXIS_TDATA_WIDTH 16
+ CNTR_WIDTH 1
+ CONTINUOUS FALSE
+} {
+ S_AXIS rate_0/M_AXIS
+ cfg_data const_1/dout
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_2/Dout
}
# Create cic_compiler
-cell xilinx.com:ip:cic_compiler cic_0 {
+cell xilinx.com:ip:cic_compiler:4.0 cic_0 {
INPUT_DATA_WIDTH.VALUE_SRC USER
FILTER_TYPE Decimation
NUMBER_OF_STAGES 6
@@ -148,152 +139,76 @@ cell xilinx.com:ip:cic_compiler cic_0 {
INPUT_DATA_WIDTH 16
QUANTIZATION Truncation
OUTPUT_DATA_WIDTH 16
- USE_XTREME_DSP_SLICE false
HAS_ARESETN true
} {
S_AXIS_DATA subset_0/M_AXIS
- S_AXIS_CONFIG rate_0/M_AXIS
- aclk pll_0/clk_out1
- aresetn rst_0/peripheral_aresetn
+ S_AXIS_CONFIG pktzr_0/M_AXIS
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_2/Dout
+}
+
+# Create xlconstant
+cell xilinx.com:ip:xlconstant:1.1 const_2 {
+ CONST_WIDTH 9
+ CONST_VAL 511
+}
+
+# Create axis_packetizer
+cell labdpr:user:axis_packetizer:1.0 pktzr_1 {
+ AXIS_TDATA_WIDTH 16
+ CNTR_WIDTH 9
+ CONTINUOUS TRUE
+} {
+ S_AXIS cic_0/M_AXIS_DATA
+ cfg_data const_2/dout
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_3/Dout
}
# Create axis_dwidth_converter
-cell xilinx.com:ip:axis_dwidth_converter conv_0 {
+cell xilinx.com:ip:axis_dwidth_converter:1.1 conv_0 {
S_TDATA_NUM_BYTES.VALUE_SRC USER
S_TDATA_NUM_BYTES 2
M_TDATA_NUM_BYTES 8
} {
- S_AXIS cic_0/M_AXIS_DATA
- aclk pll_0/clk_out1
- aresetn slice_0/dout
+ S_AXIS pktzr_1/M_AXIS
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_4/Dout
}
-# DMA
+# Create xlconstant
+cell xilinx.com:ip:xlconstant:1.1 const_3 {
+ CONST_WIDTH 32
+ CONST_VAL 503316480
+}
# Create axis_ram_writer
-cell labdpr:user:axis_ram_writer writer_0 {
- ADDR_WIDTH 16
- AXI_ID_WIDTH 3
+cell labdpr:user:axis_ram_writer:1.0 writer_0 {
+ ADDR_WIDTH 20
} {
S_AXIS conv_0/M_AXIS
- M_AXI ps_0/S_AXI_ACP
- cfg_data slice_3/dout
- aclk pll_0/clk_out1
- aresetn slice_1/dout
-}
-
-# GEN
-
-# Create axis_lfsr
-cell labdpr:user:axis_lfsr lfsr_0 {} {
- aclk pll_0/clk_out1
- aresetn rst_0/peripheral_aresetn
-}
-
-for {set i 0} {$i <= 1} {incr i} {
-
- # Create port_slicer
- cell labdpr:user:port_slicer slice_[expr $i + 4] {
- DIN_WIDTH 160 DIN_FROM [expr 32 * $i + 95] DIN_TO [expr 32 * $i + 64]
- } {
- din cfg_0/cfg_data
- }
-
- # Create port_slicer
- cell labdpr:user:port_slicer slice_[expr $i + 6] {
- DIN_WIDTH 160 DIN_FROM [expr 16 * $i + 143] DIN_TO [expr 16 * $i + 128]
- } {
- din cfg_0/cfg_data
- }
-
- # Create axis_constant
- cell labdpr:user:axis_constant phase_$i {
- AXIS_TDATA_WIDTH 32
- } {
- cfg_data slice_[expr $i + 4]/dout
- aclk pll_0/clk_out1
- }
-
- # Create dds_compiler
- cell xilinx.com:ip:dds_compiler dds_$i {
- DDS_CLOCK_RATE 125
- SPURIOUS_FREE_DYNAMIC_RANGE 138
- FREQUENCY_RESOLUTION 0.2
- PHASE_INCREMENT Streaming
- HAS_PHASE_OUT false
- PHASE_WIDTH 30
- OUTPUT_WIDTH 24
- DSP48_USE Minimal
- NEGATIVE_SINE true
- } {
- S_AXIS_PHASE phase_$i/M_AXIS
- aclk pll_0/clk_out1
- }
-
- # Create xbip_dsp48_macro
- cell xilinx.com:ip:xbip_dsp48_macro mult_$i {
- INSTRUCTION1 RNDSIMPLE(A*B+CARRYIN)
- A_WIDTH.VALUE_SRC USER
- B_WIDTH.VALUE_SRC USER
- OUTPUT_PROPERTIES User_Defined
- A_WIDTH 24
- B_WIDTH 16
- P_WIDTH 15
- } {
- A dds_$i/m_axis_data_tdata
- B slice_[expr $i + 6]/dout
- CARRYIN lfsr_0/m_axis_tdata
- CLK pll_0/clk_out1
- }
-
+ M_AXI ps_0/S_AXI_HP0
+ cfg_data const_3/dout
+ aclk ps_0/FCLK_CLK0
+ aresetn slice_4/Dout
}
-# Create xlconcat
-cell xilinx.com:ip:xlconcat concat_0 {
- NUM_PORTS 2
- IN0_WIDTH 16
- IN1_WIDTH 16
-} {
- In0 mult_0/P
- In1 mult_1/P
- dout dac_0/s_axis_tdata
-}
-
-# STS
-
-# Create dna_reader
-cell labdpr:user:dna_reader dna_0 {} {
- aclk pll_0/clk_out1
- aresetn rst_0/peripheral_aresetn
-}
-
-# Create xlconcat
-cell xilinx.com:ip:xlconcat concat_1 {
- NUM_PORTS 3
- IN0_WIDTH 32
- IN1_WIDTH 64
- IN2_WIDTH 32
-} {
- In0 const_0/dout
- In1 dna_0/dna_data
- In2 writer_0/sts_data
-}
+assign_bd_address [get_bd_addr_segs ps_0/S_AXI_HP0/HP0_DDR_LOWOCM]
# Create axi_sts_register
-cell labdpr:user:axi_sts_register sts_0 {
- STS_DATA_WIDTH 128
+cell labdpr:user:axi_sts_register:1.0 sts_0 {
+ STS_DATA_WIDTH 32
AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
} {
- sts_data concat_1/dout
+ sts_data writer_0/sts_data
}
-addr 0x40000000 4K sts_0/S_AXI /ps_0/M_AXI_GP0
-
-addr 0x40001000 4K cfg_0/S_AXI /ps_0/M_AXI_GP0
-
-assign_bd_address [get_bd_addr_segs ps_0/S_AXI_ACP/ACP_DDR_LOWOCM]
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
+ Master /ps_0/M_AXI_GP0
+ Clk Auto
+} [get_bd_intf_pins sts_0/S_AXI]
-group_bd_cells PS7 [get_bd_cells rst_0] [get_bd_cells pll_0] [get_bd_cells const_0] [get_bd_cells ps_0] [get_bd_cells ps_0_axi_periph]
-group_bd_cells ACQ [get_bd_cells rate_0] [get_bd_cells adc_0] [get_bd_cells subset_0] [get_bd_cells slice_0] [get_bd_cells slice_1] [get_bd_cells conv_0] [get_bd_cells slice_2] [get_bd_cells cic_0] [get_bd_cells writer_0] [get_bd_cells slice_3]
-group_bd_cells CMPLX_GEN [get_bd_cells phase_1] [get_bd_cells mult_0] [get_bd_cells dds_0] [get_bd_cells dds_1] [get_bd_cells mult_1] [get_bd_cells dac_0] [get_bd_cells slice_4] [get_bd_cells slice_5] [get_bd_cells concat_0] [get_bd_cells slice_6] [get_bd_cells phase_0] [get_bd_cells lfsr_0]
+set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg0]
+set_property OFFSET 0x40001000 [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg0]
diff --git a/projects/adc_test/client/adc-test-client_lnx.c b/projects/adc_test/client/adc-test-client_lnx.c
index 1cdb2cd..c8291f1 100644
--- a/projects/adc_test/client/adc-test-client_lnx.c
+++ b/projects/adc_test/client/adc-test-client_lnx.c
@@ -15,16 +15,12 @@ void error(const char *msg)
int main(int argc, char *argv[])
{
- int sockfd, portno, n, i;
+ int sockfd, portno, n;
struct sockaddr_in serv_addr;
struct hostent *server;
- int bytesReceived=0;
//char buffer[256];
- int32_t buffer[256*4096];
- //int32_t bufferIn[256];
- float bufferOut[256*4096];
-
+ char buffer[256*4096];
if (argc < 3) {
fprintf(stderr,"usage %s hostname port\n", argv[0]);
exit(0);
@@ -50,39 +46,12 @@ int main(int argc, char *argv[])
return 1;
}
-// while(1)
-// {
-// bytesReceived=recv(sockfd, buffer, 256*4096, MSG_WAITALL);
-// for(i = 0; i < bytesReceived; ++i)
-// {
-// bufferOut[i] = ((float)buffer[i]) / 2147483647.0;
-// }
-// //printf("%f\n",*bufferOut);
-// //printf(bufferOut);
-//
-// fwrite(bufferOut, 1, 256*4096, stdout);
-// fflush(stdout);
-// }
-
- do
- {
- bytesReceived = recv(
- sockfd,
- buffer,
- 256*4096,
- MSG_WAITALL);
-
- for (i = 0; i < bytesReceived; ++i)
- printf("%f\n", (float)buffer[i]/2147483647.0);
- }
- while(bytesReceived);
-
- //while(1)
- //{
+ while(1)
+ {
//recv(sockfd, buffer, 256*4096, MSG_WAITALL);
- // n=read(sockfd,buffer,256*4096);
- // printf("%s\n",buffer);
- //}
+ n = read(sockfd,buffer,255*4096);
+ printf("%s\n",buffer);
+ }
// if (connect(sockfd,(struct sockaddr *) &serv_addr,sizeof(serv_addr)) < 0)
// error("ERROR connecting");
diff --git a/projects/adc_test/server/adc-test-server.c b/projects/adc_test/server/adc-test-server.c
index ee727d9..02afe06 100644
--- a/projects/adc_test/server/adc-test-server.c
+++ b/projects/adc_test/server/adc-test-server.c
@@ -1,15 +1,13 @@
/*
command to compile:
-gcc -O3 -D_GNU_SOURCE adc-test-server.c -o adc-test-server
+gcc -O3 adc-test-server.c -o adc-test-server
*/
#include <stdio.h>
#include <stdint.h>
-#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <signal.h>
-#include <sched.h>
#include <fcntl.h>
#include <math.h>
#include <sys/mman.h>
@@ -21,8 +19,6 @@ gcc -O3 -D_GNU_SOURCE adc-test-server.c -o adc-test-server
#define TCP_PORT 1001
-#define CMA_ALLOC _IOWR('Z', 0, uint32_t)
-
int interrupted = 0;
void signal_handler(int sig)
@@ -32,133 +28,125 @@ void signal_handler(int sig)
int main ()
{
- int fd, sock_server, sock_client;
+ pid_t pid;
+ int pipefd[2], mmapfd, sockServer, sockClient;
int position, limit, offset;
- volatile uint32_t *rx_addr, *rx_cntr;
- volatile uint16_t *rx_rate;
- volatile uint8_t *rx_rst;
- volatile void *cfg, *sts, *ram;
- cpu_set_t mask;
- struct sched_param param;
+ void *cfg, *sts, *ram, *buf;
+ char *name;
struct sockaddr_in addr;
- uint32_t size;
- int yes = 1;
-
- memset(¶m, 0, sizeof(param));
- param.sched_priority = sched_get_priority_max(SCHED_FIFO);
- sched_setscheduler(0, SCHED_FIFO, ¶m);
-
- CPU_ZERO(&mask);
- CPU_SET(1, &mask);
- sched_setaffinity(0, sizeof(cpu_set_t), &mask);
+ int yes = 1, buffer = 0;
- if((fd = open("/dev/mem", O_RDWR)) < 0)
+ name = "/dev/mem";
+ if((mmapfd = open(name, O_RDWR)) < 0)
{
perror("open");
- return EXIT_FAILURE;
+ return 1;
}
- sts = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x40000000);
- cfg = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x40001000);
+ cfg = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x40000000);
+ sts = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x40001000);
+ ram = mmap(NULL, 2048*sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mmapfd, 0x1E000000);
+ buf = mmap(NULL, 2048*sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED|MAP_ANONYMOUS, -1, 0);
- close(fd);
-
- if((fd = open("/dev/cma", O_RDWR)) < 0)
- {
- perror("open");
- return EXIT_FAILURE;
- }
+ limit = 512*1024;
- size = 128*sysconf(_SC_PAGESIZE);
+ /* create a pipe */
+ pipe(pipefd);
- if(ioctl(fd, CMA_ALLOC, &size) < 0)
+ pid = fork();
+ if(pid == 0)
{
- perror("ioctl");
- return EXIT_FAILURE;
- }
-
- ram = mmap(NULL, 128*sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
-
- rx_rst = (uint8_t *)(cfg + 0);
- rx_rate = (uint16_t *)(cfg + 2);
- rx_addr = (uint32_t *)(cfg + 4);
+ /* child process */
- rx_cntr = (uint32_t *)(sts + 12);
+ close(pipefd[0]);
- *rx_addr = size;
+ while(1)
+ {
+ /* read ram writer position */
+ position = *((uint32_t *)(sts + 0));
- if((sock_server = socket(AF_INET, SOCK_STREAM, 0)) < 0)
- {
- perror("socket");
- return EXIT_FAILURE;
+ /* send 4 MB if ready, otherwise sleep 1 ms */
+ if((limit > 0 && position > limit) || (limit == 0 && position < 512*1024))
+ {
+ offset = limit > 0 ? 0 : 4096*1024;
+ limit = limit > 0 ? 0 : 512*1024;
+ memcpy(buf + offset, ram + offset, 4096*1024);
+ write(pipefd[1], &buffer, sizeof(buffer));
+ }
+ else
+ {
+ usleep(1000);
+ }
+ }
}
-
- setsockopt(sock_server, SOL_SOCKET, SO_REUSEADDR, (void *)&yes, sizeof(yes));
-
- /* setup listening address */
- memset(&addr, 0, sizeof(addr));
- addr.sin_family = AF_INET;
- addr.sin_addr.s_addr = htonl(INADDR_ANY);
- addr.sin_port = htons(TCP_PORT);
-
- if(bind(sock_server, (struct sockaddr *)&addr, sizeof(addr)) < 0)
+ else if(pid > 0)
{
- perror("bind");
- return EXIT_FAILURE;
- }
+ /* parent process */
- listen(sock_server, 1024);
-
- while(!interrupted)
- {
- /* enter reset mode */
- *rx_rst &= ~1;
- usleep(100);
- *rx_rst &= ~2;
- /* set default sample rate */
- *rx_rate = 4;
+ close(pipefd[1]);
- if((sock_client = accept(sock_server, NULL, NULL)) < 0)
+ if((sockServer = socket(AF_INET, SOCK_STREAM, 0)) < 0)
{
- perror("accept");
- return EXIT_FAILURE;
+ perror("socket");
+ return 1;
}
- signal(SIGINT, signal_handler);
+ setsockopt(sockServer, SOL_SOCKET, SO_REUSEADDR, (void *)&yes , sizeof(yes));
- /* enter normal operating mode */
- *rx_rst |= 3;
+ /* setup listening address */
+ memset(&addr, 0, sizeof(addr));
+ addr.sin_family = AF_INET;
+ addr.sin_addr.s_addr = htonl(INADDR_ANY);
+ addr.sin_port = htons(TCP_PORT);
- limit = 32*1024;
+ if(bind(sockServer, (struct sockaddr *)&addr, sizeof(addr)) < 0)
+ {
+ perror("bind");
+ return 1;
+ }
+
+ listen(sockServer, 1024);
while(!interrupted)
{
- /* read ram writer position */
- position = *rx_cntr;
+ /* enter reset mode */
+ *((uint32_t *)(cfg + 0)) &= ~15;
+ /* set default sample rate */
+ *((uint32_t *)(cfg + 4)) = 4;
- /* send 256 kB if ready, otherwise sleep 0.1 ms */
- if((limit > 0 && position > limit) || (limit == 0 && position < 32*1024))
+ if((sockClient = accept(sockServer, NULL, NULL)) < 0)
{
- offset = limit > 0 ? 0 : 256*1024;
- limit = limit > 0 ? 0 : 32*1024;
- if(send(sock_client, ram + offset, 256*1024, MSG_NOSIGNAL) < 0) break;
+ perror("accept");
+ return 1;
}
- else
+
+ signal(SIGINT, signal_handler);
+
+ printf("new connection\n");
+
+ /* enter normal operating mode */
+ *((uint32_t *)(cfg + 0)) |= 15;
+
+ while(!interrupted)
{
- usleep(100);
+ read(pipefd[0], &buffer, sizeof(buffer));
+ if(send(sockClient, buf, 4096*1024, 0) < 0) break;
+
+ read(pipefd[0], &buffer, sizeof(buffer));
+ if(send(sockClient, buf + 4096*1024, 4096*1024, 0) < 0) break;
}
+
+ signal(SIGINT, SIG_DFL);
+ close(sockClient);
}
- signal(SIGINT, SIG_DFL);
- close(sock_client);
- }
+ /* enter reset mode */
+ *((uint32_t *)(cfg + 0)) &= ~15;
- /* enter reset mode */
- *rx_rst &= ~1;
- usleep(100);
- *rx_rst &= ~2;
+ close(sockServer);
- close(sock_server);
+ kill(pid, SIGTERM);
- return EXIT_SUCCESS;
+ return 0;
+ }
}
diff --git a/projects/base_system/base_system/block_design.tcl b/projects/base_system/base_system/block_design.tcl
new file mode 100644
index 0000000..c03f30f
--- /dev/null
+++ b/projects/base_system/base_system/block_design.tcl
@@ -0,0 +1,29 @@
+# Create clk_wiz
+cell xilinx.com:ip:clk_wiz pll_0 {
+ PRIMITIVE PLL
+ PRIM_IN_FREQ.VALUE_SRC USER
+ PRIM_IN_FREQ 125.0
+ PRIM_SOURCE Differential_clock_capable_pin
+ CLKOUT1_USED true
+ CLKOUT1_REQUESTED_OUT_FREQ 125.0
+ USE_RESET false
+} {
+ clk_in1_p adc_clk_p_i
+ clk_in1_n adc_clk_n_i
+}
+
+# Create processing_system7
+cell xilinx.com:ip:processing_system7 ps_0 {
+ PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
+ PCW_USE_S_AXI_HP0 1
+} {
+ M_AXI_GP0_ACLK pll_0/clk_out1
+ S_AXI_HP0_ACLK pll_0/clk_out1
+}
+
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
+ make_external {FIXED_IO, DDR}
+ Master Disable
+ Slave Disable
+} [get_bd_cells ps_0]
diff --git a/projects/base_system/block_design.tcl b/projects/base_system/block_design.tcl
index 80ab85e..437efc5 100644
--- a/projects/base_system/block_design.tcl
+++ b/projects/base_system/block_design.tcl
@@ -1,30 +1,34 @@
+# Create processing_system7
+cell xilinx.com:ip:processing_system7:5.5 ps_0 {
+ PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
+ PCW_USE_S_AXI_HP0 1
+} {
+ M_AXI_GP0_ACLK ps_0/FCLK_CLK0
+ S_AXI_HP0_ACLK ps_0/FCLK_CLK0
+}
+
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
+ make_external {FIXED_IO, DDR}
+ Master Disable
+ Slave Disable
+} [get_bd_cells ps_0]
+
+# PLL
+
# Create clk_wiz
-cell xilinx.com:ip:clk_wiz pll_0 {
+cell xilinx.com:ip:clk_wiz:5.3 pll_0 {
PRIMITIVE PLL
PRIM_IN_FREQ.VALUE_SRC USER
PRIM_IN_FREQ 125.0
PRIM_SOURCE Differential_clock_capable_pin
CLKOUT1_USED true
CLKOUT1_REQUESTED_OUT_FREQ 125.0
+ CLKOUT2_USED true
+ CLKOUT2_REQUESTED_OUT_FREQ 250.0
+ CLKOUT2_REQUESTED_PHASE -90.0
USE_RESET false
} {
clk_in1_p adc_clk_p_i
clk_in1_n adc_clk_n_i
}
-
-# Create processing_system7
-cell xilinx.com:ip:processing_system7 ps_0 {
- PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
- PCW_USE_S_AXI_ACP 1
- PCW_USE_DEFAULT_ACP_USER_VAL 1
-} {
- M_AXI_GP0_ACLK pll_0/clk_out1
- S_AXI_ACP_ACLK pll_0/clk_out1
-}
-
-# Create all required interconnections
-apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
- make_external {FIXED_IO, DDR}
- Master Disable
- Slave Disable
-} [get_bd_cells ps_0]
diff --git a/projects/cfg_test/block_design.tcl b/projects/cfg_test/block_design.tcl
index 1c905dd..01afd81 100644
--- a/projects/cfg_test/block_design.tcl
+++ b/projects/cfg_test/block_design.tcl
@@ -1,48 +1,52 @@
source projects/base_system/block_design.tcl
-# Create xlconstant
-cell xilinx.com:ip:xlconstant const_0
-
# Create proc_sys_reset
-cell xilinx.com:ip:proc_sys_reset rst_0 {} {
- ext_reset_in const_0/dout
-}
+cell xilinx.com:ip:proc_sys_reset:5.0 rst_0
# Create c_counter_binary
-cell xilinx.com:ip:c_counter_binary cntr_0 {
+cell xilinx.com:ip:c_counter_binary:12.0 cntr_0 {
Output_Width 32
} {
CLK pll_0/clk_out1
}
-# Create port_slicer
-cell labdpr:user:port_slicer slice_0 {
- DIN_FROM 26 DIN_TO 26
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_0 {
+ DIN_FROM 26
+ DIN_TO 26
} {
- din cntr_0/Q
+ Din cntr_0/Q
}
# Create axi_cfg_register
-cell labdpr:user:axi_cfg_register cfg_0 {
+cell labdpr:user:axi_cfg_register:1.0 cfg_0 {
CFG_DATA_WIDTH 1024
- AXI_ADDR_WIDTH 7
+ AXI_ADDR_WIDTH 32
AXI_DATA_WIDTH 32
}
-addr 0x40000000 4K cfg_0/S_AXI /ps_0/M_AXI_GP0
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
+ Master /ps_0/M_AXI_GP0
+ Clk Auto
+} [get_bd_intf_pins cfg_0/S_AXI]
-# Create port_slicer
-cell labdpr:user:port_slicer slice_1 {
- DIN_WIDTH 1024 DIN_FROM 134 DIN_TO 128
+set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
+set_property OFFSET 0x40000000 [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
+
+# Create xlslice
+cell xilinx.com:ip:xlslice:1.0 slice_1 {
+ DIN_WIDTH 1024 DIN_FROM 134 DIN_TO 128 DOUT_WIDTH 7
} {
- din cfg_0/cfg_data
+ Din cfg_0/cfg_data
}
# Create xlconcat
-cell xilinx.com:ip:xlconcat concat_0 {
+cell xilinx.com:ip:xlconcat:2.1 concat_0 {
IN1_WIDTH 7
} {
- In0 slice_0/dout
- In1 slice_1/dout
+ In0 slice_0/Dout
+ In1 slice_1/Dout
dout led_o
}
+
diff --git a/projects/gpio_led_test/block_design.tcl b/projects/gpio_led_test/block_design.tcl
index 06376a3..2f35a6a 100644
--- a/projects/gpio_led_test/block_design.tcl
+++ b/projects/gpio_led_test/block_design.tcl
@@ -1,56 +1,50 @@
source projects/base_system/block_design.tcl
-#Enable interrupts
-set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1} CONFIG.PCW_IRQ_F2P_INTR {1}] [get_bd_cells ps_0]
-
-# Create xlconstant
-cell xilinx.com:ip:xlconstant const_0
-
# Create proc_sys_reset
-cell xilinx.com:ip:proc_sys_reset rst_0 {} {
- ext_reset_in const_0/dout
-}
+cell xilinx.com:ip:proc_sys_reset:5.0 rst_0
+
+# ADC
# Create axis_rp_adc
-cell labdpr:user:axis_rp_adc adc_0 {
- ADC_DATA_WIDTH 14
-} {
- aclk pll_0/clk_out1
+cell labdpr:user:axis_rp_adc:1.0 adc_0 {} {
+ adc_clk_p adc_clk_p_i
+ adc_clk_n adc_clk_n_i
adc_dat_a adc_dat_a_i
adc_dat_b adc_dat_b_i
adc_csn adc_csn_o
}
+# LED
+
# Create c_counter_binary
-cell xilinx.com:ip:c_counter_binary cntr_0 {
+cell xilinx.com:ip:c_counter_binary:12.0 cntr_0 {
Output_Width 32
} {
- CLK pll_0/clk_out1
+ CLK adc_0/adc_clk
}
# Create xlslice
-cell xilinx.com:ip:xlslice slice_0 {
+cell xilinx.com:ip:xlslice:1.0 slice_0 {
DIN_WIDTH 32 DIN_FROM 26 DIN_TO 26 DOUT_WIDTH 1
} {
Din cntr_0/Q
}
# Create GPIO core
-cell xilinx.com:ip:axi_gpio axi_gpio_0 {
+cell xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 {
C_GPIO_WIDTH 8
- C_GPIO2_WIDTH 1
- C_ALL_OUTPUTS 1
- C_IS_DUAL 1
- C_ALL_INPUTS 0
- C_ALL_INPUTS_2 1
- C_INTERRUPT_PRESENT 1
- C_ALL_OUTPUTS 1
+ C_ALL_OUTPUTS 1
} {
- s_axi_aclk pll_0/clk_out1
+ s_axi_aclk ps_0/FCLK_CLK0
s_axi_aresetn rst_0/peripheral_aresetn
- ip2intc_irpt ps_0/IRQ_F2P
gpio_io_o led_o
- gpio2_io_i slice_0/Dout
}
-addr 0x40000000 4K axi_gpio_0/S_AXI /ps_0/M_AXI_GP0
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
+ Master /ps_0/M_AXI_GP0
+ Clk Auto
+} [get_bd_intf_pins axi_gpio_0/S_AXI]
+
+set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_axi_gpio_0_reg]
+set_property OFFSET 0x40000000 [get_bd_addr_segs ps_0/Data/SEG_axi_gpio_0_reg]
diff --git a/projects/gpio_led_test/gpio_led_test.c b/projects/gpio_led_test/gpio_led_test.c
index bd79c4a..a225638 100644
--- a/projects/gpio_led_test/gpio_led_test.c
+++ b/projects/gpio_led_test/gpio_led_test.c
@@ -90,9 +90,9 @@ int memfd; // device memory handle for Linux device to memory mapping, it
// Linux application needs gpio base address and register offsets, Standalone application gets it from xparameters.h
#define GPIO_BUTTON_BASE_ADDRESS 0x41240000
-#define GPIO_LED_BASE_ADDRESS 0x40000000
-#define GPIO_DATA_OFFSET 0x0000
-#define GPIO_DIRECTION_OFFSET 0x0004
+#define GPIO_LED_BASE_ADDRESS 0x40000000
+#define GPIO_DATA_OFFSET 0x0000
+#define GPIO_DIRECTION_OFFSET 0x0004
// access the serial output
#define print printf
@@ -102,8 +102,8 @@ int memfd; // device memory handle for Linux device to memory mapping, it
#define LED_DELAY_PROFILE 2
#define BUTTON_CHANNEL 1
#define LED_CHANNEL 1
-#define ALL_OUTPUTS 0
-#define ALL_INPUTS 0xffffffff
+#define ALL_OUTPUTS 0
+#define ALL_INPUTS 0xffffffff
// function prototypes (functions defined in this file after the main)
@@ -126,77 +126,80 @@ void delay_loop(long int delay_count);
int buttons_get_state(void);
void LEDs_driver(int pattern);
+
+
int LED_delay_max; // maximum value to delay to for the LED wait loop
+
/*
* ***********************************************************
*/
int main() {
- // local variable
- int mode = 0; // used to check that one of the environment variables used
+ // local variable
+ int mode = 0; // used to check that one of the environment variables used
- // let the user know that we're starting
- print("---basic_design_zynq Exerciser---\n\r");
+ // let the user know that we're starting
+ print("---basic_design_zynq Exerciser---\n\r");
- //***** initialize the GPIOs *****
- // For Linux access memory mapped GPIO without kernel driver and initialize.
- // The function returns a pointer address to the associated GPIO and sets the GPIO direction
- mapped_led_dev_base = Linux_GPIO_initialize(GPIO_LED_BASE_ADDRESS, ALL_OUTPUTS, TRUE);
- mapped_button_dev_base = Linux_GPIO_initialize(GPIO_BUTTON_BASE_ADDRESS, ALL_INPUTS, FALSE);
+ //***** initialize the GPIOs *****
+ // For Linux access memory mapped GPIO without kernel driver and initialize.
+ // The function returns a pointer address to the associated GPIO and sets the GPIO direction
+ mapped_led_dev_base = Linux_GPIO_initialize(GPIO_LED_BASE_ADDRESS, ALL_OUTPUTS, TRUE);
+ mapped_button_dev_base = Linux_GPIO_initialize(GPIO_BUTTON_BASE_ADDRESS, ALL_INPUTS, FALSE);
- // determine the use of this software - are we exercising the hardware or doing the profiling exercise?
+ // determine the use of this software - are we exercising the hardware or doing the profiling exercise?
#ifdef hardware_test
- LED_delay_max = LED_DELAY_NORMAL;
- print("running the hardware test...\n\r");
- mode = 1;
+ LED_delay_max = LED_DELAY_NORMAL;
+ print("running the hardware test...\n\r");
+ mode = 1;
#endif
#ifdef profiler_test
- LED_delay_max = LED_DELAY_PROFILE;
- print("running the profiler code...\n\r");
- mode = 2;
+ LED_delay_max = LED_DELAY_PROFILE;
+ print("running the profiler code...\n\r");
+ mode = 2;
#endif
#ifdef CSP_test
- LED_delay_max = LED_DELAY_PROFILE;
- print("running the CSP analyzer code...\n\r");
- mode = 3;
+ LED_delay_max = LED_DELAY_PROFILE;
+ print("running the CSP analyzer code...\n\r");
+ mode = 3;
#endif
- LED_delay_max = LED_DELAY_NORMAL;
- print("running the Linux app...\n\r");
- mode = 4;
-
- // check to see that one or the other mode was selected, otherwise warn the user and abort
- if (mode != 0) {
- hardware_exerciser(); // read switches, detect changes, increment/decrement counter, display count on LEDs...
- } else {
- print("you must set the symbol \"hardware_test\", \"profiler_test\", \"CSP_test\", or \"LINUX_APP\" in the compiler settings!\n\r");
- }
-
- print("---Exiting main---\n\r"); // never reached...
-
- // unmap the memory used for the GPIO device before exiting
- // Linux only, but will never be reached
- // It is a good programming practice to always release the memory space the device was accessing
- // Since the Standalone drivers can always access memory, this sort of functionality is not needed
- if (munmap(mapped_base, MAP_SIZE) == -1) {
- printf("Can't unmap memory from user space.\n");
- exit(0);
- }
- printf("Memory Unmapped\n");
- close(memfd);
-
- return 0;
+ LED_delay_max = LED_DELAY_NORMAL;
+ print("running the Linux app...\n\r");
+ mode = 4;
+
+ // check to see that one or the other mode was selected, otherwise warn the user and abort
+ if (mode != 0) {
+ hardware_exerciser(); // read switches, detect changes, increment/decrement counter, display count on LEDs...
+ } else {
+ print("you must set the symbol \"hardware_test\", \"profiler_test\", \"CSP_test\", or \"LINUX_APP\" in the compiler settings!\n\r");
+ }
+
+ print("---Exiting main---\n\r"); // never reached...
+
+ // unmap the memory used for the GPIO device before exiting
+ // Linux only, but will never be reached
+ // It is a good programming practice to always release the memory space the device was accessing
+ // Since the Standalone drivers can always access memory, this sort of functionality is not needed
+ if (munmap(mapped_base, MAP_SIZE) == -1) {
+ printf("Can't unmap memory from user space.\n");
+ exit(0);
+ }
+ printf("Memory Unmapped\n");
+ close(memfd);
+
+ return 0;
}
-/*
- * ************** Hardware Exerciser Code *************************
- */
+ /*
+ * ************** Hardware Exerciser Code *************************
+ */
#define UP 0
#define LEFT 0
#define DOWN 1
@@ -214,46 +217,46 @@ int main() {
*/
void hardware_exerciser() {
- // local variables
- u32 last_button_state = 0;
- u32 current_button_state = 0;
- u32 button_difference = 0;
- int count_direction = UP;
- int sample = 0;
- int keep_running = 1;
- int profile_iteration_count = 500000; // used only in profile mode
-
- // deliberate infinite loop
- while (keep_running) {
- // read current switch configuration
- current_button_state = buttons_get_state();
- button_difference = (current_button_state ^ last_button_state) & current_button_state; // detect a change and that it has been pushed (not released)
- if (button_difference != 0) {
-
- // has anything changed based on the buttons?
- if (button_difference & 0x04) { print("Stop counting..."); count_direction = STOP; }
- else if (button_difference & 0x02) { print("Counting down..."); count_direction = DOWN; }
- else if (button_difference & 0x01) { print("Counting up..."); count_direction = UP; }
- }
- last_button_state = current_button_state; // update the button status to prevent runaway button action
-
- // compute the next sample number (period of 256)
- if (count_direction = UP) { sample++; sample %= ONE_PERIOD; }
- else if (count_direction = DOWN) { sample--; if (sample < -1) sample = ONE_PERIOD-1; }
- else { /* no change */}
-
- // do the math and drive the LEDs
- do_sine_sample(sample);
-
- // wait loop - caution - delay loops like this are removed when optimization is turned on!
- delay_loop(LED_delay_max); // delay for a slower display
-
- // if this is the profiler mode, we need to quit after a while
+ // local variables
+ u32 last_button_state = 0;
+ u32 current_button_state = 0;
+ u32 button_difference = 0;
+ int count_direction = UP;
+ int sample = 0;
+ int keep_running = 1;
+ int profile_iteration_count = 500000; // used only in profile mode
+
+ // deliberate infinite loop
+ while (keep_running) {
+ // read current switch configuration
+ current_button_state = buttons_get_state();
+ button_difference = (current_button_state ^ last_button_state) & current_button_state; // detect a change and that it has been pushed (not released)
+ if (button_difference != 0) {
+
+ // has anything changed based on the buttons?
+ if (button_difference & 0x04) { print("Stop counting..."); count_direction = STOP; }
+ else if (button_difference & 0x02) { print("Counting down..."); count_direction = DOWN; }
+ else if (button_difference & 0x01) { print("Counting up..."); count_direction = UP; }
+ }
+ last_button_state = current_button_state; // update the button status to prevent runaway button action
+
+ // compute the next sample number (period of 256)
+ if (count_direction = UP) { sample++; sample %= ONE_PERIOD; }
+ else if (count_direction = DOWN) { sample--; if (sample < -1) sample = ONE_PERIOD-1; }
+ else { /* no change */}
+
+ // do the math and drive the LEDs
+ do_sine_sample(sample);
+
+ // wait loop - caution - delay loops like this are removed when optimization is turned on!
+ delay_loop(LED_delay_max); // delay for a slower display
+
+ // if this is the profiler mode, we need to quit after a while
#ifdef profiler_test
- keep_running = profile_iteration_count--;
+ keep_running = profile_iteration_count--;
#endif
- }
+ }
}
@@ -308,14 +311,14 @@ double sine(double angle_in_radians) {
// determine quadrant and reflect horizontally (if necessary)
if (angle_in_radians > 3*PI/2) { // in Q4?
- quadrant = 4; // remember for later
- angle_in_radians = 2 * PI - angle_in_radians; // do horizontal (x) reflection, y reflection done later
+ quadrant = 4; // remember for later
+ angle_in_radians = 2 * PI - angle_in_radians; // do horizontal (x) reflection, y reflection done later
} else if (angle_in_radians > PI) { // in Q3?
- quadrant = 3; // remember for later
- angle_in_radians = angle_in_radians - PI; // no x reflection, y reflection done later
+ quadrant = 3; // remember for later
+ angle_in_radians = angle_in_radians - PI; // no x reflection, y reflection done later
} else if (angle_in_radians > PI/2) { // in Q2?
- quadrant = 2; // remember for later
- angle_in_radians = PI - angle_in_radians; // do horizontal (x) reflection
+ quadrant = 2; // remember for later
+ angle_in_radians = PI - angle_in_radians; // do horizontal (x) reflection
}
// compute powers of angle_in_radians
@@ -328,9 +331,9 @@ double sine(double angle_in_radians) {
result = angle_in_radians - X3/factorial(3) + X5/factorial(5) - X7/factorial(7);
// do vertical reflection for Q3 and Q4
- if (quadrant > 2) {
- result *= -1; // flip the Q1/Q2 result
- }
+ if (quadrant > 2) {
+ result *= -1; // flip the Q1/Q2 result
+ }
return result;
}
@@ -348,22 +351,22 @@ double factorial(int final_term) {
/******************************************************************************************************
- * LINUX GPIO INITIALIZATION
- * This function performs two operations:
- * 1) Opens a device to memory window in Linux so a GPIO that exists at a physical address is mapped
- * to a fixed logical address. This logical address is returned by the function.
- * 2) Initialize the GPIO for either input or output mode.
- *
- * INPUT PARAMETERS:
- * gpio_base_address - physical hardware base address of GPIO, you have to get this from XML file
- * direction - 32 bits indicating direction for each bit; 0 - output; 1 - input
- * first_call - boolean indicating that this is first call to function. The first time and only the first
- * time should the Linux device memory mapping service be mounted. Call for subsequent
- * gpio mapping this should be set to FALSE (0).
- *
- * RETURNS:
- * mapped_dev_base - memory pointer to the GPIO that was specified by the gpio_base_address
- *******************************************************************************************************/
+* LINUX GPIO INITIALIZATION
+* This function performs two operations:
+* 1) Opens a device to memory window in Linux so a GPIO that exists at a physical address is mapped
+* to a fixed logical address. This logical address is returned by the function.
+* 2) Initialize the GPIO for either input or output mode.
+*
+* INPUT PARAMETERS:
+* gpio_base_address - physical hardware base address of GPIO, you have to get this from XML file
+* direction - 32 bits indicating direction for each bit; 0 - output; 1 - input
+* first_call - boolean indicating that this is first call to function. The first time and only the first
+* time should the Linux device memory mapping service be mounted. Call for subsequent
+* gpio mapping this should be set to FALSE (0).
+*
+* RETURNS:
+* mapped_dev_base - memory pointer to the GPIO that was specified by the gpio_base_address
+*******************************************************************************************************/
void *Linux_GPIO_initialize(int gpio_base_address, int direction, int first_call)
{
void *mapped_dev_base;
@@ -383,21 +386,21 @@ void *Linux_GPIO_initialize(int gpio_base_address, int direction, int first_call
// Map one page of memory into user space such that the device is in that page, but it may not
// be at the start of the page.
mapped_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, memfd, dev_base & ~MAP_MASK);
- if (mapped_base == (void *) -1) {
- printf("Can't map the memory to user space for LED GPIO.\n");
- exit(0);
- }
- printf("LED GPIO memory mapped at address %p.\n", mapped_base);
-
- // Get the address of the device in user space which will be an offset from the base
- // that was mapped as memory is mapped at the start of a page
- mapped_dev_base = mapped_base + (dev_base & MAP_MASK);
-
- // Slight delay for Linux memory access problem
- usleep(50);
- // write to the direction GPIO direction register to set as all inputs or outputs
- *((volatile unsigned long *) (mapped_dev_base + GPIO_DIRECTION_OFFSET)) = direction;
- return mapped_dev_base;
+ if (mapped_base == (void *) -1) {
+ printf("Can't map the memory to user space for LED GPIO.\n");
+ exit(0);
+ }
+ printf("LED GPIO memory mapped at address %p.\n", mapped_base);
+
+ // Get the address of the device in user space which will be an offset from the base
+ // that was mapped as memory is mapped at the start of a page
+ mapped_dev_base = mapped_base + (dev_base & MAP_MASK);
+
+ // Slight delay for Linux memory access problem
+ usleep(50);
+ // write to the direction GPIO direction register to set as all inputs or outputs
+ *((volatile unsigned long *) (mapped_dev_base + GPIO_DIRECTION_OFFSET)) = direction;
+ return mapped_dev_base;
}
/*
@@ -436,29 +439,29 @@ void driveBarGraph(int value) {
void doBarGraph(int value, int style) {
if (style == BAR) {
- switch (value) {
- case 0: LEDs_driver(0x00); break;
- case 1: LEDs_driver(0x01); break;
- case 2: LEDs_driver(0x03); break;
- case 3: LEDs_driver(0x07); break;
- case 4: LEDs_driver(0x0f); break;
- case 5: LEDs_driver(0x1f); break;
- case 6: LEDs_driver(0x3f); break;
- case 7: LEDs_driver(0x7f); break;
- case 8: LEDs_driver(0xff); break;
- default: LEDs_driver(0x55); // non-contiguous pattern indicates error
- }
+ switch (value) {
+ case 0: LEDs_driver(0x00); break;
+ case 1: LEDs_driver(0x01); break;
+ case 2: LEDs_driver(0x03); break;
+ case 3: LEDs_driver(0x07); break;
+ case 4: LEDs_driver(0x0f); break;
+ case 5: LEDs_driver(0x1f); break;
+ case 6: LEDs_driver(0x3f); break;
+ case 7: LEDs_driver(0x7f); break;
+ case 8: LEDs_driver(0xff); break;
+ default: LEDs_driver(0x55); // non-contiguous pattern indicates error
+ }
} else if (style == CYLON) {
- switch (value) {
- case 0: LEDs_driver(0x01); break;
- case 1: LEDs_driver(0x02); break;
- case 2: LEDs_driver(0x04); break;
- case 3: LEDs_driver(0x08); break;
- case 4: LEDs_driver(0x10); break;
- case 5: LEDs_driver(0x20); break;
- case 6: LEDs_driver(0x40); break;
- case 7: LEDs_driver(0x80); break;
- default: LEDs_driver(0x55); // non-contiguous pattern indicates error
+ switch (value) {
+ case 0: LEDs_driver(0x01); break;
+ case 1: LEDs_driver(0x02); break;
+ case 2: LEDs_driver(0x04); break;
+ case 3: LEDs_driver(0x08); break;
+ case 4: LEDs_driver(0x10); break;
+ case 5: LEDs_driver(0x20); break;
+ case 6: LEDs_driver(0x40); break;
+ case 7: LEDs_driver(0x80); break;
+ default: LEDs_driver(0x55); // non-contiguous pattern indicates error
}
} else if (style == BINARY) {
LEDs_driver(value); // simple binary value to display
@@ -484,8 +487,8 @@ int buttons_get_state()
{
// local variables
int current_button_state = 0;
- // Linux read of gpio, notice that it accesses the data register of the GPIO as a memory location, no device driver needed!
- current_button_state = *((volatile unsigned long *) (mapped_button_dev_base + GPIO_DATA_OFFSET));
+ // Linux read of gpio, notice that it accesses the data register of the GPIO as a memory location, no device driver needed!
+ current_button_state = *((volatile unsigned long *) (mapped_button_dev_base + GPIO_DATA_OFFSET));
}
@@ -498,8 +501,8 @@ int buttons_get_state()
*/
void LEDs_driver(int led_image)
{
- // Linux write to gpio, by writing to a memory address of the gpio data register, no device driver needed!
- *((volatile unsigned long *) (mapped_led_dev_base + GPIO_DATA_OFFSET)) = led_image;
+ // Linux write to gpio, by writing to a memory address of the gpio data register, no device driver needed!
+ *((volatile unsigned long *) (mapped_led_dev_base + GPIO_DATA_OFFSET)) = led_image;
}
@@ -525,35 +528,35 @@ void delay_loop(long int count)
*/
char *itoa(int value, char *string, int radix)
{
- char tmp[33];
- char *tp = tmp;
- int i;
- unsigned v;
- int sign;
- char *sp;
-
- if (radix > 36 || radix <= 1) { string = "radix out of range 1..36"; return 0; }
-
- sign = (radix == 10 && value < 0);
- if (sign) { v = -value; }
- else { v = (unsigned)value; }
- while (v || tp == tmp) {
- i = v % radix;
- v = v / radix;
- if (i < 10) { *tp++ = i+'0'; }
- else { *tp++ = i + 'a' - 10; }
- }
-
- if (string == 0) {
- string = (char *)malloc((tp-tmp)+sign+1);
- // xil_printf("call to malloc() made\n\r");
- }
- sp = string;
-
- if (sign) { *sp++ = '-'; }
- while (tp > tmp) { *sp++ = *--tp; }
- *sp = 0;
- return string;
+ char tmp[33];
+ char *tp = tmp;
+ int i;
+ unsigned v;
+ int sign;
+ char *sp;
+
+ if (radix > 36 || radix <= 1) { string = "radix out of range 1..36"; return 0; }
+
+ sign = (radix == 10 && value < 0);
+ if (sign) { v = -value; }
+ else { v = (unsigned)value; }
+ while (v || tp == tmp) {
+ i = v % radix;
+ v = v / radix;
+ if (i < 10) { *tp++ = i+'0'; }
+ else { *tp++ = i + 'a' - 10; }
+ }
+
+ if (string == 0) {
+ string = (char *)malloc((tp-tmp)+sign+1);
+ // xil_printf("call to malloc() made\n\r");
+ }
+ sp = string;
+
+ if (sign) { *sp++ = '-'; }
+ while (tp > tmp) { *sp++ = *--tp; }
+ *sp = 0;
+ return string;
}
/*
@@ -565,10 +568,10 @@ char *itoa(int value, char *string, int radix)
*
*/
char * strcat ( char * destination, const char * source ){
- char *d = destination;
- while (*d) ++d;
- while ((*d++ = *source++) != '\0') ;
- return (destination);
+ char *d = destination;
+ while (*d) ++d;
+ while ((*d++ = *source++) != '\0') ;
+ return (destination);
}
diff --git a/projects/led_blinker/block_design.tcl b/projects/led_blinker/block_design.tcl
index f20c218..d1c0248 100644
--- a/projects/led_blinker/block_design.tcl
+++ b/projects/led_blinker/block_design.tcl
@@ -52,4 +52,11 @@ cell labdpr:user:axi_sts_register sts_0 {
sts_data concat_0/dout
}
-addr 0x40000000 4K sts_0/S_AXI /ps_0/M_AXI_GP0
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
+ Master /ps_0/M_AXI_GP0
+ Clk Auto
+} [get_bd_intf_pins sts_0/S_AXI]
+
+set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg0]
+set_property OFFSET 0x40000000 [get_bd_addr_segs ps_0/Data/SEG_sts_0_reg0]
diff --git a/projects/xadc_test/xadc_test.c b/projects/xadc_test/xadc_test.c
index 1bdbc6c..a2af2e9 100644
--- a/projects/xadc_test/xadc_test.c
+++ b/projects/xadc_test/xadc_test.c
@@ -1,119 +1,103 @@
-/*
- * devmem2.c: Simple program to read/write from/to any location in memory.
- *
- * Copyright (C) 2000, Jan-Derk Bakker (jdb@lartmaker.nl)
- *
- *
- * This software has been developed for the LART computing board
- * (http://www.lart.tudelft.nl/). The development has been sponsored by
- * the Mobile MultiMedia Communications (http://www.mmc.tudelft.nl/)
- * and Ubiquitous Communications (http://www.ubicom.tudelft.nl/)
- * projects.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- * */
+//#include <stdio.h>
+//#include <stdlib.h>
+//#include <unistd.h>
+//#include <string.h>
+//#include <errno.h>
+//#include <signal.h>
+//#include <fcntl.h>
+//#include <ctype.h>
+//#include <termios.h>
+//#include <sys/types.h>
+//#include <sys/mman.h>
+//
+//void FATAL (void){
+// printf("No se ejecutó correctamente. Revisar\n");
+//}
+//
+//#define MAP_SIZE 4096UL
+//#define MAP_MASK (MAP_SIZE-1)
+//#define BASE_ADDR 0x1000000
+//#define TX_BUFFER (BASE_ADDR + 0x001000)
+//#define RX_BUFFER (BASE_ADDR + 0x003000)
+//#define AXI_DMA_BASE_ADDR 0x40001000
+//#define TEMPERATURE (AXI_DMA_BASE_ADDR + 0x00)
+//#define VCCINT (AXI_DMA_BASE_ADDR + 0x01)
+//#define VCCAUX (AXI_DMA_BASE_ADDR + 0x02)
+//#define VP_VN (AXI_DMA_BASE_ADDR + 0x03)
+//#define S2MM_DMACR (AXI_DMA_BASE_ADDR + 0x30) //CR = Control Register
+//#define S2MM_DMASR (AXI_DMA_BASE_ADDR + 0x34) //SR = Status Register
+//#define S2MM_DA (AXI_DMA_BASE_ADDR + 0x48) //DA = Destination Adress
+//#define S2MM_LENGHT (AXI_DMA_BASE_ADDR + 0x58) //Longitud
+
+//int main(int argc, char * argv []){
+// int fd;
+// void *map_base, *virt_addr, *map_base_thread,
+// *virt_addr_thread;
+// //unsigned long read_result, writeval;
+// //off_t target;
+// // int access_type
+// fd = open("/dev/uio1", O_RDWR | O_SYNC); //Abrimos toda la memoria
+//fisica del Xilinx
+// printf("%d",fd);
+// if((fd = open("/dev/uio1",O_RDWR | O_SYNC)) == -1 ){
+// FATAL();
+// }
+// printf ("/dev/uio1 opened successfully.\n");
+// fflush (stdout);
+// //Inicializamos el DMA
+// initialize_axi_dma();
#include <stdio.h>
#include <stdlib.h>
+#include <stdint.h>
#include <unistd.h>
-#include <string.h>
-#include <errno.h>
-#include <signal.h>
-#include <fcntl.h>
-#include <ctype.h>
-#include <termios.h>
-#include <sys/types.h>
#include <sys/mman.h>
+#include <fcntl.h>
-#define FATAL do { fprintf(stderr, "Error at line %d, file %s (%d) [%s]\n", \
- __LINE__, __FILE__, errno, strerror(errno)); exit(1); } while(0)
-
-#define MAP_SIZE 4096UL
-#define MAP_MASK (MAP_SIZE - 1)
-
-int main(int argc, char **argv) {
- int fd;
- void *map_base, *virt_addr;
- unsigned long read_result, writeval;
- off_t target;
- int access_type = 'w';
+#define VERSION "0.1"
+int main(int argc, char *argv[])
+{
+ FILE *fd=NULL;
+ int mfd, i;
+ uint32_t wo;
+ int16_t ch[2];
+ void *cfg, *ram;
+ char *name = "/dev/mem";
+ int32_t mtd_dp = 0, mtd_cdp = 0, mtd_pulse_cnt = 0, mtd_pulse_pnt = 0;
- if(argc < 2) {
- fprintf(stderr, "\nUsage:\t%s { address } [ type [ data ] ]\n"
- "\taddress : memory address to act upon\n"
- "\ttype : access operation type : [b]yte, [h]alfword, [w]ord\n"
- "\tdata : data to be written\n\n",
- argv[0]);
- exit(1);
- }
- target = strtoul(argv[1], 0, 0);
+// printf("%d\n",argc);
- if(argc > 2)
- access_type = tolower(argv[2][0]);
+// if (argc<2) {
+// printf("%s version %s\n",argv[0],VERSION);
+// printf("Syntax: %s [filename] [trig lvl](in ADC value) [n points]\n ex: %s data.dat 300\n",argv[0],argv[0]);
+// exit(EXIT_FAILURE);
+// }
+//
+// if ((fd = fopen(argv[1], "ab")) == NULL){
+// printf("Error al abrir el archivo de destino!\n");
+// exit(EXIT_FAILURE);//1
+// }
+ if((mfd = open(name, O_RDWR)) < 0)
+ {
+ perror("open");
+ return 1;
+ }
- if((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) FATAL;
- printf("/dev/mem opened.\n");
- fflush(stdout);
+ cfg = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mfd,0x40001000);
+ ram = mmap(NULL, 1024*sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, mfd, 0x1E000000);
- /* Map one page */
- map_base = mmap(0, MAP_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd, target & ~MAP_MASK);
- if(map_base == (void *) -1) FATAL;
- printf("Memory mapped at address %p.\n", map_base);
- fflush(stdout);
+ // print IN1 and IN2 samples
+ for(i = 0; i < 64; ++i)
+ {
+ ch[0] = *((int16_t *)(cfg + i));
+ //ch[1] = *((int16_t *)(ram + 4*i + 2));
+ printf("%5d \n", (ch[0]>>4));
+ }
- virt_addr = map_base + (target & MAP_MASK);
- switch(access_type) {
- case 'b':
- read_result = *((unsigned char *) virt_addr);
- break;
- case 'h':
- read_result = *((unsigned short *) virt_addr);
- break;
- case 'w':
- read_result = *((unsigned long *) virt_addr);
- break;
- default:
- fprintf(stderr, "Illegal data type '%c'.\n", access_type);
- exit(2);
- }
- printf("Value at address 0x%X (%p): 0x%X\n", target, virt_addr, read_result);
- fflush(stdout);
- if(argc > 3) {
- writeval = strtoul(argv[3], 0, 0);
- switch(access_type) {
- case 'b':
- *((unsigned char *) virt_addr) = writeval;
- read_result = *((unsigned char *) virt_addr);
- break;
- case 'h':
- *((unsigned short *) virt_addr) = writeval;
- read_result = *((unsigned short *) virt_addr);
- break;
- case 'w':
- *((unsigned long *) virt_addr) = writeval;
- read_result = *((unsigned long *) virt_addr);
- break;
- }
- printf("Written 0x%X; readback 0x%X\n", writeval, read_result);
- fflush(stdout);
- }
+ munmap(cfg, sysconf(_SC_PAGESIZE));
+ munmap(ram, sysconf(_SC_PAGESIZE));
- if(munmap(map_base, MAP_SIZE) == -1) FATAL;
- close(fd);
- return 0;
+ return 0;
}
diff --git a/scripts/core.tcl b/scripts/core.tcl
index b8d56ff..9a39c75 100644
--- a/scripts/core.tcl
+++ b/scripts/core.tcl
@@ -7,7 +7,7 @@ set elements [split $core_name _]
set project_name [join [lrange $elements 0 end-2] _]
set version [string trimleft [join [lrange $elements end-1 end] .] v]
-file delete -force tmp/cores/$core_name tmp/cores/$project_name.cache tmp/cores/$project_name.hw tmp/cores/$project_name.xpr tmp/cores/$project_name.ip_user_files
+file delete -force tmp/cores/$core_name tmp/cores/$project_name.cache tmp/cores/$project_name.hw tmp/cores/$project_name.xpr
create_project -part $part_name $project_name tmp/cores
diff --git a/scripts/debian.sh b/scripts/debian.sh
old mode 100755
new mode 100644
index 31a882c..d4b9e71
--- a/scripts/debian.sh
+++ b/scripts/debian.sh
@@ -3,17 +3,16 @@ device=$1
boot_dir=`mktemp -d /tmp/BOOT.XXXXXXXXXX`
root_dir=`mktemp -d /tmp/ROOT.XXXXXXXXXX`
-linux_dir=tmp/linux-5.10
-linux_ver=5.10.46-xilinx
-
# Choose mirror automatically, depending the geographic and network location
-mirror=http://deb.debian.org/debian
+mirror=http://httpredir.debian.org/debian
-distro=buster
+distro=jessie
arch=armhf
+hostapd_url=https://www.dropbox.com/sh/5fy49wae6xwxa8a/AAAQHa5NkpLYFocaOrrnft-Pa/rtl8192cu/hostapd-armhf?dl=1
+
passwd=escondido
-timezone=Europe/Brussels
+timezone=America/Argentina/Mendoza
# Create partitions
@@ -21,8 +20,8 @@ parted -s $device mklabel msdos
parted -s $device mkpart primary fat16 4MiB 16MiB
parted -s $device mkpart primary ext4 16MiB 100%
-boot_dev=/dev/`lsblk -ln -o NAME -x NAME $device | sed '2!d'`
-root_dev=/dev/`lsblk -ln -o NAME -x NAME $device | sed '3!d'`
+boot_dev=/dev/`lsblk -lno NAME $device | sed '2!d'`
+root_dev=/dev/`lsblk -lno NAME $device | sed '3!d'`
# Create file systems
@@ -36,35 +35,37 @@ mount $root_dev $root_dir
# Copy files to the boot file system
-cp boot.bin devicetree.dtb uImage $boot_dir
-cp uEnv-ext4.txt $boot_dir/uEnv.txt
+cp boot.bin devicetree.dtb uImage uEnv.txt $boot_dir
# Install Debian base system to the root file system
debootstrap --foreign --arch $arch $distro $root_dir $mirror
-# Install Linux modules
-
-modules_dir=$root_dir/lib/modules/$linux_ver
-
-mkdir -p $modules_dir/kernel
-
-find $linux_dir -name \*.ko -printf '%P\0' | tar --directory=$linux_dir --owner=0 --group=0 --null --files-from=- -zcf - | tar -zxf - --directory=$modules_dir/kernel
-
-cp $linux_dir/modules.order $linux_dir/modules.builtin $modules_dir/
-
-depmod -a -b $root_dir $linux_ver
-
# Add missing configuration files and packages
cp /etc/resolv.conf $root_dir/etc/
cp /usr/bin/qemu-arm-static $root_dir/usr/bin/
+cp patches/fw_env.config $root_dir/etc/
+
+mkdir -p $root_dir/usr/local/bin
+cp fw_printenv $root_dir/usr/local/bin/fw_printenv
+cp fw_printenv $root_dir/usr/local/bin/fw_setenv
+
+mkdir -p $root_dir/usr/local/sbin
+curl -L $hostapd_url -o $root_dir/usr/local/sbin/hostapd
+chmod +x $root_dir/usr/local/sbin/hostapd
+
chroot $root_dir <<- EOF_CHROOT
export LANG=C
export LC_ALL=C
-export PATH=/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
+# Add missing paths
+
+echo :$PATH: | grep -q :/sbin: || export PATH=$PATH:/sbin
+echo :$PATH: | grep -q :/bin: || export PATH=$PATH:/bin
+echo :$PATH: | grep -q :/usr/sbin: || export PATH=$PATH:/usr/sbin
+echo :$PATH: | grep -q :/usr/bin: || export PATH=$PATH:/usr/bin
/debootstrap/debootstrap --second-stage
@@ -89,6 +90,12 @@ cat <<- EOF_CAT > etc/fstab
/dev/mmcblk0p1 /boot vfat defaults 0 2
EOF_CAT
+cat <<- EOF_CAT >> etc/securetty
+
+# Serial Console for Xilinx Zynq-7000
+ttyPS0
+EOF_CAT
+
echo red-pitaya > etc/hostname
apt-get update
@@ -100,23 +107,17 @@ sed -i "/^# en_US.UTF-8 UTF-8$/s/^# //" etc/locale.gen
locale-gen
update-locale LANG=en_US.UTF-8
-ln -sf /usr/share/zoneinfo/$timezone etc/localtime
+echo $timezone > etc/timezone
dpkg-reconfigure --frontend=noninteractive tzdata
apt-get -y install openssh-server ca-certificates ntp ntpdate fake-hwclock \
usbutils psmisc lsof parted curl vim wpasupplicant hostapd isc-dhcp-server \
iw firmware-realtek firmware-ralink firmware-atheros firmware-brcm80211 \
- ifplugd ntfs-3g net-tools less
-
-sed -i 's/^#PermitRootLogin.*/PermitRootLogin yes/' etc/ssh/sshd_config
+ ifplugd ntfs-3g
-cat <<- EOF_CAT >> etc/securetty
-
-# Serial Console for Xilinx Zynq-7000
-ttyPS0
-EOF_CAT
+sed -i 's/^PermitRootLogin.*/PermitRootLogin yes/' etc/ssh/sshd_config
-touch etc/udev/rules.d/80-net-setup-link.rules
+touch etc/udev/rules.d/75-persistent-net-generator.rules
cat <<- EOF_CAT > etc/network/interfaces.d/eth0
iface eth0 inet dhcp
@@ -160,10 +161,23 @@ EOF_CAT
cat <<- EOF_CAT > etc/default/hostapd
DAEMON_CONF=/etc/hostapd/hostapd.conf
-EOF_CAT
-cat <<- EOF_CAT > etc/default/isc-dhcp-server
-INTERFACESv4=wlan0
+if [ "\\\$1" = "start" ]
+then
+ iw wlan0 info > /dev/null 2>&1
+ if [ \\\$? -eq 0 ]
+ then
+ sed -i '/^driver/s/=.*/=nl80211/' /etc/hostapd/hostapd.conf
+ DAEMON_SBIN=/usr/sbin/hostapd
+ else
+ sed -i '/^driver/s/=.*/=rtl871xdrv/' /etc/hostapd/hostapd.conf
+ DAEMON_SBIN=/usr/local/sbin/hostapd
+ fi
+ echo \\\$DAEMON_SBIN > /run/hostapd.which
+elif [ "\\\$1" = "stop" ]
+then
+ DAEMON_SBIN=\\\$(cat /run/hostapd.which)
+fi
EOF_CAT
cat <<- EOF_CAT > etc/dhcp/dhcpd.conf
diff --git a/scripts/devicetree.tcl b/scripts/devicetree.tcl
index f5bc140..548a514 100644
--- a/scripts/devicetree.tcl
+++ b/scripts/devicetree.tcl
@@ -5,23 +5,23 @@ set proc_name [lindex $argv 1]
set repo_path [lindex $argv 2]
-set boot_args {console=ttyPS0,115200 earlyprintk}
+set boot_args {console=ttyPS0,115200 root=/dev/mmcblk0p2 ro rootfstype=ext4 earlyprintk rootwait}
set hard_path tmp/$project_name.hard
set tree_path tmp/$project_name.tree
file mkdir $hard_path
-file copy -force tmp/$project_name.xsa $hard_path/$project_name.xsa
+file copy -force tmp/$project_name.hwdef $hard_path/$project_name.hdf
-hsi set_repo_path $repo_path
+set_repo_path $repo_path
-hsi open_hw_design $hard_path/$project_name.xsa
-hsi create_sw_design -proc $proc_name -os device_tree devicetree
+open_hw_design $hard_path/$project_name.hdf
+create_sw_design -proc $proc_name -os device_tree devicetree
-hsi set_property CONFIG.kernel_version {2020.2} [hsi get_os]
-hsi set_property CONFIG.bootargs $boot_args [hsi get_os]
+set_property CONFIG.kernel_version {2016.4} [get_os]
+set_property CONFIG.bootargs $boot_args [get_os]
-hsi generate_target -dir $tree_path
+generate_bsp -dir $tree_path
-hsi close_sw_design [hsi current_sw_design]
-hsi close_hw_design [hsi current_hw_design]
+close_sw_design [current_sw_design]
+close_hw_design [current_hw_design]
diff --git a/scripts/fsbl.tcl b/scripts/fsbl.tcl
index 64095ab..10a006c 100644
--- a/scripts/fsbl.tcl
+++ b/scripts/fsbl.tcl
@@ -7,14 +7,14 @@ set hard_path tmp/$project_name.hard
set fsbl_path tmp/$project_name.fsbl
file mkdir $hard_path
-file copy -force tmp/$project_name.xsa $hard_path/$project_name.xsa
+file copy -force tmp/$project_name.hwdef $hard_path/$project_name.hdf
-hsi open_hw_design $hard_path/$project_name.xsa
-hsi create_sw_design -proc $proc_name -os standalone fsbl
+open_hw_design $hard_path/$project_name.hdf
+create_sw_design -proc $proc_name -os standalone fsbl
-hsi add_library xilffs
-hsi add_library xilrsa
+add_library xilffs
+add_library xilrsa
-hsi generate_app -proc $proc_name -app zynq_fsbl -dir $fsbl_path -compile
+generate_app -proc $proc_name -app zynq_fsbl -dir $fsbl_path -compile
-hsi close_hw_design [hsi current_hw_design]
+close_hw_design [current_hw_design]
diff --git a/scripts/hwdef.tcl b/scripts/hwdef.tcl
index 8adeaba..bfedd5c 100644
--- a/scripts/hwdef.tcl
+++ b/scripts/hwdef.tcl
@@ -3,6 +3,11 @@ set project_name [lindex $argv 0]
open_project tmp/$project_name.xpr
-write_hw_platform -fixed -force -file tmp/$project_name.xsa
+if {[get_property PROGRESS [get_runs synth_1]] != "100%"} {
+ launch_runs synth_1
+ wait_on_run synth_1
+}
+
+write_hwdef -force -file tmp/$project_name.hwdef
close_project
diff --git a/scripts/image.sh b/scripts/image.sh
old mode 100755
new mode 100644
index 6a8cffc..ee9b766
--- a/scripts/image.sh
+++ b/scripts/image.sh
@@ -8,7 +8,7 @@ then
size=$3
fi
-dd if=/dev/zero of=$image bs=1M count=$size status=progress
+dd if=/dev/zero of=$image bs=1M count=$size
device=`losetup -f`
diff --git a/scripts/project.tcl b/scripts/project.tcl
index 5d1a181..5a46bb7 100644
--- a/scripts/project.tcl
+++ b/scripts/project.tcl
@@ -3,14 +3,12 @@ set project_name [lindex $argv 0]
set part_name [lindex $argv 1]
-file delete -force tmp/$project_name.cache tmp/$project_name.hw tmp/$project_name.srcs tmp/$project_name.runs tmp/$project_name.sim tmp/$project_name.ip_user_files tmp/$project_name.xpr
+file delete -force tmp/$project_name.cache tmp/$project_name.hw tmp/$project_name.srcs tmp/$project_name.runs tmp/$project_name.xpr
create_project -part $part_name $project_name tmp
set_property IP_REPO_PATHS tmp/cores [current_project]
-update_ip_catalog
-
set_property target_language VHDL [current_project]
set bd_path tmp/$project_name.srcs/sources_1/bd/system
@@ -67,19 +65,10 @@ proc module {module_name module_body {module_ports {}}} {
}
}
-proc addr {offset range port master} {
- set object [get_bd_intf_pins $port]
- set segment [get_bd_addr_segs -of_objects $object]
- set config [list Master $master Clk Auto]
- apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config $config $object
- assign_bd_address -offset $offset -range $range $segment
-}
-
source projects/$project_name/block_design.tcl
rename cell {}
rename module {}
-rename addr {}
if {[version -short] >= 2016.3} {
set_property synth_checkpoint_mode None [get_files $bd_path/system.bd]
@@ -95,7 +84,7 @@ if {[llength $files] > 0} {
add_files -norecurse $files
}
-set files [glob -nocomplain cfg/*.xdc projects/$project_name/*.xdc]
+set files [glob -nocomplain cfg/*.xdc]
if {[llength $files] > 0} {
add_files -norecurse -fileset constrs_1 $files
}
diff --git a/scripts/ubuntu.sh b/scripts/ubuntu.sh
index e877eb9..af01c3a 100755
--- a/scripts/ubuntu.sh
+++ b/scripts/ubuntu.sh
@@ -3,11 +3,10 @@ device=$1
boot_dir=`mktemp -d /tmp/BOOT.XXXXXXXXXX`
root_dir=`mktemp -d /tmp/ROOT.XXXXXXXXXX`
-linux_dir=tmp/linux-5.10
-linux_ver=5.10.46-xilinx
+root_tar=ubuntu-base-14.04.5-core-armhf.tar.gz
+root_url=http://cdimage.ubuntu.com/ubuntu-base/releases/14.04/release/$root_tar
-root_tar=ubuntu-base-20.04.2-base-armhf.tar.gz
-root_url=http://cdimage.ubuntu.com/ubuntu-base/releases/20.04/release/$root_tar
+hostapd_url=https://www.dropbox.com/sh/5fy49wae6xwxa8a/AAAQHa5NkpLYFocaOrrnft-Pa/rtl8192cu/hostapd-armhf?dl=1
passwd=escondido
timezone=America/Argentina/Mendoza
@@ -18,8 +17,8 @@ parted -s $device mklabel msdos
parted -s $device mkpart primary fat16 4MiB 16MiB
parted -s $device mkpart primary ext4 16MiB 100%
-boot_dev=/dev/`lsblk -ln -o NAME -x NAME $device | sed '2!d'`
-root_dev=/dev/`lsblk -ln -o NAME -x NAME $device | sed '3!d'`
+boot_dev=/dev/`lsblk -lno NAME $device | sed '2!d'`
+root_dev=/dev/`lsblk -lno NAME $device | sed '3!d'`
# Create file systems
@@ -33,8 +32,7 @@ mount $root_dev $root_dir
# Copy files to the boot file system
-cp boot.bin devicetree.dtb uImage $boot_dir
-cp uEnv-ext4.txt $boot_dir/uEnv.txt
+cp boot.bin devicetree.dtb uImage uEnv.txt $boot_dir
# Copy Ubuntu Core to the root file system
@@ -42,28 +40,29 @@ test -f $root_tar || curl -L $root_url -o $root_tar
tar -zxf $root_tar --directory=$root_dir
-# Install Linux modules
-
-modules_dir=$root_dir/lib/modules/$linux_ver
-
-mkdir -p $modules_dir/kernel
-
-find $linux_dir -name \*.ko -printf '%P\0' | tar --directory=$linux_dir --owner=0 --group=0 --null --files-from=- -zcf - | tar -zxf - --directory=$modules_dir/kernel
-
-cp $linux_dir/modules.order $linux_dir/modules.builtin $modules_dir/
-
-depmod -a -b $root_dir $linux_ver
-
# Add missing configuration files and packages
cp /etc/resolv.conf $root_dir/etc/
cp /usr/bin/qemu-arm-static $root_dir/usr/bin/
+cp patches/fw_env.config $root_dir/etc/
+
+cp fw_printenv $root_dir/usr/local/bin/fw_printenv
+cp fw_printenv $root_dir/usr/local/bin/fw_setenv
+
+curl -L $hostapd_url -o $root_dir/usr/local/sbin/hostapd
+chmod +x $root_dir/usr/local/sbin/hostapd
+
chroot $root_dir <<- EOF_CHROOT
export LANG=C
export LC_ALL=C
-export PATH=/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
+# Add missing paths
+
+echo :$PATH: | grep -q :/sbin: || export PATH=$PATH:/sbin
+echo :$PATH: | grep -q :/bin: || export PATH=$PATH:/bin
+echo :$PATH: | grep -q :/usr/sbin: || export PATH=$PATH:/usr/sbin
+echo :$PATH: | grep -q :/usr/bin: || export PATH=$PATH:/usr/bin
cat <<- EOF_CAT > etc/apt/apt.conf.d/99norecommends
APT::Install-Recommends "0";
@@ -147,6 +146,23 @@ EOF_CAT
cat <<- EOF_CAT > etc/default/hostapd
DAEMON_CONF=/etc/hostapd/hostapd.conf
+
+if [ "\\\$1" = "start" ]
+then
+ iw wlan0 info > /dev/null 2>&1
+ if [ \\\$? -eq 0 ]
+ then
+ sed -i '/^driver/s/=.*/=nl80211/' /etc/hostapd/hostapd.conf
+ DAEMON_SBIN=/usr/sbin/hostapd
+ else
+ sed -i '/^driver/s/=.*/=rtl871xdrv/' /etc/hostapd/hostapd.conf
+ DAEMON_SBIN=/usr/local/sbin/hostapd
+ fi
+ echo \\\$DAEMON_SBIN > /run/hostapd.which
+elif [ "\\\$1" = "stop" ]
+then
+ DAEMON_SBIN=\\\$(cat /run/hostapd.which)
+fi
EOF_CAT
cat <<- EOF_CAT > etc/dhcp/dhcpd.conf
diff --git a/settings.sh b/settings.sh
index 0a43e7b..83084ad 100644
--- a/settings.sh
+++ b/settings.sh
@@ -16,9 +16,7 @@ export LC_ALL="en_US.UTF-8"
# setup Xilinx Vivado FPGA tools
################################################################################
-. /tools/Xilinx/SDK/2018.3/settings64.sh
-#. /tools/Xilinx/Vivado/2018.3/settings64.sh
-#. /tools/Xilinx/Vivado/2019.2/settings64.sh
+. /tools/Xilinx/Vivado/2019.2/settings64.sh
################################################################################
# setup cross compiler toolchain
diff --git a/uEnv.txt b/uEnv.txt
old mode 100644
new mode 100755
index 0680df0..5e65556
--- a/uEnv.txt
+++ b/uEnv.txt
@@ -1,15 +1,11 @@
+
kernel_image=uImage
devicetree_image=devicetree.dtb
-ramdisk_image=uInitrd
-
kernel_load_address=0x2080000
devicetree_load_address=0x2000000
-ramdisk_load_address=0x3000000
-
-bootcmd=fatload mmc 0 ${kernel_load_address} ${kernel_image} && fatload mmc 0 ${devicetree_load_address} ${devicetree_image} && load mmc 0 ${ramdisk_load_address} ${ramdisk_image} && bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}
+bootcmd=mmcinfo && fatload mmc 0 ${kernel_load_address} ${kernel_image} && fatload mmc 0 ${devicetree_load_address} ${devicetree_image} && bootm ${kernel_load_address} - ${devicetree_load_address}
-bootargs=console=ttyPS0,115200 earlyprintk modloop=modloop cma=36M
--
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