diff --git a/Makefile b/Makefile
index 0695bc9b15bea84dbec1d362be5766c84b9cc2c0..38cc038f24960f8bc73620fb479fcaf63a636a74 100644
--- a/Makefile
+++ b/Makefile
@@ -35,6 +35,7 @@ CORES = axi_axis_reader_v1_0 \
 				axis_lago_trigger_v1_1 \
 				axis_lago_trigger_v1_2 \
 				axis_lago_trigger_v1_3 \
+				axis_lpf_v1_0 \
 				axis_packetizer_v1_0 \
 				axis_ram_writer_v1_0 \
 				axis_rp_adc_v1_0 \
diff --git a/cores/axis_avgr32bits_v1_0/old_stuffs/avg_ntoone.vhd b/cores/axis_avgr32bits_v1_0/old_stuffs/avg_ntoone.vhd
deleted file mode 100644
index 82d577202089d4187c9e5b1dda58bcc769ec0f7b..0000000000000000000000000000000000000000
--- a/cores/axis_avgr32bits_v1_0/old_stuffs/avg_ntoone.vhd
+++ /dev/null
@@ -1,256 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity avg_ntoone is
-  generic (
-            I_DWIDTH   : natural := 128; -- ADC data width x8
-            O_DWIDTH   : natural := 32;  -- AXI data width
-            ADC_DWIDTH : natural := 16;  -- ADC data width
-            MEM_AWIDTH : natural := 10;  --
-            MEM_DEPTH  : natural := 1024 -- Max 2**16
-          );
-  port (
-         -- Averager specific ports
-         start_i        : in std_logic;
-         send_i         : in std_logic;
-         trig_i         : in std_logic;
-         done_o         : out std_logic;
-         --state_mon      : out std_logic_vector(3 downto 0);
-         --nsamples Must be power of 2. Minimum is 8 and maximum is 2^AW
-         en_i           : in std_logic;
-         naverages_i    : in std_logic_vector(ADC_DWIDTH-1 downto 0);
-         nsamples_i     : in std_logic_vector(ADC_DWIDTH-1 downto 0);
-
-         --avg_o          : out std_logic_vector(O_DWIDTH-1 downto 0);
-
-         s_axis_cfg_aclk    : in std_logic;
-         s_axis_cfg_aresetn : in std_logic;
-
-         -- Slave side
-         s_axis_aclk    : in std_logic;
-         s_axis_aresetn : in std_logic;
-         s_axis_tready  : out std_logic;
-         s_axis_tvalid  : in std_logic;
-         s_axis_tdata   : in std_logic_vector(I_DWIDTH-1 downto 0);
-
-         -- Master side
-         m_axis_aclk    : in std_logic;
-         m_axis_aresetn : in std_logic;
-         m_axis_tready  : in std_logic;
-         m_axis_tdata   : out std_logic_vector(O_DWIDTH-1 downto 0);
-         m_axis_tvalid  : out std_logic;
-         m_axis_tlast   : out std_logic;
-         m_axis_tkeep   : out std_logic_vector(4-1 downto 0)
-       );
-end avg_ntoone;
-
-architecture rtl of avg_ntoone is
-
-  function log2c(n: integer) return integer is
-    variable m, p: integer;
-  begin
-    m := 0;
-    p := 1;
-    while p < n loop
-      m := m + 1;
-      p := p * 2;
-    end loop;
-    return m;
-  end log2c;
-
-  constant RATIO : natural := I_DWIDTH/ADC_DWIDTH;
-
-  type state_t is (
-  ST_IDLE,
-  ST_WAIT_TRIG,
-  ST_AVG_N1,
-  ST_WRITE_AVG,
-  ST_FINISH
-);
-signal state_reg, state_next      : state_t;
-
-signal tdp_wea     : std_logic;
-signal tdp_addra_reg, tdp_addra_next : unsigned(MEM_AWIDTH-1 downto 0);
-signal tdp_dia     : std_logic_vector(O_DWIDTH-1 downto 0);
-signal tdp_doa     : std_logic_vector(O_DWIDTH-1 downto 0);
-signal data_reg, data_next       : std_logic_vector(2*I_DWIDTH-1 downto 0);
-signal samples_reg, samples_next : unsigned(ADC_DWIDTH-1 downto 0);
-
-signal done_s, tready_s : std_logic;
-signal avg_reg, avg_next: unsigned(ADC_DWIDTH-1 downto 0);
-signal restart_s, restart_os : std_logic;
-
-signal bram_clk  : std_logic;
-signal bram_rst  : std_logic;
-signal bram_en   : std_logic;
-signal bram_addr : std_logic_vector(MEM_AWIDTH-1 downto 0);
-signal bram_rddata : std_logic_vector(O_DWIDTH-1 downto 0);
-signal naverages_b : std_logic_vector(O_DWIDTH-1 downto 0);
-
-begin
-
-  s_axis_tready <= tready_s;
-  --avg_o         <= std_logic_vector(avg_reg);
-  done_o        <= done_s;
-
-  -- TDP RAM
-  tdp_ram_i : entity work.tdp_ram_pip
-  generic map(
-               AWIDTH       => MEM_AWIDTH,
-               DWIDTH       => O_DWIDTH
-             )
-  port map(
-            clka  => s_axis_aclk,
-            wea   => tdp_wea,
-            addra => std_logic_vector(tdp_addra_reg),
-            dia   => tdp_dia,
-
-            clkb  => bram_clk,
-            rstb  => bram_rst,
-            enb   => bram_en,
-            addrb => bram_addr,
-            dob   => bram_rddata
-          );
-
-  process(s_axis_aclk)
-  begin
-    if rising_edge(s_axis_aclk) then
-      if (s_axis_aresetn = '0') then
-        state_reg     <= ST_IDLE;
-        tdp_addra_reg <= (others => '0');
-        data_reg      <= (others => '0');
-        samples_reg   <= (others => '0');
-        avg_reg       <= (others => '0');
-      else
-        state_reg     <= state_next;
-        tdp_addra_reg <= tdp_addra_next;
-        data_reg      <= data_next;
-        samples_reg   <= samples_next;
-        avg_reg       <= avg_next;
-      end if;
-    end if;
-  end process;
-
-  --Next state logic
-  process(state_reg, en_i, start_i, trig_i, nsamples_i,
-    naverages_i, tdp_addra_reg, tdp_dia, data_reg, samples_reg,
-    s_axis_tvalid, s_axis_tdata, avg_reg, m_axis_tready, restart_os)
-    variable dinbv : std_logic_vector(O_DWIDTH-1 downto 0);
-  begin
-    state_next    <= state_reg;
-    tdp_wea       <= '0';
-    tdp_addra_next<= tdp_addra_reg;
-    data_next     <= data_reg;
-    samples_next  <= samples_reg;
-    tdp_dia       <= (others => '0'); 
-    tready_s      <= '0';
-    avg_next      <= avg_reg;
-    done_s        <= '0';
-
-    case state_reg is
-      when ST_IDLE => -- Start
-        --state_mon      <= "0000"; --state mon
-        samples_next   <= (others => '0');
-        tdp_addra_next <= (others => '0');
-        avg_next       <= (others => '0');
-        data_next      <= (others => '0');
-        if en_i = '1' and start_i = '1' then
-          state_next  <= ST_WAIT_TRIG;
-        else
-          state_next  <= ST_IDLE;
-        end if;
-
-      when ST_WAIT_TRIG => -- Wait for trigger
-        --state_mon <= "0001"; --state mon
-        if(trig_i = '1') then
-          state_next    <= ST_AVG_N1;
-        else
-          state_next <= ST_WAIT_TRIG;
-        end if;
-
-      when ST_AVG_N1 => 
-        --state_mon <= "0010"; 
-        if (s_axis_tvalid = '1') then
-        tready_s <= '1';
-        samples_next <= samples_reg + 1;
-        ASSIGN_N: for I in 0 to RATIO-1 loop
-          data_next(2*I_DWIDTH-1-I*2*ADC_DWIDTH downto 2*I_DWIDTH-(I+1)*2*ADC_DWIDTH) <=
-          std_logic_vector(signed(data_reg(2*I_DWIDTH-1-I*2*ADC_DWIDTH downto 2*I_DWIDTH-(I+1)*2*ADC_DWIDTH)) +
-          resize(signed(s_axis_tdata(I_DWIDTH-1-I*ADC_DWIDTH downto I_DWIDTH-((I+1)*ADC_DWIDTH))),ADC_DWIDTH));
-        end loop;
-        if(samples_reg = (unsigned(nsamples_i)/RATIO)-1) then
-          samples_next <= (others => '0');
-          state_next  <= ST_WRITE_AVG;
-        end if;
-      end if;
-
-      when ST_WRITE_AVG => 
-        --state_mon <= "0011"; 
-        dinbv := (others => '0');
-        ASSIGN_AVG1: for K in 0 to RATIO-1 loop
-          dinbv := std_logic_vector(signed(dinbv) + signed(data_reg(2*I_DWIDTH-1-K*2*ADC_DWIDTH downto 2*I_DWIDTH-(K+1)*2*ADC_DWIDTH)));
-        end loop;
-        tdp_dia <= dinbv;
-        tdp_wea <= '1';
-        data_next <= (others => '0');
-        tdp_addra_next <= tdp_addra_reg + 1;
-        avg_next <= avg_reg + 1;
-        if (avg_reg = unsigned(naverages_i)-1) then
-          state_next <= ST_FINISH;
-        else
-          state_next <= ST_WAIT_TRIG;
-        end if;
-
-      when ST_FINISH => 
-        --state_mon <= "0100"; 
-        done_s    <= '1';
-        if restart_os = '1' then
-          state_next <= ST_IDLE;
-        end if;
-
-    end case;
-  end process;
-
-  --lets synchronize the restart signal
-  os_restart_nt: entity work.edge_det
-  port map(
-            aclk     => s_axis_aclk,
-            aresetn  => s_axis_aresetn,
-            sig_i    => restart_s,
-            sig_o    => restart_os
-          );
-
-  naverages_b <= (31 downto 16 => '0') & naverages_i;
-  reader_i: entity work.bram_reader 
-  generic map(
-               MEM_DEPTH   => MEM_DEPTH,
-               MEM_AWIDTH  => MEM_AWIDTH,
-               AXIS_DWIDTH => O_DWIDTH
-             )
-  port map(
-
-            cfg_data_i     => naverages_b,
-            --cfg_data_i     => naverages_i,
-            --sts_data_o     => open,
-            done_i         => done_s,
-            send_i         => send_i,
-            restart_o      => restart_s,
-
-         -- Master side
-            aclk           => m_axis_aclk,
-            aresetn        => m_axis_aresetn,
-            m_axis_tready  => m_axis_tready,
-            m_axis_tdata   => m_axis_tdata,
-            m_axis_tvalid  => m_axis_tvalid,
-            m_axis_tlast   => m_axis_tlast, 
-            m_axis_tkeep   => m_axis_tkeep, 
-         -- BRAM port
-            bram_clk       => bram_clk,   
-            bram_rst       => bram_rst,
-            bram_en        => bram_en,
-            bram_addr      => bram_addr,
-            bram_rddata    => bram_rddata
-          );
-
-end rtl;
diff --git a/cores/axis_avgr32bits_v1_0/old_stuffs/avg_scope.vhd b/cores/axis_avgr32bits_v1_0/old_stuffs/avg_scope.vhd
deleted file mode 100644
index eca402c9810e80602b981baabb5fedb82505dc42..0000000000000000000000000000000000000000
--- a/cores/axis_avgr32bits_v1_0/old_stuffs/avg_scope.vhd
+++ /dev/null
@@ -1,365 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity avg_scope is
-  generic (
-            I_DWIDTH   : natural := 128; -- ADC data width x8
-            O_DWIDTH   : natural := 32;  -- AXI data width
-            ADC_DWIDTH : natural := 16;  -- ADC data width
-            MEM_AWIDTH : natural := 10;  --
-            MEM_DEPTH  : natural := 1024 -- Max 2**16
-          );
-  port (
-         -- Averager specific ports
-         start_i        : in std_logic;
-         send_i         : in std_logic;
-         trig_i         : in std_logic;
-         done_o         : out std_logic;
-         --state_mon      : out std_logic_vector(3 downto 0);
-         --nsamples Must be power of 2. Minimum is 8 and maximum is 2^AW
-         en_i           : in std_logic;
-         naverages_i    : in std_logic_vector(ADC_DWIDTH-1 downto 0);
-         nsamples_i     : in std_logic_vector(ADC_DWIDTH-1 downto 0);
-
-         --bram_en_o      : out std_logic;
-         --bram_addr_o    : out std_logic_vector(MEM_AWIDTH-1 downto 0);
-         --bram_rddata_o  : out std_logic_vector(O_DWIDTH-1 downto 0);
-         --bram_en_oo      : out std_logic;
-         --bram_addr_oo    : out std_logic_vector(MEM_AWIDTH-1 downto 0);
-         --bram_rddata_oo  : out std_logic_vector(O_DWIDTH-1 downto 0);
-         --avg_o          : out std_logic_vector(O_DWIDTH-1 downto 0);
-
-         --tdp_addra_o    : out std_logic_vector(11-1 downto 0);
-         --tdp_addrb_o    : out std_logic_vector(11-1 downto 0);
-
-         s_axis_cfg_aclk    : in std_logic;
-         s_axis_cfg_aresetn : in std_logic;
-
-         -- Slave side
-         s_axis_aclk    : in std_logic;
-         s_axis_aresetn : in std_logic;
-         s_axis_tready  : out std_logic;
-         s_axis_tvalid  : in std_logic;
-         s_axis_tdata   : in std_logic_vector(I_DWIDTH-1 downto 0);
-
-         -- Master side
-         m_axis_aclk    : in std_logic;
-         m_axis_aresetn : in std_logic;
-         m_axis_tready  : in std_logic;
-         m_axis_tdata   : out std_logic_vector(O_DWIDTH-1 downto 0);
-         m_axis_tvalid  : out std_logic;
-         m_axis_tlast   : out std_logic;
-         m_axis_tkeep   : out std_logic_vector(4-1 downto 0)
-       );
-end avg_scope;
-
-architecture rtl of avg_scope is
-
-  function log2c(n: integer) return integer is
-    variable m, p: integer;
-  begin
-    m := 0;
-    p := 1;
-    while p < n loop
-      m := m + 1;
-      p := p * 2;
-    end loop;
-    return m;
-  end log2c;
-
-  constant RATIO : natural := I_DWIDTH/ADC_DWIDTH;
-
-  type state_t is (
-  ST_IDLE,
-  ST_WAIT_TRIG,
-  ST_EN_TDPB,
-  ST_AVG_SCOPE,
-  ST_FINISH,
-  ST_WR_ZEROS
-);
-signal state_reg, state_next      : state_t;
---signal state_mon_reg, state_mon_next : std_logic_vector(3 downto 0);
-
-signal rstb_s   : std_logic;
-signal tdp_wea  : std_logic;
-signal tdp_addra_reg, tdp_addra_next : unsigned(log2c(MEM_DEPTH/RATIO)-1 downto 0);
-signal tdp_dia  : std_logic_vector(2*I_DWIDTH-1 downto 0);
-signal tdp_enb  : std_logic;
-signal tdp_addrb_reg, tdp_addrb_next : unsigned(log2c(MEM_DEPTH/RATIO)-1 downto 0);
-signal tdp_doa, tdp_dob              : std_logic_vector(2*I_DWIDTH-1 downto 0);
-signal addrb_s                       : std_logic_vector(log2c(MEM_DEPTH/RATIO)-1 downto 0);
-
-signal asy_rsta  : std_logic;
-signal asy_ena   : std_logic;
-signal asy_enb   : std_logic;
-signal asy_web   : std_logic;
-signal asy_doa   : std_logic_vector(ADC_DWIDTH-1 downto 0);
-
-signal done_s, tready_s : std_logic;
-signal avg_reg, avg_next: unsigned(ADC_DWIDTH-1 downto 0);
-signal restart_s, restart_os : std_logic;
-
-signal bram_clk  : std_logic;
-signal bram_rst  : std_logic;
-signal bram_en   : std_logic;
-signal bram_addr : std_logic_vector(MEM_AWIDTH-1 downto 0);
-signal bram_rddata : std_logic_vector(O_DWIDTH-1 downto 0);
-signal nsamples_b  : std_logic_vector(O_DWIDTH-1 downto 0);
-
-begin
-
-  --state_mon <= state_mon_reg;
-  --tdp_addra_o <= std_logic_vector(tdp_addra_reg);
-  --tdp_addrb_o <= std_logic_vector(tdp_addrb_reg);
-
-  s_axis_tready <= tready_s;
-  --avg_o         <= std_logic_vector(avg_reg);
-  done_o <= done_s;
-
-  -- TDP RAM
-  tdp_ram_i : entity work.tdp_ram_pip
-  generic map(
-               AWIDTH       => log2c(MEM_DEPTH/RATIO),
-               DWIDTH       => 2*I_DWIDTH
-             )
-  port map(
-            clka  => s_axis_aclk,
-            --rsta  => rsta_s,
-            wea   => tdp_wea,
-            addra => std_logic_vector(tdp_addra_reg),
-            dia   => tdp_dia,
-
-            clkb  => s_axis_aclk,
-            rstb  => rstb_s,
-            enb   => tdp_enb, --'1',
-            addrb => std_logic_vector(tdp_addrb_reg),
-            dob   => tdp_dob
-          );
-
-  -- ASYMMETRIC RAM
-  -- Port A -> AXI IF
-  -- Port B -> same as WIDER BRAM
-  asy_ram_i : entity work.asym_ram_sdp_write_wider
-  generic map
-  (
-    WIDTHA      => O_DWIDTH,
-    SIZEA       => MEM_DEPTH,
-    ADDRWIDTHA  => MEM_AWIDTH,
-    WIDTHB      => 2*I_DWIDTH,
-    SIZEB       => (MEM_DEPTH/RATIO),
-    ADDRWIDTHB  => log2c(MEM_DEPTH/RATIO)
-  )
-  port map
-  (
-    clkA        => bram_clk,
-    rstA        => bram_rst,
-    enA         => bram_en, 
-    addrA       => bram_addr, 
-    doA         => bram_rddata, 
-
-    --portB same as portA in tdp_ram
-    clkB        => s_axis_aclk,
-    weB         => tdp_wea,
-    addrB       => std_logic_vector(tdp_addra_reg),
-    diB         => tdp_dia
-  );
-
-  --debug signals
-  --lets synchronize the en signal
-  --sync_bram_en: entity work.sync
-  --port map(
-  --          aclk     => s_axis_aclk,
-  --          aresetn  => s_axis_aresetn,
-  --          in_async => bram_en,
-  --          out_sync => bram_en_o
-  --        );
-  --bram_en_oo <= bram_en;
-
-  --lets synchronize the addr signal
-  --sync_bram_addr: entity work.n_sync
-  --generic map(
-  --             N => MEM_AWIDTH
-  --           )
-  --port map(
-  --          aclk     => s_axis_aclk,
-  --          aresetn  => s_axis_aresetn,
-  --          in_async => bram_addr,
-  --          out_sync => bram_addr_o
-  --        );
-  --bram_addr_oo <= bram_addr;
-
-  ----lets synchronize the en signal
-  --sync_bram_rddata: entity work.n_sync
-  --generic map(
-  --             N => O_DWIDTH
-  --           )
-  --port map(
-  --          aclk     => s_axis_aclk,
-  --          aresetn  => s_axis_aresetn,
-  --          in_async => bram_rddata,
-  --          out_sync => bram_rddata_o
-  --        );
-  --bram_rddata_oo <= bram_rddata;
-
-  process(s_axis_aclk)
-  begin
-    if rising_edge(s_axis_aclk) then
-      if (s_axis_aresetn = '0') then
-        state_reg     <= ST_IDLE;
-        --state_mon_reg <= (others => '0');
-        tdp_addra_reg <= (others => '0');
-        tdp_addrb_reg <= (others => '0');
-        avg_reg       <= (others => '0');
-      else
-        state_reg     <= state_next;
-        --state_mon_reg <= state_mon_next;
-        tdp_addra_reg <= tdp_addra_next;
-        tdp_addrb_reg <= tdp_addrb_next;
-        avg_reg       <= avg_next;
-      end if;
-    end if;
-  end process;
-
-  --tdp_addra_next <= tdp_addrb_reg;
-
-  --Next state logic
-  --process(state_reg, state_mon_reg, en_i, start_i, trig_i, nsamples_i, naverages_i,
-  process(state_reg, en_i, start_i, trig_i, nsamples_i, naverages_i,
-    tdp_addra_reg, tdp_addrb_reg, tdp_dia, tdp_dob, s_axis_tvalid, s_axis_tdata,
-    avg_reg, m_axis_tready, restart_os)
-  begin
-    state_next    <= state_reg;
-    --state_mon_next<= state_mon_reg;
-    rstb_s        <= '0';
-    tdp_wea       <= '0';
-    tdp_addra_next<= tdp_addra_reg;
-    tdp_dia       <= (others => '0'); 
-    tdp_enb       <= '0';
-    tdp_addrb_next<= tdp_addrb_reg;
-    asy_rsta      <= '1';
-    asy_ena       <= '0';
-    tready_s      <= '0';
-    avg_next      <= avg_reg;
-    done_s        <= '0';
-
-    case state_reg is
-      when ST_IDLE => -- Start
-        rstb_s         <= '1';
-        tdp_addra_next <= (others => '0');
-        tdp_addrb_next <= (others => '0');
-        avg_next       <= (others => '0');
-        if en_i = '1' and start_i = '1' then
-          state_next  <= ST_WAIT_TRIG;
-          --state_mon_next <= "0001"; 
-        else
-          state_next  <= ST_IDLE;
-          --state_mon_next <= (others => '0'); 
-        end if;
-
-      when ST_WAIT_TRIG => -- Wait for trigger
-        if(trig_i = '1') then
-          state_next  <= ST_EN_TDPB;
-          --state_mon_next <= "0010"; 
-        else
-          state_next <= ST_WAIT_TRIG;
-          --state_mon_next <= "0001"; 
-        end if;
-
-      when ST_EN_TDPB =>
-        if (s_axis_tvalid = '1') then
-          tdp_enb        <= '1';
-          tdp_addrb_next <= tdp_addrb_reg + 1;
-          state_next     <= ST_AVG_SCOPE;
-          --state_mon_next <= "0011"; 
-        end if;
-
-      when ST_AVG_SCOPE => -- Measure
-        if (s_axis_tvalid = '1') then
-          tready_s <= '1';
-          tdp_enb  <= '1';
-          tdp_wea  <= '1';
-          tdp_addra_next <= tdp_addra_reg + 1;
-          tdp_addrb_next <= tdp_addrb_reg + 1;
-          ASSIGN_G1: for I in 0 to RATIO-1 loop
-            tdp_dia(2*I_DWIDTH-1-I*2*ADC_DWIDTH downto 2*I_DWIDTH-(I+1)*2*ADC_DWIDTH) <=
-            std_logic_vector(signed(tdp_dob(2*I_DWIDTH-1-I*2*ADC_DWIDTH downto 2*I_DWIDTH-(I+1)*2*ADC_DWIDTH)) +
-            resize(signed(s_axis_tdata(I_DWIDTH-1-I*ADC_DWIDTH downto I_DWIDTH-((I+1)*ADC_DWIDTH))),O_DWIDTH));
-          end loop;
-          if(tdp_addra_reg = (unsigned(nsamples_i)/RATIO)-1) then
-            tdp_addra_next <= (others => '0');
-            tdp_addrb_next <= (others => '0');
-            avg_next <= avg_reg + 1;
-            if (avg_reg = unsigned(naverages_i)-1) then
-              state_next  <= ST_FINISH;
-              --state_mon_next <= "0100"; 
-            else
-              state_next  <= ST_WAIT_TRIG;
-              --state_mon_next <= "0001"; 
-            end if;
-          end if;
-        else 
-          state_next <= ST_AVG_SCOPE;
-          --state_mon_next <= "0011"; 
-        end if;
-
-      when ST_FINISH => 
-        done_s    <= '1';
-        if restart_os = '1' then
-          state_next <= ST_WR_ZEROS;
-          --state_mon_next <= "0101";
-        end if;
-
-      when ST_WR_ZEROS => 
-        tdp_wea   <= '1';
-        tdp_addra_next <= tdp_addra_reg + 1; 
-        if (tdp_addra_reg = (unsigned(nsamples_i)/RATIO)-1) then
-          state_next <= ST_IDLE;
-          --state_mon_next <= (others => '0');
-        end if;
-
-    end case;
-  end process;
-
-  --lets synchronize the restart signal
-  os_restart_as: entity work.edge_det
-  port map(
-            aclk     => s_axis_aclk,
-            aresetn  => s_axis_aresetn,
-            sig_i    => restart_s,
-            sig_o    => restart_os
-          );
-
-  nsamples_b <= (31 downto 16 => '0') & nsamples_i;
-  reader_i: entity work.bram_reader 
-  generic map(
-            MEM_DEPTH   => MEM_DEPTH,
-            MEM_AWIDTH  => MEM_AWIDTH,
-            AXIS_DWIDTH => O_DWIDTH
-          )
-  port map(
-
-         cfg_data_i     => nsamples_b,
-         --cfg_data_i     => nsamples_i,
-         --sts_data_o     => open,
-         done_i         => done_s,
-         send_i         => send_i, 
-         restart_o      => restart_s,
-
-         -- Master side
-         aclk           => m_axis_aclk,
-         aresetn        => m_axis_aresetn,
-         m_axis_tready  => m_axis_tready,
-         m_axis_tdata   => m_axis_tdata,
-         m_axis_tvalid  => m_axis_tvalid,
-         m_axis_tlast   => m_axis_tlast, 
-         m_axis_tkeep   => m_axis_tkeep, 
-          -- BRAM port
-         bram_clk       => bram_clk,   
-         bram_rst       => bram_rst,
-         bram_en        => bram_en,
-         bram_addr      => bram_addr,
-         bram_rddata    => bram_rddata
-       );
-
-end rtl;
diff --git a/cores/axis_avgr32bits_v1_0/old_stuffs/bram_reader.vhd b/cores/axis_avgr32bits_v1_0/old_stuffs/bram_reader.vhd
deleted file mode 100644
index 8b9376b2903e93739bcd69c2bbe47df66e30fb31..0000000000000000000000000000000000000000
--- a/cores/axis_avgr32bits_v1_0/old_stuffs/bram_reader.vhd
+++ /dev/null
@@ -1,150 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity bram_reader is
-  generic (
-            MEM_DEPTH   : natural := 1024;
-            MEM_AWIDTH  : natural := 10;
-            AXIS_DWIDTH : natural := 32
-          );
-  port (
-         -- System signals
-         aclk           : in std_logic;
-         aresetn        : in std_logic;
-
-         cfg_data_i     : in std_logic_vector(AXIS_DWIDTH-1 downto 0);
-         --sts_data_o     : out std_logic_vector(AXIS_DWIDTH-1 downto 0);
-         done_i         : in std_logic;
-         send_i         : in std_logic;
-         restart_o      : out std_logic;
-
-         -- Master side
-         m_axis_tready  : in std_logic;
-         m_axis_tdata   : out std_logic_vector(AXIS_DWIDTH-1 downto 0);
-         m_axis_tvalid  : out std_logic;
-         m_axis_tlast   : out std_logic;
-         m_axis_tkeep   : out std_logic_vector(4-1 downto 0);
-
-         -- BRAM port
-         bram_clk       : out std_logic;
-         bram_rst       : out std_logic;
-         bram_en        : out std_logic;
-         bram_addr      : out std_logic_vector(MEM_AWIDTH-1 downto 0);
-         bram_rddata    : in std_logic_vector(AXIS_DWIDTH-1 downto 0)
-       );
-end bram_reader;
-
-architecture rtl of bram_reader is
-
-  type state_t is (
-  ST_IDLE,
-  ST_EN_BRAM,
-  ST_SEND_DATA,
-  ST_TLAST,
-  ST_FINISH
-);
-signal state_reg, state_next   : state_t;
-
-signal addr_reg, addr_next     : unsigned(MEM_AWIDTH-1 downto 0);
-signal tlast_s, rst_s, en_s    : std_logic;
-signal tvalid_s                : std_logic;
-signal restart_s               : std_logic;
-signal tkeep_s                 : std_logic_vector(4-1 downto 0);
---signal bram_st_mon             : std_logic_vector(4-1 downto 0);
-
-begin
-
-  process(aclk)
-  begin
-    if rising_edge(aclk) then
-      if aresetn = '0' then
-        state_reg  <= ST_IDLE;
-        addr_reg   <= (others => '0');
-      else 
-        state_reg  <= state_next;
-        addr_reg   <= addr_next;
-      end if;
-    end if;
-  end process;
-
-  --Next state logic
-  process(state_reg, addr_reg, done_i, send_i, m_axis_tready,
-    cfg_data_i)
-  begin
-    state_next   <= state_reg;
-    addr_next    <= addr_reg;
-    tvalid_s     <= '0';
-    tlast_s      <= '0';
-    restart_s    <= '0';
-    en_s         <= '0';
-    rst_s        <= '0';
-    tkeep_s      <= (others => '0');
-
-    case state_reg is
-      when ST_IDLE => 
-        --bram_st_mon <= "0000"; --state mon
-        rst_s       <= '1';
-        addr_next  <= (others => '0');
-        if (done_i = '1') and (send_i = '1') then
-          state_next  <= ST_EN_BRAM;
-        else
-          state_next  <= ST_IDLE;
-        end if;
-
-      when ST_EN_BRAM =>
-        --bram_st_mon <= "0001"; --state mon
-        if m_axis_tready = '1' then
-          en_s <= '1';
-          addr_next <= addr_reg + 1;
-          state_next  <= ST_SEND_DATA;
-        else
-          state_next <= ST_EN_BRAM;
-        end if;
-
-      when ST_SEND_DATA =>
-        --bram_st_mon <= "0010"; --state mon
-        tvalid_s <= '1';
-        tkeep_s  <= (others => '1');
-        if m_axis_tready = '1' then
-          en_s     <= '1';
-          addr_next <= addr_reg + 1;
-          if (addr_reg = unsigned(cfg_data_i)-1) then
-            --addr_next <= (others => '0');
-            state_next <= ST_TLAST;
-          else
-            state_next <= ST_SEND_DATA;
-          end if;
-        else 
-          state_next <= ST_SEND_DATA;
-        end if;
-
-      when ST_TLAST =>
-        --bram_st_mon <= "0011";
-        tvalid_s <= '1';
-        tkeep_s  <= (others => '1');
-        tlast_s <= '1';
-        state_next <= ST_FINISH;
-
-      when ST_FINISH =>
-        --bram_st_mon <= "0100"; --state mon
-        restart_s <= '1';
-        state_next <= ST_IDLE;
-
-    end case;
-  end process;
-
-  --sts_data_o <= std_logic_vector(resize(addr_reg,AXIS_DWIDTH));
-
-  m_axis_tdata  <= bram_rddata;
-  m_axis_tvalid <= tvalid_s;
-  m_axis_tlast  <= tlast_s;
-  m_axis_tkeep  <= tkeep_s;
-
-  bram_clk <= aclk;
-  bram_rst <= rst_s;
-  bram_en  <= en_s;
-  bram_addr <= std_logic_vector(addr_reg);
-  restart_o <= restart_s; 
-
-end rtl;
diff --git a/cores/axis_lpf_v1_0/axis_lpf.vhd b/cores/axis_lpf_v1_0/axis_lpf.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b1484941442b228249644bb880d004dfe442e4af
--- /dev/null
+++ b/cores/axis_lpf_v1_0/axis_lpf.vhd
@@ -0,0 +1,71 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity lpf_iir is
+generic (
+  AXIS_TDATA_WIDTH: natural := 32;
+  ADC_DATA_WIDTH  : natural := 14
+);
+port(
+  aclk       : in std_logic;
+  aresetn    : in std_logic;
+  tc_i       : in std_logic_vector (AXIS_TDATA_WIDTH-1 downto 0); -- time constant: parameter equal to e^-1/d where d is number of samples time constant
+  data_o     : out std_logic_vector (AXIS_TDATA_WIDTH-1 downto 0);
+
+  -- Slave side
+  s_axis_tdata : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);  
+  s_axis_tready: out std_logic;
+  s_axis_tvalid: in std_logic; 
+
+  -- Master side
+  m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+  m_axis_tready: in std_logic;
+  m_axis_tvalid: out std_logic
+
+);
+end lpf_iir;
+
+architecture rtl of lpf_iir is
+
+constant one               : std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0) := "01111111111111111111111111111111";
+
+signal sig_reg, sig_next   : std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+signal data_reg, data_next : std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+
+signal mult_out            : std_logic_vector(2*AXIS_TDATA_WIDTH-1 downto 0);
+
+signal a0                  : std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+signal b1                  : std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+
+begin
+
+  process(aclk)
+  begin
+  	if(aresetn = '0') then
+  		sig_reg <= s_axis_tdata;
+      data_reg <= (others => '0');
+  	elsif rising_edge(aclk) then
+  		sig_reg <= sig_next;
+      data_reg <= data_next;
+  	end if;
+  end process;
+
+  --next state logic
+  sig_next <= s_axis_tdata;
+  s_axis_tready <= m_axis_tready;
+  m_axis_tvalid <= s_axis_tvalid;
+  
+  a0 <= std_logic_vector(signed(one) - signed(tc_i)); --  & (AXIS_TDATA_WIDTH-2 downto 0 => '1') - signed(tc_i)); 
+  b1 <= tc_i;  
+  
+  mult_out <= std_logic_vector(signed(a0)*signed(s_axis_tdata) + signed(b1)*signed(sig_reg));
+  
+  data_next <= mult_out((2*AXIS_TDATA_WIDTH)-1) & mult_out(2*AXIS_TDATA_WIDTH-2 downto 32);
+  
+  data_o <= data_reg;
+  
+  m_axis_tdata <= mult_out((2*AXIS_TDATA_WIDTH)-1) & mult_out(2*AXIS_TDATA_WIDTH-2 downto 32);
+
+end rtl;
diff --git a/cores/axis_lpf_v1_0/core_config.tcl b/cores/axis_lpf_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1128d10e42f4631b14988ec39a088b0111159287
--- /dev/null
+++ b/cores/axis_lpf_v1_0/core_config.tcl
@@ -0,0 +1,21 @@
+set display_name {AXI4-Stream IIR Low Pass Filter}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the M_AXIS data bus.}
+core_parameter ADC_DATA_WIDTH {ADC DATA WIDTH} {Width of the ADC data bus.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core m_axis]
+set_property NAME M_AXIS $bus
+set_property INTERFACE_MODE master $bus
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axis]
+set_property NAME S_AXIS $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::add_bus_parameter ASSOCIATED_BUSIF $bus]
+set_property VALUE M_AXIS:S_AXIS $parameter