From 94b5793ab67400f51b9270cedefd6200cbb7220e Mon Sep 17 00:00:00 2001
From: Horacio Arnaldi <lharnaldi@gmail.com>
Date: Fri, 5 Aug 2022 09:34:29 -0300
Subject: [PATCH] Remuevo algunos cores que no son necesarios para LAGO
---
Makefile | 13 +---
.../axi_axis_reader_v1_0/axi_axis_reader.vhd | 77 +++++++++++++++++++
cores/axi_axis_reader_v1_0/core_config.tcl | 21 +++++
3 files changed, 99 insertions(+), 12 deletions(-)
create mode 100644 cores/axi_axis_reader_v1_0/axi_axis_reader.vhd
create mode 100644 cores/axi_axis_reader_v1_0/core_config.tcl
diff --git a/Makefile b/Makefile
index c42f914..a9a1e50 100644
--- a/Makefile
+++ b/Makefile
@@ -17,32 +17,22 @@ CORES = axi_axis_reader_v1_0 \
axi_bram_reader_v1_0 \
axi_cfg_register_v1_0 \
axi_sts_register_v1_0 \
- axi_time_trig_gen_v1_0 \
- axis_avgr16bits_v1_0 \
- axis_avgr32bits_v1_0 \
- axis_avgr_v1_0 \
axis_bram_reader_v1_0 \
axis_bram_writer_v1_0 \
axis_constant_v1_0 \
axis_counter_v1_0 \
axis_dc_removal_v1_0 \
- axis_decimator_v1_0 \
axis_fifo_v1_0 \
axis_generator_v1_0 \
axis_gpio_reader_i_v1_0 \
axis_gpio_reader_v1_0 \
axis_histogram_v1_0 \
axis_histogram_v1_1 \
- axis_interpolator_v1_0 \
axis_lago_trigger_v1_0 \
axis_lago_trigger_v1_1 \
axis_lago_trigger_v1_2 \
axis_lago_trigger_v1_3 \
- axis_lfsr_v1_0 \
- axis_lpf_v1_0 \
- axis_oscilloscope_v1_0 \
axis_packetizer_v1_0 \
- axis_phase_generator_v1_0 \
axis_ram_writer_v1_0 \
axis_rp_adc_v1_0 \
axis_rp_adc_v3_0 \
@@ -65,8 +55,7 @@ CORES = axi_axis_reader_v1_0 \
pps_gen_v1_1 \
pwm_gen_v1_0 \
ramp_gen_v1_0 \
- selector_v1_0 \
- time_trig_gen_v1_0
+ selector_v1_0
VIVADO = vivado -nolog -nojournal -mode batch
XSCT = xsct
diff --git a/cores/axi_axis_reader_v1_0/axi_axis_reader.vhd b/cores/axi_axis_reader_v1_0/axi_axis_reader.vhd
new file mode 100644
index 0000000..7461116
--- /dev/null
+++ b/cores/axi_axis_reader_v1_0/axi_axis_reader.vhd
@@ -0,0 +1,77 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axi_axis_reader is
+ generic (
+ AXI_DATA_WIDTH : natural := 32;
+ AXI_ADDR_WIDTH : natural := 32
+);
+port (
+ -- System signals
+ aclk : in std_logic;
+ aresetn : in std_logic;
+
+ -- Slave side
+ s_axi_awaddr : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); -- AXI4-Lite slave: Write address
+ s_axi_awvalid : in std_logic; -- AXI4-Lite slave: Write address valid
+ s_axi_awready : out std_logic; -- AXI4-Lite slave: Write address ready
+ s_axi_wdata : in std_logic_vector(AXI_DATA_WIDTH-1 downto 0); -- AXI4-Lite slave: Write data
+ s_axi_wvalid : in std_logic; -- AXI4-Lite slave: Write data valid
+ s_axi_wready : out std_logic; -- AXI4-Lite slave: Write data ready
+ s_axi_bresp : out std_logic_vector(1 downto 0); -- AXI4-Lite slave: Write response
+ s_axi_bvalid : out std_logic; -- AXI4-Lite slave: Write response valid
+ s_axi_bready : in std_logic; -- AXI4-Lite slave: Write response ready
+ s_axi_araddr : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); -- AXI4-Lite slave: Read address
+ s_axi_arvalid : in std_logic; -- AXI4-Lite slave: Read address valid
+ s_axi_arready : out std_logic; -- AXI4-Lite slave: Read address ready
+ s_axi_rdata : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0); -- AXI4-Lite slave: Read data
+ s_axi_rresp : out std_logic_vector(1 downto 0); -- AXI4-Lite slave: Read data response
+ s_axi_rvalid : out std_logic; -- AXI4-Lite slave: Read data valid
+ s_axi_rready : in std_logic; -- AXI4-Lite slave: Read data ready
+
+ -- Slave side
+ s_axis_tready : out std_logic;
+ s_axis_tdata : in std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
+ s_axis_tvalid : in std_logic
+);
+end axi_axis_reader;
+
+architecture rtl of axi_axis_reader is
+
+signal int_rvalid_reg, int_rvalid_next : std_logic;
+signal int_rdata_reg, int_rdata_next : std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
+
+begin
+
+ process(aclk)
+ begin
+ if rising_edge(aclk) then
+ if (aresetn = '0') then
+ int_rvalid_reg <= '0';
+ int_rdata_reg <= (others => '0');
+ else
+ int_rvalid_reg <= int_rvalid_next;
+ int_rdata_reg <= int_rdata_next;
+ end if;
+ end if;
+ end process;
+
+ int_rvalid_next <= '1' when (s_axi_arvalid = '1') else
+ '0' when (s_axi_rready = '1') and (int_rvalid_reg = '1') else
+ int_rvalid_reg;
+
+ int_rdata_next <= s_axis_tdata when (s_axi_arvalid = '1') and (s_axis_tvalid = '1') else
+ (others => '0') when (s_axi_arvalid = '1') and (s_axis_tvalid = '0') else
+ int_rdata_reg;
+
+ s_axi_rresp <= (others => '0');
+
+ s_axi_arready <= '1';
+ s_axi_rdata <= int_rdata_reg;
+ s_axi_rvalid <= int_rvalid_reg;
+
+ s_axis_tready <= s_axi_rready and int_rvalid_reg;
+
+end rtl;
diff --git a/cores/axi_axis_reader_v1_0/core_config.tcl b/cores/axi_axis_reader_v1_0/core_config.tcl
new file mode 100644
index 0000000..7b45e22
--- /dev/null
+++ b/cores/axi_axis_reader_v1_0/core_config.tcl
@@ -0,0 +1,21 @@
+set display_name {AXI AXI4-Stream Reader}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXI_DATA_WIDTH {AXI DATA WIDTH} {Width of the AXI data bus.}
+core_parameter AXI_ADDR_WIDTH {AXI ADDR WIDTH} {Width of the AXI address bus.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axi]
+set_property NAME S_AXI $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axis]
+set_property NAME S_AXIS $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE S_AXIS:S_AXI $parameter
--
GitLab