From 8dd55a0ed17354b84c939feb107fb4eb487fa3be Mon Sep 17 00:00:00 2001
From: lharnaldi <lharnaldi@gmail.com>
Date: Fri, 5 Aug 2022 10:16:07 -0300
Subject: [PATCH] Agrego el core time_trig_gen_v1_0
---
Makefile | 3 +-
cores/time_trig_gen_v1_0/core_config.tcl | 7 ++++
cores/time_trig_gen_v1_0/time_trig_gen.vhd | 49 ++++++++++++++++++++++
3 files changed, 58 insertions(+), 1 deletion(-)
create mode 100644 cores/time_trig_gen_v1_0/core_config.tcl
create mode 100644 cores/time_trig_gen_v1_0/time_trig_gen.vhd
diff --git a/Makefile b/Makefile
index 0d4a2ba..d09bf6e 100644
--- a/Makefile
+++ b/Makefile
@@ -60,7 +60,8 @@ CORES = axi_axis_reader_v1_0 \
pps_gen_v1_1 \
pwm_gen_v1_0 \
ramp_gen_v1_0 \
- selector_v1_0
+ selector_v1_0 \
+ time_trig_gen_v1_0
VIVADO = vivado -nolog -nojournal -mode batch
XSCT = xsct
diff --git a/cores/time_trig_gen_v1_0/core_config.tcl b/cores/time_trig_gen_v1_0/core_config.tcl
new file mode 100644
index 0000000..f931d39
--- /dev/null
+++ b/cores/time_trig_gen_v1_0/core_config.tcl
@@ -0,0 +1,7 @@
+set display_name {Time Trigger Generator}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
diff --git a/cores/time_trig_gen_v1_0/time_trig_gen.vhd b/cores/time_trig_gen_v1_0/time_trig_gen.vhd
new file mode 100644
index 0000000..660101b
--- /dev/null
+++ b/cores/time_trig_gen_v1_0/time_trig_gen.vhd
@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity time_trig_gen is
+ port (
+ aclk : in std_logic;
+ aresetn : in std_logic;
+ cfg_data: in std_logic_vector(32-1 downto 0);
+ trig_o : out std_logic
+ );
+end time_trig_gen;
+
+architecture rtl of time_trig_gen is
+
+ signal cntr_reg, cntr_next : std_logic_vector(32-1 downto 0);
+ signal trig_reg, trig_next : std_logic;
+ signal comp_reg, comp_next : std_logic;
+
+begin
+
+ process(aclk)
+ begin
+ if rising_edge(aclk) then
+ if (aresetn = '0') then
+ cntr_reg <= (others => '0');
+ trig_reg <= '0';
+ comp_reg <= '0';
+ else
+ cntr_reg <= cntr_next;
+ trig_reg <= trig_next;
+ comp_reg <= comp_next;
+ end if;
+ end if;
+ end process;
+
+ comp_next <= '0' when (unsigned(cntr_reg) = unsigned(cfg_data)-1) else
+ '1';
+
+ cntr_next <= std_logic_vector(unsigned(cntr_reg) + 1) when (comp_reg = '1') else
+ (others => '0') when (comp_reg = '0') else --reset
+ cntr_reg;
+
+ trig_next <= '1' when (unsigned(cntr_reg) = unsigned(cfg_data)-1) else
+ '0';
+
+ trig_o <= trig_reg;
+
+end rtl;
--
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