diff --git a/Makefile b/Makefile
index 0d4a2ba9e9e383c1d6ee126132115163a53b4c44..d09bf6e19fb36a7a5415c8f6a04da5c9616d6ec9 100644
--- a/Makefile
+++ b/Makefile
@@ -60,7 +60,8 @@ CORES = axi_axis_reader_v1_0 \
 				pps_gen_v1_1 \
 				pwm_gen_v1_0 \
 				ramp_gen_v1_0 \
-				selector_v1_0 
+				selector_v1_0 \
+				time_trig_gen_v1_0
 
 VIVADO = vivado -nolog -nojournal -mode batch
 XSCT = xsct
diff --git a/cores/time_trig_gen_v1_0/core_config.tcl b/cores/time_trig_gen_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f931d39ff2769c59ab02c91c0271fbc88c79cb54
--- /dev/null
+++ b/cores/time_trig_gen_v1_0/core_config.tcl
@@ -0,0 +1,7 @@
+set display_name {Time Trigger Generator}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
diff --git a/cores/time_trig_gen_v1_0/time_trig_gen.vhd b/cores/time_trig_gen_v1_0/time_trig_gen.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..660101b10241b849d2352863c6a4d99f5f491e21
--- /dev/null
+++ b/cores/time_trig_gen_v1_0/time_trig_gen.vhd
@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity time_trig_gen is
+  port (
+    aclk    : in std_logic;
+    aresetn : in std_logic;
+    cfg_data: in std_logic_vector(32-1 downto 0);
+    trig_o  : out std_logic
+    );
+end time_trig_gen;
+
+architecture rtl of time_trig_gen is
+
+  signal cntr_reg, cntr_next : std_logic_vector(32-1 downto 0);
+  signal trig_reg, trig_next : std_logic;
+  signal comp_reg, comp_next : std_logic;
+
+begin
+
+ process(aclk)
+  begin
+    if rising_edge(aclk) then
+      if (aresetn = '0') then
+        cntr_reg <= (others => '0');
+        trig_reg <= '0';
+        comp_reg <= '0';
+      else
+        cntr_reg <= cntr_next;
+        trig_reg <= trig_next;
+        comp_reg <= comp_next;
+      end if;
+    end if;
+  end process;
+  
+  comp_next <= '0' when (unsigned(cntr_reg) = unsigned(cfg_data)-1) else 
+               '1';
+
+  cntr_next <= std_logic_vector(unsigned(cntr_reg) + 1) when (comp_reg = '1') else
+               (others => '0') when (comp_reg = '0') else --reset
+               cntr_reg;
+
+  trig_next <= '1' when (unsigned(cntr_reg) = unsigned(cfg_data)-1) else 
+               '0';
+ 
+  trig_o    <= trig_reg;
+
+end rtl;