From 8b8aaa2b879ab53a1a8cd0cd4da29cd90e9866a6 Mon Sep 17 00:00:00 2001 From: Horacio Arnaldi <lharnaldi@gmail.com> Date: Thu, 25 Aug 2022 09:05:22 -0300 Subject: [PATCH] Simple arreglo de conexiones en ram_writer --- projects/lago_v1_3/block_design.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/lago_v1_3/block_design.tcl b/projects/lago_v1_3/block_design.tcl index c8dea1e..e07ae62 100644 --- a/projects/lago_v1_3/block_design.tcl +++ b/projects/lago_v1_3/block_design.tcl @@ -221,8 +221,8 @@ module fadc_0 { writer_0/sts_data sts_0/sts_data pps_0/resetn_i rst_1/peripheral_aresetn pps_0/int_o axi_intc_0/intr - writer_0/cfg_data cfg_ram_wr/dout writer_0/M_AXI ps_0/S_AXI_ACP + writer_0/cfg_data cfg_ram_wr/dout tlast_gen_0/pkt_length nsamples/dout pps_0/gpsen_i gpsen/dout pps_0/pps_i exp_n_tri_io -- GitLab