diff --git a/projects/adc_recorder_old/adc-recorder.c b/projects/adc_recorder_old/adc-recorder.c
new file mode 100644
index 0000000000000000000000000000000000000000..c8c6e7ba100ee61ce849e72981afc9bd3930eee6
--- /dev/null
+++ b/projects/adc_recorder_old/adc-recorder.c
@@ -0,0 +1,58 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+
+int main()
+{
+ int fd, i;
+ int16_t value[2];
+ void *cfg, *ram;
+ char *name = "/dev/mem";
+
+ if((fd = open(name, O_RDWR)) < 0)
+ {
+ perror("open");
+ return 1;
+ }
+
+ cfg = mmap(NULL, sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x40000000);
+ ram = mmap(NULL, 1024*sysconf(_SC_PAGESIZE), PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0x1E000000);
+
+ // reset writer
+ *((uint32_t *)(cfg + 0)) &= ~4;
+ *((uint32_t *)(cfg + 0)) |= 4;
+
+ // reset fifo and filters
+ *((uint32_t *)(cfg + 0)) &= ~1;
+ *((uint32_t *)(cfg + 0)) |= 1;
+
+ // wait 1 second
+ sleep(1);
+
+ // enter reset mode for packetizer
+ *((uint32_t *)(cfg + 0)) &= ~2;
+
+ // set number of samples
+ *((uint32_t *)(cfg + 4)) = 1024 * 1024 - 1;
+
+ // enter normal mode
+ *((uint32_t *)(cfg + 0)) |= 2;
+
+ // wait 1 second
+ sleep(1);
+
+ // print IN1 and IN2 samples
+ for(i = 0; i < 1024 * 1024; ++i)
+ {
+ value[0] = *((int16_t *)(ram + 4*i + 0));
+ value[1] = *((int16_t *)(ram + 4*i + 2));
+ printf("%5d %5d\n", value[0], value[1]);
+ }
+
+ munmap(cfg, sysconf(_SC_PAGESIZE));
+ munmap(ram, sysconf(_SC_PAGESIZE));
+
+ return 0;
+}
diff --git a/projects/adc_recorder_old/block_design.tcl b/projects/adc_recorder_old/block_design.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..2658cdb573969173151812a10bd7c5d6a237c357
--- /dev/null
+++ b/projects/adc_recorder_old/block_design.tcl
@@ -0,0 +1,244 @@
+# Create clk_wiz
+cell xilinx.com:ip:clk_wiz pll_0 {
+ PRIMITIVE PLL
+ PRIM_IN_FREQ.VALUE_SRC USER
+ PRIM_IN_FREQ 125.0
+ PRIM_SOURCE Differential_clock_capable_pin
+ CLKOUT1_USED true
+ CLKOUT1_REQUESTED_OUT_FREQ 125.0
+ USE_RESET false
+} {
+ clk_in1_p adc_clk_p_i
+ clk_in1_n adc_clk_n_i
+}
+
+# Create processing_system7
+cell xilinx.com:ip:processing_system7 ps_0 {
+ PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
+ PCW_USE_S_AXI_HP0 1
+} {
+ M_AXI_GP0_ACLK pll_0/clk_out1
+ S_AXI_HP0_ACLK pll_0/clk_out1
+}
+
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
+ make_external {FIXED_IO, DDR}
+ Master Disable
+ Slave Disable
+} [get_bd_cells ps_0]
+
+# Create xlconstant
+cell xilinx.com:ip:xlconstant const_0
+
+# Create proc_sys_reset
+cell xilinx.com:ip:proc_sys_reset rst_0 {} {
+ ext_reset_in const_0/dout
+}
+
+# GPIO
+
+# Delete input/output port
+delete_bd_objs [get_bd_ports exp_p_tri_io]
+
+# Create output port
+create_bd_port -dir O -from 7 -to 0 exp_p_tri_io
+
+# ADC
+
+# Create axis_red_pitaya_adc
+cell labdpr:user:axis_rp_adc adc_0 {} {
+ aclk pll_0/clk_out1
+ adc_dat_a adc_dat_a_i
+ adc_dat_b adc_dat_b_i
+ adc_csn adc_csn_o
+}
+
+# Create axi_cfg_register
+cell labdpr:user:axi_cfg_register cfg_0 {
+ CFG_DATA_WIDTH 64
+ AXI_ADDR_WIDTH 32
+ AXI_DATA_WIDTH 32
+}
+
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config {
+ Master /ps_0/M_AXI_GP0
+ Clk Auto
+} [get_bd_intf_pins cfg_0/S_AXI]
+
+set_property RANGE 4K [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
+set_property OFFSET 0x40000000 [get_bd_addr_segs ps_0/Data/SEG_cfg_0_reg0]
+
+# Create port_slicer
+cell labdpr:user:port_slicer slice_1 {
+ DIN_WIDTH 64 DIN_FROM 0 DIN_TO 0
+} {
+ din cfg_0/cfg_data
+}
+
+# Create port_slicer
+cell labdpr:user:port_slicer slice_2 {
+ DIN_WIDTH 64 DIN_FROM 1 DIN_TO 1
+} {
+ din cfg_0/cfg_data
+}
+
+# Create port_slicer
+cell labdpr:user:port_slicer slice_3 {
+ DIN_WIDTH 64 DIN_FROM 2 DIN_TO 2
+} {
+ din cfg_0/cfg_data
+}
+
+# Create port_slicer
+cell labdpr:user:port_slicer slice_4 {
+ DIN_WIDTH 64 DIN_FROM 63 DIN_TO 32
+} {
+ din cfg_0/cfg_data
+}
+
+# Create util_vector_logic
+cell xilinx.com:ip:util_vector_logic not_0 {
+ C_SIZE 1
+ C_OPERATION not
+} {
+ Op1 slice_2/dout
+}
+
+# Create xlconcat
+cell xilinx.com:ip:xlconcat concat_0 {
+ NUM_PORTS 2
+ IN0_WIDTH 1
+ IN1_WIDTH 7
+} {
+ In0 not_0/Res
+ dout exp_p_tri_io
+}
+
+# Create axis_broadcaster
+cell xilinx.com:ip:axis_broadcaster bcast_0 {
+ S_TDATA_NUM_BYTES.VALUE_SRC USER
+ M_TDATA_NUM_BYTES.VALUE_SRC USER
+ S_TDATA_NUM_BYTES 4
+ M_TDATA_NUM_BYTES 2
+ M00_TDATA_REMAP {tdata[13:0],2'b00}
+ M01_TDATA_REMAP {tdata[29:16],2'b00}
+} {
+ S_AXIS adc_0/M_AXIS
+ aclk pll_0/clk_out1
+ aresetn rst_0/peripheral_aresetn
+}
+
+# Create cic_compiler
+cell xilinx.com:ip:cic_compiler cic_0 {
+ INPUT_DATA_WIDTH.VALUE_SRC USER
+ FILTER_TYPE Decimation
+ NUMBER_OF_STAGES 6
+ FIXED_OR_INITIAL_RATE 32
+ INPUT_SAMPLE_FREQUENCY 125
+ CLOCK_FREQUENCY 125
+ INPUT_DATA_WIDTH 16
+ QUANTIZATION Truncation
+ OUTPUT_DATA_WIDTH 16
+ USE_XTREME_DSP_SLICE true
+ HAS_ARESETN true
+} {
+ S_AXIS_DATA bcast_0/M00_AXIS
+ aclk pll_0/clk_out1
+ aresetn slice_1/dout
+}
+
+# Create cic_compiler
+cell xilinx.com:ip:cic_compiler cic_1 {
+ INPUT_DATA_WIDTH.VALUE_SRC USER
+ FILTER_TYPE Decimation
+ NUMBER_OF_STAGES 6
+ FIXED_OR_INITIAL_RATE 32
+ INPUT_SAMPLE_FREQUENCY 125
+ CLOCK_FREQUENCY 125
+ INPUT_DATA_WIDTH 16
+ QUANTIZATION Truncation
+ OUTPUT_DATA_WIDTH 16
+ USE_XTREME_DSP_SLICE true
+ HAS_ARESETN true
+} {
+ S_AXIS_DATA bcast_0/M01_AXIS
+ aclk pll_0/clk_out1
+ aresetn slice_1/dout
+}
+
+# Create axis_combiner
+cell xilinx.com:ip:axis_combiner comb_0 {
+ TDATA_NUM_BYTES.VALUE_SRC USER
+ TDATA_NUM_BYTES 2
+} {
+ S00_AXIS cic_0/M_AXIS_DATA
+ S01_AXIS cic_1/M_AXIS_DATA
+ aclk pll_0/clk_out1
+ aresetn rst_0/peripheral_aresetn
+}
+
+# Create fir_compiler
+cell xilinx.com:ip:fir_compiler fir_0 {
+ DATA_WIDTH.VALUE_SRC USER
+ DATA_WIDTH 16
+ COEFFICIENTVECTOR {-1.64753028794138e-08, -4.72969860103254e-08, -7.81983994864729e-10, 3.09179315378013e-08, 1.8600476137934e-08, 3.27300695910419e-08, -6.27121813377163e-09, -1.52196115352429e-07, -8.30377969926702e-08, 3.14361841397898e-07, 3.05515872274853e-07, -4.73906648324436e-07, -7.13188274738437e-07, 5.47004771774003e-07, 1.33401100809314e-06, -4.13867548024707e-07, -2.14949555259695e-06, -6.77977800948474e-08, 3.07398932714553e-06, 1.0366230107463e-06, -3.94245232963009e-06, -2.59076839821521e-06, 4.51317323767107e-06, 4.74563996488482e-06, -4.49064349142054e-06, -7.3947777960083e-06, 3.57041197419745e-06, 1.02846684426837e-05, -1.50308472093842e-06, -1.30146997163052e-05, -1.8311731233767e-06, 1.50710364353895e-05, 6.3515248701083e-06, -1.58982472678568e-05, -1.17267343142635e-05, 1.50041199296265e-05, 1.73635115814309e-05, -1.20890304109726e-05, -2.24560062957254e-05, 7.16700059796055e-06, 2.60907689345942e-05, -6.64193032293714e-07, -2.74163749798938e-05, -6.54632074532538e-06, 2.5852558776971e-05, 1.31966582845397e-05, -2.13079073598636e-05, -1.77801135294917e-05, 1.43611952054032e-05, 1.88093817512436e-05, -6.35698021047062e-06, -1.51543007857966e-05, -6.31269475321274e-07, 6.41236246473726e-06, 4.00235076480002e-06, 6.75384652715119e-06, -1.00102812372645e-06, -2.23907547607786e-05, -1.07614170164429e-05, 3.72128949266483e-05, 3.26888314865614e-05, -4.68343172264928e-05, -6.46247522446593e-05, 4.62331324663801e-05, 0.000104353987875991, -3.05204178369922e-05, -0.000147387572103254, -4.12376672483791e-06, 0.000187096070793206, 5.94492160104715e-05, -0.000215270553995213, -0.000134242574203586, 0.000223115373945588, 0.000223732063932204, -0.000202601585158347, -0.000319473722277179, 0.000148023831554525, 0.000409856470754451, -5.75319241913947e-05, -0.00048128691789378, -6.56435551088113e-05, 0.000520005389882914, 0.000212559310978688, -0.000514378040456993, -0.000368824791639381, 0.000457257636791032, 0.00051572189965271, -0.000348325111720936, -0.000632574861580132, 0.000195575644936742, 0.000699853643923955, -1.5816811333843e-05, -0.000702875004558909, -0.000166267212059945, 0.000635554670416145, 0.000320646045613507, -0.000503596369030625, -0.000416023690327203, 0.000326453158345306, 0.00042516016658693, -0.000137454215410763, -0.000330867755122004, -1.83577770104995e-05, 0.000131884375290827, 8.88732824246191e-05, 0.000152320700965935, -2.19145324792827e-05, -0.000478845867687744, -0.000226130995959082, 0.000781165284659716, 0.000680083599509367, -0.000973297239795462, -0.00133684955123469, 0.000956951103249511, 0.00215724393391554, -0.000632647805407322, -0.00306094569410801, -8.63474252426424e-05, 0.00392560461099799, 0.00125840455441931, -0.00459097537930345, -0.00289777037472875, 0.00486843895178868, 0.00496041688761007, -0.00455566278421732, -0.0073332195556104, 0.00345548961533671, 0.00982788076765724, -0.0013975392826423, -0.0121803938743171, -0.00173944634676796, 0.0140556603140014, 0.00600554245501628, -0.0150585666700821, -0.0113645359721422, 0.0147416608531572, 0.0176785888467245, -0.0126130926725902, -0.0247012339350495, 0.00812796467212303, 0.0320712315374266, -0.000646259298618774, -0.0392988478933562, -0.0106852885932714, 0.0457163887873562, 0.0272344645510023, -0.0503010855018923, -0.0516879242105393, 0.0510032995068897, 0.0905252892059647, -0.0416077244968566, -0.163677972614864, -0.0107434888500177, 0.356350050991766, 0.554721342376512, 0.356350050991766, -0.0107434888500177, -0.163677972614864, -0.0416077244968565, 0.0905252892059646, 0.0510032995068897, -0.0516879242105392, -0.0503010855018923, 0.0272344645510023, 0.0457163887873562, -0.0106852885932714, -0.0392988478933562, -0.000646259298618766, 0.0320712315374266, 0.008127964672123, -0.0247012339350495, -0.0126130926725902, 0.0176785888467245, 0.0147416608531572, -0.0113645359721422, -0.0150585666700821, 0.00600554245501627, 0.0140556603140014, -0.00173944634676796, -0.0121803938743171, -0.0013975392826423, 0.00982788076765723, 0.00345548961533672, -0.0073332195556104, -0.00455566278421732, 0.00496041688761004, 0.00486843895178868, -0.00289777037472874, -0.00459097537930345, 0.00125840455441931, 0.003925604610998, -8.6347425242651e-05, -0.00306094569410801, -0.000632647805407327, 0.00215724393391554, 0.000956951103249513, -0.00133684955123469, -0.000973297239795458, 0.00068008359950937, 0.000781165284659718, -0.000226130995959085, -0.000478845867687734, -2.19145324792814e-05, 0.000152320700965923, 8.88732824246168e-05, 0.000131884375290828, -1.83577770104952e-05, -0.000330867755122008, -0.000137454215410769, 0.000425160166586931, 0.000326453158345309, -0.000416023690327193, -0.000503596369030629, 0.000320646045613497, 0.000635554670416148, -0.000166267212059939, -0.000702875004558908, -1.58168113338674e-05, 0.000699853643923955, 0.000195575644936758, -0.000632574861580132, -0.000348325111720941, 0.000515721899652708, 0.000457257636791035, -0.000368824791639379, -0.000514378040456997, 0.000212559310978687, 0.000520005389882915, -6.56435551088096e-05, -0.000481286917893776, -5.7531924191395e-05, 0.000409856470754451, 0.000148023831554525, -0.000319473722277176, -0.000202601585158348, 0.000223732063932204, 0.000223115373945587, -0.000134242574203588, -0.000215270553995212, 5.944921601047e-05, 0.000187096070793206, -4.12376672483805e-06, -0.000147387572103254, -3.05204178369924e-05, 0.000104353987875991, 4.62331324663777e-05, -6.46247522446589e-05, -4.68343172264921e-05, 3.26888314865612e-05, 3.72128949266458e-05, -1.07614170164428e-05, -2.23907547607785e-05, -1.0010281237264e-06, 6.7538465271515e-06, 4.00235076480007e-06, 6.41236246473652e-06, -6.31269475321259e-07, -1.5154300785797e-05, -6.35698021047036e-06, 1.88093817512439e-05, 1.43611952054029e-05, -1.77801135294911e-05, -2.13079073598635e-05, 1.31966582845395e-05, 2.58525587769708e-05, -6.54632074532428e-06, -2.74163749798938e-05, -6.64193032294061e-07, 2.60907689345942e-05, 7.16700059796085e-06, -2.24560062957254e-05, -1.20890304109726e-05, 1.7363511581431e-05, 1.50041199296266e-05, -1.17267343142635e-05, -1.58982472678571e-05, 6.3515248701082e-06, 1.50710364353894e-05, -1.83117312337678e-06, -1.30146997163053e-05, -1.50308472093845e-06, 1.02846684426836e-05, 3.57041197419745e-06, -7.39477779600816e-06, -4.49064349142055e-06, 4.74563996488478e-06, 4.51317323767109e-06, -2.59076839821518e-06, -3.94245232963005e-06, 1.03662301074629e-06, 3.07398932714552e-06, -6.77977800948646e-08, -2.14949555259695e-06, -4.13867548024735e-07, 1.33401100809314e-06, 5.47004771773993e-07, -7.13188274738437e-07, -4.73906648324394e-07, 3.05515872274853e-07, 3.14361841397861e-07, -8.30377969926656e-08, -1.5219611535243e-07, -6.27121813377245e-09, 3.27300695910341e-08, 1.86004761379317e-08, 3.0917931537805e-08, -7.81983994865244e-10, -4.72969860103212e-08, -1.64753028794135e-08}
+ COEFFICIENT_WIDTH 16
+ QUANTIZATION Quantize_Only
+ BESTPRECISION true
+ FILTER_TYPE Decimation
+ DECIMATION_RATE 2
+ NUMBER_PATHS 2
+ RATESPECIFICATION Input_Sample_Period
+ SAMPLEPERIOD 32
+ OUTPUT_ROUNDING_MODE Truncate_LSBs
+ OUTPUT_WIDTH 16
+ HAS_ARESETN true
+} {
+ S_AXIS_DATA comb_0/M_AXIS
+ aclk pll_0/clk_out1
+ aresetn slice_1/dout
+}
+
+# Create axis_packetizer
+cell labdpr:user:axis_packetizer pktzr_0 {
+ AXIS_TDATA_WIDTH 32
+ CNTR_WIDTH 32
+ CONTINUOUS FALSE
+} {
+ S_AXIS fir_0/M_AXIS_DATA
+ cfg_data slice_4/dout
+ aclk pll_0/clk_out1
+ aresetn slice_2/dout
+}
+
+# Create axis_dwidth_converter
+cell xilinx.com:ip:axis_dwidth_converter conv_0 {
+ S_TDATA_NUM_BYTES.VALUE_SRC USER
+ S_TDATA_NUM_BYTES 4
+ M_TDATA_NUM_BYTES 8
+} {
+ S_AXIS pktzr_0/M_AXIS
+ aclk pll_0/clk_out1
+ aresetn slice_3/dout
+}
+
+# Create xlconstant
+cell xilinx.com:ip:xlconstant const_1 {
+ CONST_WIDTH 32
+ CONST_VAL 503316480
+}
+
+# Create axis_ram_writer
+cell labdpr:user:axis_ram_writer writer_0 {
+ ADDR_WIDTH 22
+} {
+ S_AXIS conv_0/M_AXIS
+ M_AXI ps_0/S_AXI_HP0
+ cfg_data const_1/dout
+ aclk pll_0/clk_out1
+ aresetn slice_3/dout
+}
+
+assign_bd_address [get_bd_addr_segs ps_0/S_AXI_HP0/HP0_DDR_LOWOCM]
diff --git a/projects/adc_recorder_old/src/Makefile b/projects/adc_recorder_old/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..3949c777a22024657bcf96313056f149c2373b2f
--- /dev/null
+++ b/projects/adc_recorder_old/src/Makefile
@@ -0,0 +1,16 @@
+CC=gcc
+FLAGS=-Wall -O3
+ARCH=arm
+CROSS_COMPILE=arm-xilinx-linux-gnueabi-
+
+####
+PROG=adc_recorder
+EXTRA=
+
+all: $(PROG)
+
+$(PROG): $(PROG).c $(EXTRA)
+ $(CC) $(FLAGS) -o $(PROG) $(PROG).c $(EXTRA) -lm -lpthread
+
+clean:
+ rm -f $(PROG)
diff --git a/projects/adc_recorder_old/src/adc_recorder.c b/projects/adc_recorder_old/src/adc_recorder.c
new file mode 100644
index 0000000000000000000000000000000000000000..febaf6b14ee289a3ca507268ee427e58c9e34d95
--- /dev/null
+++ b/projects/adc_recorder_old/src/adc_recorder.c
@@ -0,0 +1,361 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+
+#include "zynq_io.h"
+
+int intc_fd, cfg_fd, sts_fd, xadc_fd, mem_fd;
+void *intc_ptr, *cfg_ptr, *sts_ptr, *xadc_ptr, *mem_ptr;
+int dev_size;
+
+void dev_write(void *dev_base, uint32_t offset, int32_t value)
+{
+ *((volatile unsigned *)(dev_base + offset)) = value;
+}
+
+uint32_t dev_read(void *dev_base, uint32_t offset)
+{
+ return *((volatile unsigned *)(dev_base + offset));
+}
+
+int32_t rd_reg_value(int n_dev, uint32_t reg_off)
+{
+ int32_t reg_val;
+ switch(n_dev)
+ {
+ case 0:
+ reg_val = dev_read(intc_ptr, reg_off);
+ break;
+ case 1:
+ reg_val = dev_read(cfg_ptr, reg_off);
+ break;
+ case 2:
+ reg_val = dev_read(sts_ptr, reg_off);
+ break;
+ case 3:
+ reg_val = dev_read(xadc_ptr, reg_off);
+ break;
+ default:
+ printf("Invalid option: %d\n", n_dev);
+ return -1;
+ }
+ printf("Complete. Received data 0x%08x\n", reg_val);
+ //printf("Complete. Received data %d\n", reg_val);
+
+ return reg_val;
+}
+
+int32_t wr_reg_value(int n_dev, uint32_t reg_off, int32_t reg_val)
+{
+ switch(n_dev)
+ {
+ case 0:
+ dev_write(intc_ptr, reg_off, reg_val);
+ break;
+ case 1:
+ dev_write(cfg_ptr, reg_off, reg_val);
+ break;
+ case 2:
+ dev_write(sts_ptr, reg_off, reg_val);
+ break;
+ case 3:
+ dev_write(xadc_ptr, reg_off, reg_val);
+ break;
+ default:
+ printf("Invalid option: %d\n", n_dev);
+ return -1;
+ }
+ printf("Complete. Data written: 0x%08x\n", reg_val);
+ //printf("Complete. Data written: %d\n", reg_val);
+
+ return 0;
+}
+
+static uint32_t get_memory_size(char *sysfs_path_file)
+{
+ FILE *size_fp;
+ uint32_t size;
+
+ // open the file that describes the memory range size that is based on
+ // the reg property of the node in the device tree
+ size_fp = fopen(sysfs_path_file, "r");
+
+ if (!size_fp) {
+ printf("unable to open the uio size file\n");
+ exit(-1);
+ }
+
+ // get the size which is an ASCII string such as 0xXXXXXXXX and then be
+ // stop using the file
+ if(fscanf(size_fp, "0x%08X", &size) == EOF){
+ printf("unable to get the size of the uio size file\n");
+ exit(-1);
+ }
+ fclose(size_fp);
+
+ return size;
+}
+
+int intc_init(void)
+{
+ char *uiod = "/dev/uio0";
+
+ //printf("Initializing INTC device...\n");
+
+ // open the UIO device file to allow access to the device in user space
+ intc_fd = open(uiod, O_RDWR);
+ if (intc_fd < 1) {
+ printf("intc_init: Invalid UIO device file:%s.\n", uiod);
+ return -1;
+ }
+
+ dev_size = get_memory_size("/sys/class/uio/uio0/maps/map0/size");
+
+ // mmap the INTC device into user space
+ intc_ptr = mmap(NULL, dev_size, PROT_READ|PROT_WRITE, MAP_SHARED, intc_fd, 0);
+ if (intc_ptr == MAP_FAILED) {
+ printf("intc_init: mmap call failure.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+int cfg_init(void)
+{
+ char *uiod = "/dev/uio0";
+
+ printf("Initializing CFG device...\n");
+
+ // open the UIO device file to allow access to the device in user space
+ cfg_fd = open(uiod, O_RDWR);
+ if (cfg_fd < 1) {
+ printf("cfg_init: Invalid UIO device file:%s.\n", uiod);
+ return -1;
+ }
+
+ dev_size = get_memory_size("/sys/class/uio/uio1/maps/map0/size");
+
+ // mmap the cfgC device into user space
+ cfg_ptr = mmap(NULL, dev_size, PROT_READ|PROT_WRITE, MAP_SHARED, cfg_fd, 0);
+ if (cfg_ptr == MAP_FAILED) {
+ printf("cfg_init: mmap call failure.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+int sts_init(void)
+{
+ char *uiod = "/dev/uio2";
+
+ //printf("Initializing STS device...\n");
+
+ // open the UIO device file to allow access to the device in user space
+ sts_fd = open(uiod, O_RDWR);
+ if (sts_fd < 1) {
+ printf("sts_init: Invalid UIO device file:%s.\n", uiod);
+ return -1;
+ }
+
+ dev_size = get_memory_size("/sys/class/uio/uio2/maps/map0/size");
+
+ // mmap the STS device into user space
+ sts_ptr = mmap(NULL, dev_size, PROT_READ|PROT_WRITE, MAP_SHARED, sts_fd, 0);
+ if (sts_ptr == MAP_FAILED) {
+ printf("sts_init: mmap call failure.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+int mem_init(void)
+{
+ char *mem_name = "/dev/mem";
+
+ //printf("Initializing mem device...\n");
+
+ // open the UIO device file to allow access to the device in user space
+ mem_fd = open(mem_name, O_RDWR);
+ if (mem_fd < 1) {
+ printf("mem_init: Invalid device file:%s.\n", mem_name);
+ return -1;
+ }
+
+ //dev_size = 2048*sysconf(_SC_PAGESIZE);
+ dev_size = 1024*sysconf(_SC_PAGESIZE);
+
+ // mmap the mem device into user space
+ mem_ptr = mmap(NULL, dev_size, PROT_READ|PROT_WRITE, MAP_SHARED, mem_fd, 0x1E000000);
+ if (mem_ptr == MAP_FAILED) {
+ printf("mem_init: mmap call failure.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+//System initialization
+int init_system(void)
+{
+ uint32_t reg_val;
+
+ // set trigger_lvl_1
+ dev_write(cfg_ptr,CFG_TRLVL_1_OFFSET,8190);
+
+ // set trigger_lvl_2
+ dev_write(cfg_ptr,CFG_TRLVL_2_OFFSET,8190);
+
+ // set subtrigger_lvl_1
+ dev_write(cfg_ptr,CFG_STRLVL_1_OFFSET,8190);
+
+ // set subtrigger_lvl_2
+ dev_write(cfg_ptr,CFG_STRLVL_2_OFFSET,8190);
+
+ // set hv1 and hv2 to zero
+ dev_write(cfg_ptr,CFG_HV1_OFFSET,0);
+ dev_write(cfg_ptr,CFG_HV2_OFFSET,0);
+
+ // reset ramp generators
+ reg_val = dev_read(cfg_ptr, CFG_RESET_GRAL_OFFSET);
+ dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val & ~8);
+
+ // reset pps_gen, fifo and trigger modules
+ reg_val = dev_read(cfg_ptr, CFG_RESET_GRAL_OFFSET);
+ dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val & ~1);
+
+ /* reset data converter and writer */
+ reg_val = dev_read(cfg_ptr, CFG_RESET_GRAL_OFFSET);
+ dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val & ~4);
+
+ // enter reset mode for tlast_gen
+ reg_val = dev_read(cfg_ptr, CFG_RESET_GRAL_OFFSET);
+ dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val & ~2);
+
+ // set number of samples
+ dev_write(cfg_ptr,CFG_NSAMPLES_OFFSET, 1024 * 1024);
+
+ // set default value for trigger scalers a and b
+ dev_write(cfg_ptr,CFG_TR_SCAL_A_OFFSET, 1);
+ dev_write(cfg_ptr,CFG_TR_SCAL_B_OFFSET, 1);
+
+ // enter normal mode for tlast_gen
+ /* reg_val = dev_read(cfg_ptr, CFG_RESET_GRAL_OFFSET);
+ //printf("reg_val : 0x%08x\n",reg_val);
+ dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val | 2);
+ //printf("written reg_val tlast : 0x%08x\n",reg_val | 2);
+ // enter normal mode for pps_gen, fifo and trigger modules
+ reg_val = dev_read(cfg_ptr, CFG_RESET_GRAL_OFFSET);
+ //printf("reg_val : 0x%08x\n",reg_val);
+ dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val | 1);
+ //printf("written reg_val pps_gen, fifo : 0x%08x\n",reg_val | 1);
+ */
+ // enable false GPS
+ reg_val = dev_read(cfg_ptr, CFG_RESET_GRAL_OFFSET);
+ //printf("reg_val : 0x%08x\n",reg_val);
+ dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val | FGPS_EN_MASK);
+ //printf("written reg_val : 0x%08x\n",reg_val | 16);
+ // disable
+ //dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val & ~16);
+ //dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val & ~FGPS_EN_MASK);
+ //printf("written reg_val : 0x%08x\n",reg_val & ~16);
+
+ /* // enter normal mode for data converter and writer
+ reg_val = dev_read(cfg_ptr, CFG_RESET_GRAL_OFFSET);
+ dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val | 4);
+ //printf("written reg_val : 0x%08hx\n",reg_val | 4);
+ */
+ // enter normal mode for ramp generators
+ reg_val = dev_read(cfg_ptr, CFG_RESET_GRAL_OFFSET);
+ dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val | 8);
+ // enter in MASTER mode (default)
+ reg_val = dev_read(cfg_ptr, CFG_RESET_GRAL_OFFSET);
+ dev_write(cfg_ptr,CFG_RESET_GRAL_OFFSET, reg_val | 0x20);
+
+ return 0;
+}
+
+int main(int argc, char *argv[])
+{
+ //int fd;
+ //unsigned int size;
+ uint32_t i,val=0;
+ uint32_t wo;
+ int16_t ch[2];
+
+ printf("CFG UIO test\n");
+
+ //initialize devices. TODO: add error checking
+ mem_init();
+ //intc_init();
+ cfg_init();
+ //sts_init();
+ //xadc_init();
+
+ // reset writer
+ //*((uint32_t *)(cfg + 0)) &= ~4;
+ printf("Reseting writer...\n");
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &= ~4);
+ //*((uint32_t *)(cfg + 0)) |= 4;
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |= 4);
+ printf("Reseting writer %d ...\n",val);
+ printf("Reseting fifo and filters...\n");
+ // reset fifo and filters
+ //*((uint32_t *)(cfg + 0)) &= ~1;
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~1);
+ //*((uint32_t *)(cfg + 0)) |= 1;
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=1);
+ printf("Reseting fifo and filters %d ...\n",val);
+
+ // wait 1 second
+ sleep(1);
+
+ printf("Reseting packetizer...\n");
+ // enter reset mode for packetizer
+ //*((uint32_t *)(cfg + 0)) &= ~2;
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val &=~2);
+
+ // set number of samples
+ //*((uint32_t *)(cfg + 4)) = 1024 * 1024 - 1;
+ wr_reg_value(1, CFG_NSAMPLES_OFFSET, 1024 * 1024 - 1);
+
+ // enter normal mode
+ //*((uint32_t *)(cfg + 0)) |= 2;
+ val=rd_reg_value(1, CFG_RESET_GRAL_OFFSET);
+ wr_reg_value(1, CFG_RESET_GRAL_OFFSET, val |=2);
+ printf("Reseting packetizer %d ...\n",val);
+
+ // wait 1 second
+ sleep(1);
+
+ // print IN1 and IN2 samples
+ for(i = 0; i < 1024 * 1024; ++i){
+ ch[0] = *((int16_t *)(mem_ptr + 4*i + 0));
+ ch[1] = *((int16_t *)(mem_ptr + 4*i + 2));
+ wo = *((uint32_t *)(mem_ptr + i));
+ printf("%5d %5d %10d\n", ch[0], ch[1], wo);
+ }
+
+ // unmap and close the devices
+ //munmap(intc_ptr, sysconf(_SC_PAGESIZE));
+ munmap(cfg_ptr, sysconf(_SC_PAGESIZE));
+ //munmap(sts_ptr, sysconf(_SC_PAGESIZE));
+ //munmap(xadc_ptr, sysconf(_SC_PAGESIZE));
+ munmap(mem_ptr, sysconf(_SC_PAGESIZE));
+
+ //close(intc_fd);
+ close(cfg_fd);
+ //close(sts_fd);
+ //close(xadc_fd);
+
+ return 0;
+
+}
diff --git a/projects/adc_recorder_old/src/zynq_io.h b/projects/adc_recorder_old/src/zynq_io.h
new file mode 100644
index 0000000000000000000000000000000000000000..812e09686d7d600ef860f2fd73a67161466e1fb4
--- /dev/null
+++ b/projects/adc_recorder_old/src/zynq_io.h
@@ -0,0 +1,149 @@
+#ifndef _ZYNQ_IO_H_
+#define _ZYNQ_IO_H_
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+#include <unistd.h>
+
+#define INTC_BASEADDR 0x40000000
+#define INTC_HIGHADDR 0x40000FFF
+
+#define CFG_BASEADDR 0x40000000
+#define CFG_HIGHADDR 0x40000FFF
+
+#define STS_BASEADDR 0x40002000
+#define STS_HIGHADDR 0x40002FFF
+
+#define XADC_BASEADDR 0x40003000
+#define XADC_HIGHADDR 0x40003FFF
+
+#define XIL_AXI_INTC_ISR_OFFSET 0x0
+#define XIL_AXI_INTC_IPR_OFFSET 0x4
+#define XIL_AXI_INTC_IER_OFFSET 0x8
+#define XIL_AXI_INTC_IAR_OFFSET 0xC
+#define XIL_AXI_INTC_SIE_OFFSET 0x10
+#define XIL_AXI_INTC_CIE_OFFSET 0x14
+#define XIL_AXI_INTC_IVR_OFFSET 0x18
+#define XIL_AXI_INTC_MER_OFFSET 0x1C
+#define XIL_AXI_INTC_IMR_OFFSET 0x20
+#define XIL_AXI_INTC_ILR_OFFSET 0x24
+#define XIL_AXI_INTC_IVAR_OFFSET 0x100
+
+#define XIL_AXI_INTC_MER_ME_MASK 0x00000001
+#define XIL_AXI_INTC_MER_HIE_MASK 0x00000002
+
+//CFG
+#define CFG_RESET_GRAL_OFFSET 0x0
+#define CFG_NSAMPLES_OFFSET 0x4
+#define CFG_TRLVL_1_OFFSET 0x8
+#define CFG_TRLVL_2_OFFSET 0xC
+#define CFG_STRLVL_1_OFFSET 0x10
+#define CFG_STRLVL_2_OFFSET 0x14
+#define CFG_TEMPERATURE_OFFSET 0x18
+#define CFG_PRESSURE_OFFSET 0x1C
+#define CFG_TIME_OFFSET 0x20
+#define CFG_DATE_OFFSET 0x24
+#define CFG_LATITUDE_OFFSET 0x28
+#define CFG_LONGITUDE_OFFSET 0x2C
+#define CFG_ALTITUDE_OFFSET 0x30
+#define CFG_SATELLITE_OFFSET 0x34
+#define CFG_TR_SCAL_A_OFFSET 0x38
+#define CFG_TR_SCAL_B_OFFSET 0x3C
+#define CFG_HV1_OFFSET 0x4C //DAC_PWM3
+#define CFG_HV2_OFFSET 0x48 //DAC_PWM2
+#define CFG_HV3_OFFSET 0x40 //DAC_PWM0
+#define CFG_HV4_OFFSET 0x44 //DAC_PWM1
+
+//CFG Slow DAC
+#define CFG_DAC_PWM0_OFFSET 0x40
+#define CFG_DAC_PWM1_OFFSET 0x44
+#define CFG_DAC_PWM2_OFFSET 0x48
+#define CFG_DAC_PWM3_OFFSET 0x4C
+
+#define ENBL_ALL_MASK 0xFFFFFFFF
+#define RST_ALL_MASK 0x00000000
+#define RST_PPS_TRG_FIFO_MASK 0x00000001
+#define RST_TLAST_GEN_MASK 0x00000002
+#define RST_WRITER_MASK 0x00000004
+#define RST_AO_MASK 0x00000008
+#define FGPS_EN_MASK 0x00000010
+
+//STS
+#define STS_STATUS_OFFSET 0x0
+
+//XADC
+//See page 17 of PG091
+#define XADC_SRR_OFFSET 0x00 //Software reset register
+#define XADC_SR_OFFSET 0x04 //Status Register
+#define XADC_AOSR_OFFSET 0x08 //Alarm Out Status Register
+#define XADC_CONVSTR_OFFSET 0x0C //CONVST Register
+#define XADC_SYSMONRR_OFFSET 0x10 //XADC Reset Register
+#define XADC_GIER_OFFSET 0x5C //Global Interrupt Enable Register
+#define XADC_IPISR_OFFSET 0x60 //IP Interrupt Status Register
+#define XADC_IPIER_OFFSET 0x68 //IP Interrupt Enable Register
+#define XADC_TEMPERATURE_OFFSET 0x200 //Temperature
+#define XADC_VCCINT_OFFSET 0x204 //VCCINT
+#define XADC_VCCAUX_OFFSET 0x208 //VCCAUX
+#define XADC_VPVN_OFFSET 0x20C //VP/VN
+#define XADC_VREFP_OFFSET 0x210 //VREFP
+#define XADC_VREFN_OFFSET 0x214 //VREFN
+#define XADC_VBRAM_OFFSET 0x218 //VBRAM
+#define XADC_UNDEF_OFFSET 0x21C //Undefined
+#define XADC_SPLYOFF_OFFSET 0x220 //Supply Offset
+#define XADC_ADCOFF_OFFSET 0x224 //ADC Offset
+#define XADC_GAIN_ERR_OFFSET 0x228 //Gain Error
+#define XADC_ZDC_SPLY_OFFSET 0x234 //Zynq-7000 Device Core Supply
+#define XADC_ZDC_AUX_SPLY_OFFSET 0x238 //Zynq-7000 Device Core Aux Supply
+#define XADC_ZDC_MEM_SPLY_OFFSET 0x23C //Zynq-7000 Device Core Memory Supply
+#define XADC_VAUX_PN_0_OFFSET 0x240 //VAUXP[0]/VAUXN[0]
+#define XADC_VAUX_PN_1_OFFSET 0x244 //VAUXP[1]/VAUXN[1]
+#define XADC_VAUX_PN_2_OFFSET 0x248 //VAUXP[2]/VAUXN[2]
+#define XADC_VAUX_PN_3_OFFSET 0x24C //VAUXP[3]/VAUXN[3]
+#define XADC_VAUX_PN_4_OFFSET 0x250 //VAUXP[4]/VAUXN[4]
+#define XADC_VAUX_PN_5_OFFSET 0x254 //VAUXP[5]/VAUXN[5]
+#define XADC_VAUX_PN_6_OFFSET 0x258 //VAUXP[6]/VAUXN[6]
+#define XADC_VAUX_PN_7_OFFSET 0x25C //VAUXP[7]/VAUXN[7]
+#define XADC_VAUX_PN_8_OFFSET 0x260 //VAUXP[8]/VAUXN[8]
+#define XADC_VAUX_PN_9_OFFSET 0x264 //VAUXP[9]/VAUXN[9]
+#define XADC_VAUX_PN_10_OFFSET 0x268 //VAUXP[10]/VAUXN[10]
+#define XADC_VAUX_PN_11_OFFSET 0x26C //VAUXP[11]/VAUXN[11]
+#define XADC_VAUX_PN_12_OFFSET 0x270 //VAUXP[12]/VAUXN[12]
+#define XADC_VAUX_PN_13_OFFSET 0x274 //VAUXP[13]/VAUXN[13]
+#define XADC_VAUX_PN_14_OFFSET 0x278 //VAUXP[14]/VAUXN[14]
+#define XADC_VAUX_PN_15_OFFSET 0x27C //VAUXP[15]/VAUXN[15]
+
+#define XADC_AI0_OFFSET XADC_VAUX_PN_8_OFFSET
+#define XADC_AI1_OFFSET XADC_VAUX_PN_0_OFFSET
+#define XADC_AI2_OFFSET XADC_VAUX_PN_1_OFFSET
+#define XADC_AI3_OFFSET XADC_VAUX_PN_9_OFFSET
+
+#define XADC_CONV_VAL 0.00171191993362 //(A_ip/2^12)*(34.99/4.99)
+#define XADC_RDIV_VAL 1.883236177 //voltage divisor in board (15k+16.983k)/16.983k = 1.88
+#define XADC_BASE_HVDIV 0.00294088 //voltage divisor in HV base board (100k/31.3Meg) = 3.194888179. The value I put here is the measured one.
+
+extern int intc_fd, cfg_fd, sts_fd, xadc_fd, mem_fd;
+extern void *intc_ptr, *cfg_ptr, *sts_ptr, *xadc_ptr, *mem_ptr;
+
+void dev_write(void *dev_base, uint32_t offset, int32_t value);
+uint32_t dev_read(void *dev_base, uint32_t offset);
+//int dev_init(int n_dev);
+int32_t rd_reg_value(int n_dev, uint32_t reg_off);
+int32_t wr_reg_value(int n_dev, uint32_t reg_off, int32_t reg_val);
+int32_t rd_cfg_status(void);
+int intc_init(void);
+int cfg_init(void);
+int sts_init(void);
+int xadc_init(void);
+int mem_init(void);
+float get_voltage(uint32_t offset);
+void set_voltage(uint32_t offset, int32_t value);
+float get_temp_AD592(uint32_t offset);
+int init_system(void);
+int enable_interrupt(void);
+int disable_interrupt(void);
+
+#endif
+