diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000000000000000000000000000000000000..ad5aa25c4c6130a4233814c024830d556532a1d6
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,13 @@
+The LAGO ECOSYSTEM
+Copyright (C) 2018-Today, The LAGO Project, [lagoproject.org](http://lagoproject.org)
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..c42f914da9a6094611117691aa49ab7f618e6401
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,204 @@
+# 'make' builds everything
+# 'make clean' deletes everything except source files and Makefile
+#
+# You need to set NAME, PART and PROC for your project.
+# NAME is the base name for most of the generated files.
+
+# solves problem with awk while building linux kernel
+# solution taken from http://www.googoolia.com/wp/2015/04/21/awk-symbol-lookup-error-awk-undefined-symbol-mpfr_z_sub/
+LD_LIBRARY_PATH =
+
+NAME = led_blinker
+PART = xc7z010clg400-1
+PROC = ps7_cortexa9_0
+
+CORES = axi_axis_reader_v1_0 \
+				axi_axis_writer_v1_0 \
+				axi_bram_reader_v1_0 \
+				axi_cfg_register_v1_0 \
+				axi_sts_register_v1_0 \
+				axi_time_trig_gen_v1_0 \
+				axis_avgr16bits_v1_0 \
+				axis_avgr32bits_v1_0 \
+				axis_avgr_v1_0 \
+				axis_bram_reader_v1_0 \
+				axis_bram_writer_v1_0 \
+				axis_constant_v1_0 \
+				axis_counter_v1_0 \
+				axis_dc_removal_v1_0 \
+				axis_decimator_v1_0 \
+				axis_fifo_v1_0 \
+				axis_generator_v1_0 \
+				axis_gpio_reader_i_v1_0 \
+				axis_gpio_reader_v1_0 \
+				axis_histogram_v1_0 \
+				axis_histogram_v1_1 \
+				axis_interpolator_v1_0 \
+				axis_lago_trigger_v1_0 \
+				axis_lago_trigger_v1_1 \
+				axis_lago_trigger_v1_2 \
+				axis_lago_trigger_v1_3 \
+				axis_lfsr_v1_0 \
+				axis_lpf_v1_0 \
+				axis_oscilloscope_v1_0 \
+				axis_packetizer_v1_0 \
+				axis_phase_generator_v1_0 \
+				axis_ram_writer_v1_0 \
+				axis_rp_adc_v1_0 \
+				axis_rp_adc_v3_0 \
+				axis_rp_dac_v1_0 \
+				axis_rp_dac_v2_0 \
+				axis_tlast_gen_v1_0 \
+				axis_trigger_v1_0 \
+				axis_validator_v1_0 \
+				axis_variable_v1_0 \
+				axis_zero_crossing_det_v1_0 \
+				axis_zeroer_v1_0 \
+				bram_counter_v1_0 \
+				bram_selector_v1_0 \
+				dc_removal_v1_0 \
+				dna_reader_v1_0 \
+				int_counter_v1_0 \
+				port_selector_v1_0 \
+				port_slicer_v1_0 \
+				pps_gen_v1_0 \
+				pps_gen_v1_1 \
+				pwm_gen_v1_0 \
+				ramp_gen_v1_0 \
+				selector_v1_0 \
+				time_trig_gen_v1_0 
+
+VIVADO = vivado -nolog -nojournal -mode batch
+XSCT = xsct
+RM = rm -rf
+
+UBOOT_TAG = 2021.04
+LINUX_TAG = 5.10
+DTREE_TAG = xilinx-v2020.2
+
+UBOOT_DIR = tmp/u-boot-$(UBOOT_TAG)
+LINUX_DIR = tmp/linux-$(LINUX_TAG)
+DTREE_DIR = tmp/device-tree-xlnx-$(DTREE_TAG)
+
+UBOOT_TAR = tmp/u-boot-$(UBOOT_TAG).tar.bz2
+LINUX_TAR = tmp/linux-$(LINUX_TAG).tar.xz
+DTREE_TAR = tmp/device-tree-xlnx-$(DTREE_TAG).tar.gz
+
+UBOOT_URL = https://ftp.denx.de/pub/u-boot/u-boot-$(UBOOT_TAG).tar.bz2
+LINUX_URL = https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-$(LINUX_TAG).107.tar.xz
+DTREE_URL = https://github.com/Xilinx/device-tree-xlnx/archive/$(DTREE_TAG).tar.gz
+
+RTL8188_TAR = tmp/rtl8188eu-v5.2.2.4.tar.gz
+RTL8188_URL = https://github.com/lwfinger/rtl8188eu/archive/v5.2.2.4.tar.gz
+
+RTL8192_TAR = tmp/rtl8192cu-fixes-master.tar.gz
+RTL8192_URL = https://github.com/pvaret/rtl8192cu-fixes/archive/master.tar.gz
+
+.PRECIOUS: tmp/cores/% tmp/%.xpr tmp/%.xsa tmp/%.bit tmp/%.fsbl/executable.elf tmp/%.tree/system-top.dts
+
+all: tmp/$(NAME).bit boot.bin uImage devicetree.dtb
+
+cores: $(addprefix tmp/cores/, $(CORES))
+
+xpr: tmp/$(NAME).xpr
+
+bit: tmp/$(NAME).bit
+
+$(UBOOT_TAR):
+	mkdir -p $(@D)
+	curl -L $(UBOOT_URL) -o $@
+
+$(LINUX_TAR):
+	mkdir -p $(@D)
+	curl -L $(LINUX_URL) -o $@
+
+$(DTREE_TAR):
+	mkdir -p $(@D)
+	curl -L $(DTREE_URL) -o $@
+
+$(RTL8188_TAR):
+	mkdir -p $(@D)
+	curl -L $(RTL8188_URL) -o $@
+
+$(RTL8192_TAR):
+	mkdir -p $(@D)
+	curl -L $(RTL8192_URL) -o $@
+
+$(UBOOT_DIR): $(UBOOT_TAR)
+	mkdir -p $@
+	tar -jxf $< --strip-components=1 --directory=$@
+	patch -d tmp -p 0 < patches/u-boot-$(UBOOT_TAG).patch
+	cp patches/zynq_red_pitaya_defconfig $@/configs
+	cp patches/zynq-red-pitaya.dts $@/arch/arm/dts
+
+$(LINUX_DIR): $(LINUX_TAR) $(RTL8188_TAR) $(RTL8192_TAR)
+	mkdir -p $@
+	tar -Jxf $< --strip-components=1 --directory=$@
+	mkdir -p $@/drivers/net/wireless/realtek/rtl8188eu
+	mkdir -p $@/drivers/net/wireless/realtek/rtl8192cu
+	tar -zxf $(RTL8188_TAR) --strip-components=1 --directory=$@/drivers/net/wireless/realtek/rtl8188eu
+	tar -zxf $(RTL8192_TAR) --strip-components=1 --directory=$@/drivers/net/wireless/realtek/rtl8192cu
+	patch -d tmp -p 0 < patches/linux-$(LINUX_TAG).patch
+	cp patches/zynq_ocm.c $@/arch/arm/mach-zynq
+	cp patches/cma.c $@/drivers/char
+	cp patches/xilinx_devcfg.c $@/drivers/char
+	cp patches/xilinx_zynq_defconfig $@/arch/arm/configs
+
+$(DTREE_DIR): $(DTREE_TAR)
+	mkdir -p $@
+	tar -zxf $< --strip-components=1 --directory=$@
+
+uImage: $(LINUX_DIR)
+	make -C $< mrproper
+	make -C $< ARCH=arm xilinx_zynq_defconfig
+	make -C $< ARCH=arm -j $(shell nproc 2> /dev/null || echo 1) \
+	  CROSS_COMPILE=arm-linux-gnueabihf- UIMAGE_LOADADDR=0x8000 \
+	  uImage modules
+	cp $</arch/arm/boot/uImage $@
+
+$(UBOOT_DIR)/u-boot.bin: $(UBOOT_DIR)
+	mkdir -p $(@D)
+	make -C $< mrproper
+	make -C $< ARCH=arm zynq_red_pitaya_defconfig
+	make -C $< ARCH=arm -j $(shell nproc 2> /dev/null || echo 1) \
+	  CROSS_COMPILE=arm-linux-gnueabihf- all
+
+boot.bin: tmp/$(NAME).fsbl/executable.elf $(UBOOT_DIR)/u-boot.bin
+	echo "img:{[bootloader] tmp/$(NAME).fsbl/executable.elf [load=0x4000000,startup=0x4000000] $(UBOOT_DIR)/u-boot.bin}" > tmp/boot.bif
+	bootgen -image tmp/boot.bif -w -o i $@
+
+devicetree.dtb: uImage tmp/$(NAME).tree/system-top.dts
+	$(LINUX_DIR)/scripts/dtc/dtc -I dts -O dtb -o devicetree.dtb \
+	  -i tmp/$(NAME).tree tmp/$(NAME).tree/system-top.dts
+
+tmp/cores/%: cores/%/core_config.tcl cores/%/*.vhd
+	mkdir -p $(@D)
+	$(VIVADO) -source scripts/core.tcl -tclargs $* $(PART)
+
+tmp/%.xpr: projects/% $(addprefix tmp/cores/, $(CORES))
+	mkdir -p $(@D)
+	$(VIVADO) -source scripts/project.tcl -tclargs $* $(PART)
+
+tmp/%.xsa: tmp/%.xpr
+	mkdir -p $(@D)
+	$(VIVADO) -source scripts/hwdef.tcl -tclargs $*
+
+tmp/%.bit: tmp/%.xpr
+	mkdir -p $(@D)
+	$(VIVADO) -source scripts/bitstream.tcl -tclargs $*
+
+tmp/%.fsbl/executable.elf: tmp/%.xsa
+	mkdir -p $(@D)
+	$(XSCT) scripts/fsbl.tcl $* $(PROC)
+
+tmp/%.tree/system-top.dts: tmp/%.xsa $(DTREE_DIR)
+	mkdir -p $(@D)
+	$(XSCT) scripts/devicetree.tcl $* $(PROC) $(DTREE_DIR)
+	sed -i 's|#include|/include/|' $@
+	patch -d $(@D) < patches/devicetree.patch
+
+clean:
+	$(RM) uImage boot.bin devicetree.dtb tmp
+	$(RM) .Xil usage_statistics_webtalk.html usage_statistics_webtalk.xml
+	$(RM) vivado*.jou vivado*.log
+	$(RM) webtalk*.jou webtalk*.log
diff --git a/TODO.md b/TODO.md
new file mode 100644
index 0000000000000000000000000000000000000000..c0f38923ed15c9400f1dc6bc50eccf353717ac69
--- /dev/null
+++ b/TODO.md
@@ -0,0 +1,51 @@
+FPGA:
+- replace undocumented system bus with AXI4 Lite
+- move CPU accessible registers out from processing modules
+- separate the code into smaller modules connected over AXI4-Stream
+- rethink generator and osciloscope SW interface sequences
+- sestructure registers into a hierarchy
+- generalize trigger modes
+- write configurable PLL
+- write streaming benches
+- Scope:
+  - use DMA from Xilinx
+  - continuous mode
+  - trigger mode
+- add configurable PLL
+
+Linux:
+- upgrade to 3.19, there are Ethernet and USB driver issues
+- write IIO drivers
+- rethink user management and security
+
+Bazaar:
+- review the Nginx current patch, try to remove it and instead update the config file
+- update Nginx to newer version
+- update Buildroot to newer version
+- use API to get Zynq DNA (there are 2 instances)
+
+API:
+- move type definitins (structures, constants) to header files
+- remove middle API layer
+- avoid using read modify write access to registers
+
+Applications:
+- remove library sources from GIT, use sources from Buildroot instead
+- replace kiss FFT with NE10 library
+- replace libjpeg with turbo-jpeg from Buildroot
+
+SCPI:
+- migrate to latest upstream
+- push our patches upstream
+
+
+TODO
+
+* Fix bugs.
+* Decrease the amount of duplicated code and move common components
+  to shared.
+* Bring OS & ecosystem sources together as they compose one package.
+* Comment the code extensively in Doxygen style. Provide Doxygen
+  documentation.
+* Simplify Test/monitor.
+
diff --git a/cfg/clocks.xdc b/cfg/clocks.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..d2cfe3fa18e4254f16df57408a4b52d741536646
--- /dev/null
+++ b/cfg/clocks.xdc
@@ -0,0 +1,2 @@
+set_input_delay -max 1.000 -clock adc_clk_p_i [get_ports adc_dat_a_i[*]]
+set_input_delay -max 1.000 -clock adc_clk_p_i [get_ports adc_dat_b_i[*]]
diff --git a/cfg/ports.tcl b/cfg/ports.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9a7319b7deecba98b061108ee491d363e2912a1b
--- /dev/null
+++ b/cfg/ports.tcl
@@ -0,0 +1,43 @@
+
+### ADC
+
+create_bd_port -dir I -from 15 -to 0 adc_dat_a_i
+create_bd_port -dir I -from 15 -to 0 adc_dat_b_i
+
+create_bd_port -dir I adc_clk_p_i
+create_bd_port -dir I adc_clk_n_i
+
+create_bd_port -dir O adc_enc_p_o
+create_bd_port -dir O adc_enc_n_o
+
+create_bd_port -dir O adc_csn_o
+
+### DAC
+
+create_bd_port -dir O -from 13 -to 0 dac_dat_o
+
+create_bd_port -dir O dac_clk_o
+create_bd_port -dir O dac_rst_o
+create_bd_port -dir O dac_sel_o
+create_bd_port -dir O dac_wrt_o
+
+### PWM
+
+create_bd_port -dir O -from 3 -to 0 dac_pwm_o
+
+### XADC
+
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux1
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux9
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8
+
+### Expansion connector
+
+create_bd_port -dir IO -from 7 -to 0 exp_p_tri_io
+create_bd_port -dir IO -from 7 -to 0 exp_n_tri_io
+
+### LED
+
+create_bd_port -dir O -from 7 -to 0 led_o
diff --git a/cfg/ports.xdc b/cfg/ports.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..f0703c590182c7be868b4345f6b68c9497b10c91
--- /dev/null
+++ b/cfg/ports.xdc
@@ -0,0 +1,208 @@
+
+# set_property CFGBVS VCCO [current_design]
+# set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+### ADC
+
+# data
+
+set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_a_i[*]}]
+set_property IOB TRUE [get_ports {adc_dat_a_i[*]}]
+
+set_property PACKAGE_PIN V17 [get_ports {adc_dat_a_i[0]}]
+set_property PACKAGE_PIN U17 [get_ports {adc_dat_a_i[1]}]
+set_property PACKAGE_PIN Y17 [get_ports {adc_dat_a_i[2]}]
+set_property PACKAGE_PIN W16 [get_ports {adc_dat_a_i[3]}]
+set_property PACKAGE_PIN Y16 [get_ports {adc_dat_a_i[4]}]
+set_property PACKAGE_PIN W15 [get_ports {adc_dat_a_i[5]}]
+set_property PACKAGE_PIN W14 [get_ports {adc_dat_a_i[6]}]
+set_property PACKAGE_PIN Y14 [get_ports {adc_dat_a_i[7]}]
+set_property PACKAGE_PIN W13 [get_ports {adc_dat_a_i[8]}]
+set_property PACKAGE_PIN V12 [get_ports {adc_dat_a_i[9]}]
+set_property PACKAGE_PIN V13 [get_ports {adc_dat_a_i[10]}]
+set_property PACKAGE_PIN T14 [get_ports {adc_dat_a_i[11]}]
+set_property PACKAGE_PIN T15 [get_ports {adc_dat_a_i[12]}]
+set_property PACKAGE_PIN V15 [get_ports {adc_dat_a_i[13]}]
+set_property PACKAGE_PIN T16 [get_ports {adc_dat_a_i[14]}]
+set_property PACKAGE_PIN V16 [get_ports {adc_dat_a_i[15]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {adc_dat_b_i[*]}]
+set_property IOB TRUE [get_ports {adc_dat_b_i[*]}]
+
+set_property PACKAGE_PIN T17 [get_ports {adc_dat_b_i[0]}]
+set_property PACKAGE_PIN R16 [get_ports {adc_dat_b_i[1]}]
+set_property PACKAGE_PIN R18 [get_ports {adc_dat_b_i[2]}]
+set_property PACKAGE_PIN P16 [get_ports {adc_dat_b_i[3]}]
+set_property PACKAGE_PIN P18 [get_ports {adc_dat_b_i[4]}]
+set_property PACKAGE_PIN N17 [get_ports {adc_dat_b_i[5]}]
+set_property PACKAGE_PIN R19 [get_ports {adc_dat_b_i[6]}]
+set_property PACKAGE_PIN T20 [get_ports {adc_dat_b_i[7]}]
+set_property PACKAGE_PIN T19 [get_ports {adc_dat_b_i[8]}]
+set_property PACKAGE_PIN U20 [get_ports {adc_dat_b_i[9]}]
+set_property PACKAGE_PIN V20 [get_ports {adc_dat_b_i[10]}]
+set_property PACKAGE_PIN W20 [get_ports {adc_dat_b_i[11]}]
+set_property PACKAGE_PIN W19 [get_ports {adc_dat_b_i[12]}]
+set_property PACKAGE_PIN Y19 [get_ports {adc_dat_b_i[13]}]
+set_property PACKAGE_PIN W18 [get_ports {adc_dat_b_i[14]}]
+set_property PACKAGE_PIN Y18 [get_ports {adc_dat_b_i[15]}]
+
+# clock input
+
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_clk_p_i]
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports adc_clk_n_i]
+set_property PACKAGE_PIN U18 [get_ports adc_clk_p_i]
+set_property PACKAGE_PIN U19 [get_ports adc_clk_n_i]
+
+# clock output
+
+set_property IOSTANDARD LVCMOS18 [get_ports adc_enc_p_o]
+set_property IOSTANDARD LVCMOS18 [get_ports adc_enc_n_o]
+
+set_property SLEW FAST [get_ports adc_enc_p_o]
+set_property SLEW FAST [get_ports adc_enc_n_o]
+
+set_property DRIVE 8 [get_ports adc_enc_p_o]
+set_property DRIVE 8 [get_ports adc_enc_n_o]
+
+set_property PACKAGE_PIN N20 [get_ports adc_enc_p_o]
+set_property PACKAGE_PIN P20 [get_ports adc_enc_n_o]
+
+# clock duty cycle stabilizer (CSn)
+
+set_property IOSTANDARD LVCMOS18 [get_ports adc_csn_o]
+set_property PACKAGE_PIN V18 [get_ports adc_csn_o]
+set_property SLEW FAST [get_ports adc_csn_o]
+set_property DRIVE 8 [get_ports adc_csn_o]
+
+### DAC
+
+# data
+
+set_property IOSTANDARD LVCMOS33 [get_ports {dac_dat_o[*]}]
+set_property SLEW SLOW [get_ports {dac_dat_o[*]}]
+set_property DRIVE 4 [get_ports {dac_dat_o[*]}]
+# set_property IOB TRUE [get_ports {dac_dat_o[*]}]
+
+set_property PACKAGE_PIN M19 [get_ports {dac_dat_o[0]}]
+set_property PACKAGE_PIN M20 [get_ports {dac_dat_o[1]}]
+set_property PACKAGE_PIN L19 [get_ports {dac_dat_o[2]}]
+set_property PACKAGE_PIN L20 [get_ports {dac_dat_o[3]}]
+set_property PACKAGE_PIN K19 [get_ports {dac_dat_o[4]}]
+set_property PACKAGE_PIN J19 [get_ports {dac_dat_o[5]}]
+set_property PACKAGE_PIN J20 [get_ports {dac_dat_o[6]}]
+set_property PACKAGE_PIN H20 [get_ports {dac_dat_o[7]}]
+set_property PACKAGE_PIN G19 [get_ports {dac_dat_o[8]}]
+set_property PACKAGE_PIN G20 [get_ports {dac_dat_o[9]}]
+set_property PACKAGE_PIN F19 [get_ports {dac_dat_o[10]}]
+set_property PACKAGE_PIN F20 [get_ports {dac_dat_o[11]}]
+set_property PACKAGE_PIN D20 [get_ports {dac_dat_o[12]}]
+set_property PACKAGE_PIN D19 [get_ports {dac_dat_o[13]}]
+
+# control
+
+set_property IOSTANDARD LVCMOS33 [get_ports dac_*_o]
+set_property SLEW FAST [get_ports dac_*_o]
+set_property DRIVE 8 [get_ports dac_*_o]
+# set_property IOB TRUE [get_ports {dac_*_o}]
+
+set_property PACKAGE_PIN M17 [get_ports dac_wrt_o]
+set_property PACKAGE_PIN N16 [get_ports dac_sel_o]
+set_property PACKAGE_PIN M18 [get_ports dac_clk_o]
+set_property PACKAGE_PIN N15 [get_ports dac_rst_o]
+
+### PWM
+
+set_property IOSTANDARD LVCMOS18 [get_ports {dac_pwm_o[*]}]
+set_property SLEW FAST [get_ports {dac_pwm_o[*]}]
+set_property DRIVE 12 [get_ports {dac_pwm_o[*]}]
+# set_property IOB TRUE [get_ports {dac_pwm_o[*]}]
+
+set_property PACKAGE_PIN T10 [get_ports {dac_pwm_o[0]}]
+set_property PACKAGE_PIN T11 [get_ports {dac_pwm_o[1]}]
+set_property PACKAGE_PIN P15 [get_ports {dac_pwm_o[2]}]
+set_property PACKAGE_PIN U13 [get_ports {dac_pwm_o[3]}]
+
+### XADC
+
+set_property IOSTANDARD LVCMOS33 [get_ports Vp_Vn_v_p]
+set_property IOSTANDARD LVCMOS33 [get_ports Vp_Vn_v_n]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux0_v_p]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux0_v_n]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux1_v_p]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux1_v_n]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux8_v_p]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux8_v_n]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux9_v_p]
+set_property IOSTANDARD LVCMOS33 [get_ports Vaux9_v_n]
+
+set_property PACKAGE_PIN K9  [get_ports Vp_Vn_v_p]
+set_property PACKAGE_PIN L10 [get_ports Vp_Vn_v_n]
+set_property PACKAGE_PIN C20 [get_ports Vaux0_v_p]
+set_property PACKAGE_PIN B20 [get_ports Vaux0_v_n]
+set_property PACKAGE_PIN E17 [get_ports Vaux1_v_p]
+set_property PACKAGE_PIN D18 [get_ports Vaux1_v_n]
+set_property PACKAGE_PIN B19 [get_ports Vaux8_v_p]
+set_property PACKAGE_PIN A20 [get_ports Vaux8_v_n]
+set_property PACKAGE_PIN E18 [get_ports Vaux9_v_p]
+set_property PACKAGE_PIN E19 [get_ports Vaux9_v_n]
+
+### Expansion connector
+
+set_property IOSTANDARD LVCMOS33 [get_ports {exp_p_tri_io[*]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {exp_n_tri_io[*]}]
+set_property SLEW FAST [get_ports {exp_p_tri_io[*]}]
+set_property SLEW FAST [get_ports {exp_n_tri_io[*]}]
+set_property DRIVE 8 [get_ports {exp_p_tri_io[*]}]
+set_property DRIVE 8 [get_ports {exp_n_tri_io[*]}]
+
+set_property PACKAGE_PIN G17 [get_ports {exp_p_tri_io[0]}]
+set_property PACKAGE_PIN G18 [get_ports {exp_n_tri_io[0]}]
+set_property PACKAGE_PIN H16 [get_ports {exp_p_tri_io[1]}]
+set_property PACKAGE_PIN H17 [get_ports {exp_n_tri_io[1]}]
+set_property PACKAGE_PIN J18 [get_ports {exp_p_tri_io[2]}]
+set_property PACKAGE_PIN H18 [get_ports {exp_n_tri_io[2]}]
+set_property PACKAGE_PIN K17 [get_ports {exp_p_tri_io[3]}]
+set_property PACKAGE_PIN K18 [get_ports {exp_n_tri_io[3]}]
+set_property PACKAGE_PIN L14 [get_ports {exp_p_tri_io[4]}]
+set_property PACKAGE_PIN L15 [get_ports {exp_n_tri_io[4]}]
+set_property PACKAGE_PIN L16 [get_ports {exp_p_tri_io[5]}]
+set_property PACKAGE_PIN L17 [get_ports {exp_n_tri_io[5]}]
+set_property PACKAGE_PIN K16 [get_ports {exp_p_tri_io[6]}]
+set_property PACKAGE_PIN J16 [get_ports {exp_n_tri_io[6]}]
+set_property PACKAGE_PIN M14 [get_ports {exp_p_tri_io[7]}]
+set_property PACKAGE_PIN M15 [get_ports {exp_n_tri_io[7]}]
+
+### SATA connector
+
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_o[*]]
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_n_o[*]]
+
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_i[*]]
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_n_i[*]]
+
+set_property PACKAGE_PIN T12 [get_ports {daisy_p_o[0]}]
+set_property PACKAGE_PIN U12 [get_ports {daisy_n_o[0]}]
+
+set_property PACKAGE_PIN U14 [get_ports {daisy_p_o[1]}]
+set_property PACKAGE_PIN U15 [get_ports {daisy_n_o[1]}]
+
+set_property PACKAGE_PIN P14 [get_ports {daisy_p_i[0]}]
+set_property PACKAGE_PIN R14 [get_ports {daisy_n_i[0]}]
+
+set_property PACKAGE_PIN N18 [get_ports {daisy_p_i[1]}]
+set_property PACKAGE_PIN P19 [get_ports {daisy_n_i[1]}]
+
+### LED
+
+set_property IOSTANDARD LVCMOS33 [get_ports {led_o[*]}]
+set_property SLEW SLOW [get_ports {led_o[*]}]
+set_property DRIVE 4 [get_ports {led_o[*]}]
+
+set_property PACKAGE_PIN F16 [get_ports {led_o[0]}]
+set_property PACKAGE_PIN F17 [get_ports {led_o[1]}]
+set_property PACKAGE_PIN G15 [get_ports {led_o[2]}]
+set_property PACKAGE_PIN H15 [get_ports {led_o[3]}]
+set_property PACKAGE_PIN K14 [get_ports {led_o[4]}]
+set_property PACKAGE_PIN G14 [get_ports {led_o[5]}]
+set_property PACKAGE_PIN J15 [get_ports {led_o[6]}]
+set_property PACKAGE_PIN J14 [get_ports {led_o[7]}]
diff --git a/cfg/red_pitaya.xml b/cfg/red_pitaya.xml
new file mode 100644
index 0000000000000000000000000000000000000000..c48ea199e6e360542bdb68aed65988593206e6c5
--- /dev/null
+++ b/cfg/red_pitaya.xml
@@ -0,0 +1,70 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE project PUBLIC "project" "project.dtd" >
+<project version="1.0" >
+  <set param="PCW::ENET0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::ENET0::GRP_MDIO::ENABLE" value="1" />
+  <set param="PCW::ENET0::ENET0::IO" value="MIO 16 .. 27" />
+  <set param="PCW::ENET0::GRP_MDIO::IO" value="MIO 52 .. 53" />
+  <set param="PCW::GPIO::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::GPIO::MIO_GPIO::ENABLE" value="1" />
+  <set param="PCW::GPIO::EMIO_GPIO::ENABLE" value="1" />
+  <set param="PCW::I2C0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::I2C0::I2C0::IO" value="MIO 50 .. 51" />
+  <set param="PCW::UART0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::UART0::UART0::IO" value="MIO 14 .. 15" />
+  <set param="PCW::UART1::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::UART1::UART1::IO" value="MIO 8 .. 9" />
+  <set param="PCW::USB0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::USB0::RESET::ENABLE" value="1" />
+  <set param="PCW::USB0::RESET::IO" value="MIO 48" />
+  <set param="PCW::SD0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::SD0::SD0::IO" value="MIO 40 .. 45" />
+  <set param="PCW::SD0::GRP_CD::ENABLE" value="1" />
+  <set param="PCW::SD0::GRP_WP::ENABLE" value="1" />
+  <set param="PCW::SD0::GRP_CD::IO" value="MIO 46" />
+  <set param="PCW::SD0::GRP_WP::IO" value="MIO 47" />
+  <set param="PCW::SPI0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::SPI1::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::SPI1::SPI1::IO" value="MIO 10 .. 15" />
+  <set param="PCW::PRESET::BANK0::VOLTAGE" value="LVCMOS 3.3V" />
+  <set param="PCW::PRESET::BANK1::VOLTAGE" value="LVCMOS 2.5V" />
+  <set param="PCW::UIPARAM::DDR::PARTNO" value="MT41J256M16 RE-125" />
+  <set param="PCW::UIPARAM::DDR::BUS_WIDTH" value="16 Bit" />
+  <set param="PCW::MIO::MIO[0]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[16]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[16]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[17]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[17]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[18]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[18]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[19]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[19]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[20]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[20]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[21]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[21]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[22]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[22]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[23]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[23]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[24]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[24]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[25]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[25]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[26]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[26]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[27]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[27]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[28]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[29]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[30]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[31]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[32]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[33]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[34]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[35]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[36]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[37]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[38]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[39]::SLEW" value="fast" />
+</project>
diff --git a/cores/axi_cfg_register_v1_0/axi_cfg_register.vhd b/cores/axi_cfg_register_v1_0/axi_cfg_register.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0dad943ebfdc5146027895c886f3554f5fd883de
--- /dev/null
+++ b/cores/axi_cfg_register_v1_0/axi_cfg_register.vhd
@@ -0,0 +1,146 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity axi_cfg_register is
+  generic (
+  CFG_DATA_WIDTH : natural := 1024;
+  AXI_DATA_WIDTH : natural := 32;
+  AXI_ADDR_WIDTH : natural := 32
+);
+port (
+  -- System signals
+  aclk           : in std_logic;
+  aresetn        : in std_logic;
+
+	-- Configuration bits
+  cfg_data       : out std_logic_vector(CFG_DATA_WIDTH-1 downto 0);
+
+  -- Slave side
+  s_axi_awaddr   : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);  -- AXI4-Lite slave: Write address
+  s_axi_awvalid  : in std_logic;                                    -- AXI4-Lite slave: Write address valid
+  s_axi_awready  : out std_logic;                                   -- AXI4-Lite slave: Write address ready
+  s_axi_wdata    : in std_logic_vector(AXI_DATA_WIDTH-1 downto 0);  -- AXI4-Lite slave: Write data
+  s_axi_wstrb    : in std_logic_vector(AXI_DATA_WIDTH/8-1 downto 0);-- AXI4-Lite slave: Write strobe
+  s_axi_wvalid   : in std_logic;                                    -- AXI4-Lite slave: Write data valid
+  s_axi_wready   : out std_logic;                                   -- AXI4-Lite slave: Write data ready
+  s_axi_bresp    : out std_logic_vector(1 downto 0);                -- AXI4-Lite slave: Write response
+  s_axi_bvalid   : out std_logic;                                   -- AXI4-Lite slave: Write response valid
+  s_axi_bready   : in std_logic;                                    -- AXI4-Lite slave: Write response ready
+  s_axi_araddr   : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);  -- AXI4-Lite slave: Read address
+  s_axi_arvalid  : in std_logic;                                    -- AXI4-Lite slave: Read address valid
+  s_axi_arready  : out std_logic;                                   -- AXI4-Lite slave: Read address ready
+  s_axi_rdata    : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0); -- AXI4-Lite slave: Read data
+  s_axi_rresp    : out std_logic_vector(1 downto 0);                -- AXI4-Lite slave: Read data response
+  s_axi_rvalid   : out std_logic;                                   -- AXI4-Lite slave: Read data valid
+  s_axi_rready   : in std_logic                                     -- AXI4-Lite slave: Read data ready
+);
+end axi_cfg_register;
+
+architecture rtl of axi_cfg_register is
+
+function clogb2 (value: natural) return natural is
+    variable temp    : natural := value;
+    variable ret_val : natural := 1; 
+  begin					
+    while temp > 1 loop
+      ret_val := ret_val + 1;
+      temp    := temp / 2;     
+    end loop;
+  	
+    return ret_val;
+  end function;
+
+function sel(cond: boolean; if_true, if_false: natural) return natural is 
+    begin 
+        if (cond = true) then 
+            return(if_true); 
+        else 
+            return(if_false); 
+        end if; 
+    end function; 
+
+  constant ADDR_LSB : natural := clogb2(AXI_DATA_WIDTH/8 - 1);
+  constant CFG_SIZE : natural := CFG_DATA_WIDTH/AXI_DATA_WIDTH;
+  constant CFG_WIDTH : natural := sel((CFG_SIZE > 1), clogb2(CFG_SIZE-1), 1);
+
+  signal int_bvalid_reg, int_bvalid_next: std_logic;
+
+  signal int_rvalid_reg, int_rvalid_next: std_logic;
+  signal int_rdata_reg, int_rdata_next: std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
+
+  type int_data_mux_t is array (CFG_SIZE-1 downto 0) of std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
+  signal int_data_mux: int_data_mux_t;	
+	
+  signal int_data_wire   : std_logic_vector(CFG_DATA_WIDTH-1 downto 0);
+  signal int_ce_wire     : std_logic_vector(CFG_SIZE-1 downto 0);
+  signal int_wvalid_wire : std_logic;
+  type tmp_s1_t is array (CFG_SIZE-1 downto 0) of std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
+  signal tmp_s1  : tmp_s1_t;--std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
+  signal reset_s : std_logic;
+
+begin
+
+  int_wvalid_wire <= s_axi_awvalid and s_axi_wvalid;
+
+  WORDS: for j in 0 to CFG_SIZE-1 generate 
+    int_data_mux(j) <= int_data_wire(j*AXI_DATA_WIDTH+AXI_DATA_WIDTH-1 downto j*AXI_DATA_WIDTH);
+    int_ce_wire(j)  <= '1' when (int_wvalid_wire = '1') and (unsigned(s_axi_awaddr(ADDR_LSB+CFG_WIDTH-1 downto ADDR_LSB)) = j) else '0';
+    BITS: for k in 0 to AXI_DATA_WIDTH-1 generate
+      tmp_s1(j)(k) <= int_ce_wire(j) and s_axi_wstrb(k/8);
+      FDRE_inst: FDRE 
+       generic map( INIT => '0')
+       port map (
+         Q => int_data_wire(j*AXI_DATA_WIDTH + k),
+         C => aclk,
+         CE => tmp_s1(j)(k),
+         R => reset_s,
+         D => s_axi_wdata(k)
+       );
+    end generate;
+  end generate;
+
+  process(aclk)
+  begin
+    if rising_edge(aclk) then
+    if(aresetn = '0') then
+      reset_s <= '1';
+      int_bvalid_reg <= '0';
+      int_rvalid_reg <= '0';
+      int_rdata_reg <= (others => '0');
+    else 
+      reset_s <= '0';
+      int_bvalid_reg <= int_bvalid_next;
+      int_rvalid_reg <= int_rvalid_next;
+      int_rdata_reg <= int_rdata_next;
+    end if;
+    end if;
+  end process;
+
+  int_bvalid_next <= '1' when (int_wvalid_wire = '1') else
+                     '0' when (s_axi_bready = '1') and (int_bvalid_reg = '1') else
+                     int_bvalid_reg;
+
+  int_rvalid_next <= '1' when (s_axi_arvalid = '1') else
+                     '0' when (s_axi_rready = '1') and (int_rvalid_reg = '1') else
+                     int_rvalid_reg;
+
+  int_rdata_next <= int_data_mux(to_integer(unsigned(s_axi_araddr(ADDR_LSB+CFG_WIDTH-1 downto ADDR_LSB)))) when (s_axi_arvalid = '1') else
+                    int_rdata_reg;
+
+  cfg_data <= int_data_wire;
+  s_axi_bresp <= (others => '0');
+  s_axi_rresp <= (others => '0');
+
+  s_axi_awready <= int_wvalid_wire;
+  s_axi_wready <= int_wvalid_wire;
+  s_axi_bvalid <= int_bvalid_reg;
+  s_axi_arready <= '1';
+  s_axi_rdata <= int_rdata_reg;
+  s_axi_rvalid <= int_rvalid_reg;
+
+end rtl;
diff --git a/cores/axi_cfg_register_v1_0/core_config.tcl b/cores/axi_cfg_register_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..694510dd3720c3096341d4bfb0451a5b2da20f42
--- /dev/null
+++ b/cores/axi_cfg_register_v1_0/core_config.tcl
@@ -0,0 +1,18 @@
+set display_name {AXI Configuration Register}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXI_DATA_WIDTH {AXI DATA WIDTH} {Width of the AXI data bus.}
+core_parameter AXI_ADDR_WIDTH {AXI ADDR WIDTH} {Width of the AXI address bus.}
+core_parameter CFG_DATA_WIDTH {CFG DATA WIDTH} {Width of the configuration data.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axi]
+set_property NAME S_AXI $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE S_AXI $parameter
diff --git a/cores/axi_sts_register_v1_0/axi_sts_register.vhd b/cores/axi_sts_register_v1_0/axi_sts_register.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..347df1ca4590bd2617ceb3f76d152a5f9cdd31fa
--- /dev/null
+++ b/cores/axi_sts_register_v1_0/axi_sts_register.vhd
@@ -0,0 +1,108 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity axi_sts_register is
+  generic (
+  STS_DATA_WIDTH : integer := 1024;
+  AXI_DATA_WIDTH : integer := 32;
+  AXI_ADDR_WIDTH: integer := 32
+);
+port (
+  -- System signals
+  aclk: in std_logic;
+  aresetn : in std_logic;
+
+  -- Status bits
+  sts_data : in std_logic_vector(STS_DATA_WIDTH-1 downto 0);
+
+  -- Slave side
+  s_axi_awaddr: in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);  -- AXI4-Lite slave: Write address
+  s_axi_awvalid: in std_logic;                                   -- AXI4-Lite slave: Write address valid
+  s_axi_awready: out std_logic;                                  -- AXI4-Lite slave: Write address ready
+  s_axi_wdata: in std_logic_vector(AXI_DATA_WIDTH-1 downto 0);   -- AXI4-Lite slave: Write data
+  s_axi_wvalid: in std_logic;                                    -- AXI4-Lite slave: Write data valid
+  s_axi_wready: out std_logic;                                   -- AXI4-Lite slave: Write data ready
+  s_axi_bresp: out std_logic_vector(1 downto 0);                 -- AXI4-Lite slave: Write response
+  s_axi_bvalid: out std_logic;                                   -- AXI4-Lite slave: Write response valid
+  s_axi_bready: in std_logic;                                    -- AXI4-Lite slave: Write response ready
+  s_axi_araddr: in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);  -- AXI4-Lite slave: Read address
+  s_axi_arvalid: in std_logic;                                   -- AXI4-Lite slave: Read address valid
+  s_axi_arready: out std_logic;                                  -- AXI4-Lite slave: Read address ready
+  s_axi_rdata: out std_logic_vector(AXI_DATA_WIDTH-1 downto 0);  -- AXI4-Lite slave: Read data
+  s_axi_rresp: out std_logic_vector(1 downto 0);                 -- AXI4-Lite slave: Read data response
+  s_axi_rvalid: out std_logic;                                   -- AXI4-Lite slave: Read data valid
+  s_axi_rready: in std_logic                                     -- AXI4-Lite slave: Read data ready
+);
+end axi_sts_register;
+
+architecture rtl of axi_sts_register is
+
+function clogb2 (value: natural) return integer is
+    variable temp    : integer := value;
+    variable ret_val : integer := 1; 
+  begin					
+    while temp > 1 loop
+      ret_val := ret_val + 1;
+      temp    := temp / 2;     
+    end loop;
+  	
+    return ret_val;
+  end function;
+
+function sel(cond: boolean; if_true, if_false: integer) return integer is 
+    begin 
+        if (cond = true) then 
+            return(if_true); 
+        else 
+            return(if_false); 
+        end if; 
+    end function; 
+
+  constant ADDR_LSB : integer := clogb2(AXI_DATA_WIDTH/8 - 1);
+  constant STS_SIZE : integer := STS_DATA_WIDTH/AXI_DATA_WIDTH;
+  constant STS_WIDTH : integer := sel((STS_SIZE > 1), clogb2(STS_SIZE-1), 1);
+
+  signal int_rvalid_reg, int_rvalid_next: std_logic;
+  signal int_rdata_reg, int_rdata_next: std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
+
+  type int_data_mux_t is array (STS_SIZE-1 downto 0) of std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
+  signal int_data_mux: int_data_mux_t;	
+
+begin
+
+  WORDS: for j in 0 to STS_SIZE-1 generate 
+     int_data_mux(j) <= sts_data(j*AXI_DATA_WIDTH+AXI_DATA_WIDTH-1 downto j*AXI_DATA_WIDTH);
+  end generate;
+
+  process(aclk)
+  begin
+    if rising_edge(aclk) then
+    if(aresetn = '0') then
+      int_rvalid_reg <= '0';
+      int_rdata_reg <= (others => '0');
+    else
+      int_rvalid_reg <= int_rvalid_next;
+      int_rdata_reg <= int_rdata_next;
+    end if;
+    end if;
+  end process;
+
+  int_rvalid_next <= '1' when (s_axi_arvalid = '1') else
+                     '0' when (s_axi_rready = '1') and (int_rvalid_reg = '1') else
+                     int_rvalid_reg;
+
+  int_rdata_next <= int_data_mux(to_integer(unsigned(s_axi_araddr(ADDR_LSB+STS_WIDTH-1 downto ADDR_LSB)))) when (s_axi_arvalid = '1') else
+                    int_rdata_reg;
+
+  s_axi_rresp <= (others => '0');
+
+  s_axi_arready <= '1';
+  s_axi_rdata <= int_rdata_reg;
+  s_axi_rvalid <= int_rvalid_reg;
+
+end rtl;
diff --git a/cores/axi_sts_register_v1_0/core_config.tcl b/cores/axi_sts_register_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..048310cd9bcb8abb4565fe3c816d0c7e8e62412d
--- /dev/null
+++ b/cores/axi_sts_register_v1_0/core_config.tcl
@@ -0,0 +1,18 @@
+set display_name {AXI Status Register}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXI_DATA_WIDTH {AXI DATA WIDTH} {Width of the AXI data bus.}
+core_parameter AXI_ADDR_WIDTH {AXI ADDR WIDTH} {Width of the AXI address bus.}
+core_parameter STS_DATA_WIDTH {STS DATA WIDTH} {Width of the status data.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axi]
+set_property NAME S_AXI $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE S_AXI $parameter
diff --git a/cores/axis_bram_reader_v1_0/axis_bram_reader.vhd b/cores/axis_bram_reader_v1_0/axis_bram_reader.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..54ca5a94d39d0cb616aa69859c8c66db08c11ae0
--- /dev/null
+++ b/cores/axis_bram_reader_v1_0/axis_bram_reader.vhd
@@ -0,0 +1,90 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axis_bram_reader is
+  generic (
+            BRAM_ADDR_WIDTH   : natural := 10;
+            BRAM_DATA_WIDTH   : natural := 32;
+            AXIS_TDATA_WIDTH  : natural := 32
+          );
+  port (
+         -- System signals
+         aclk             : in std_logic;
+         aresetn          : in std_logic;
+
+         cfg_data         : in std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+         sts_data         : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+
+         -- Master side
+         m_axis_tready    : in std_logic;
+         m_axis_tdata     : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+         m_axis_tvalid    : out std_logic;
+         m_axis_tlast     : out std_logic;
+
+         --m_axis_config_tready : in std_logic;
+         --m_axis_config_tvalid : out std_logic;
+
+         -- BRAM port
+         bram_porta_clk   : out std_logic;
+         bram_porta_rst   : out std_logic;
+         bram_porta_addr  : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+         bram_porta_rddata: in std_logic_vector(BRAM_DATA_WIDTH-1 downto 0)
+       );
+end axis_bram_reader;
+
+architecture rtl of axis_bram_reader is
+
+  signal addr_reg, addr_next     : unsigned(BRAM_ADDR_WIDTH-1 downto 0);
+  signal addr_dly_reg, addr_dly_next : unsigned(BRAM_ADDR_WIDTH-1 downto 0);
+  signal tlast_reg, tlast_next   : std_logic;
+  signal comp_reg, comp_next     : std_logic;
+
+begin
+
+  process(aclk)
+  begin
+    if rising_edge(aclk) then
+      if aresetn = '0' then
+        addr_reg <= (others => '0');
+        comp_reg <= '0';
+        addr_dly_reg <= (others => '0');
+        tlast_reg <= '0';
+      else 
+        addr_reg <= addr_next;
+        comp_reg <= comp_next;
+        addr_dly_reg <= addr_dly_next;
+        tlast_reg <= tlast_next;
+      end if;
+    end if;
+  end process;
+
+  -- Next state logic
+  comp_next <= '0' when (addr_reg = unsigned(cfg_data)) else
+               '1';
+
+  tlast_next <= '1' when (addr_reg = unsigned(cfg_data)-1) else
+                '0';
+
+  addr_next <= addr_reg + 1 when (m_axis_tready = '1') and (comp_reg = '1') else
+               (others => '0') when (comp_reg = '0') else
+               addr_reg;
+
+  addr_dly_next <= addr_reg;
+
+  --tvalid_next <= '1' when (tvalid_reg = '0') and (comp_reg = '1') else 
+  --							 '0' when 
+  --							 tvalid_reg;
+
+  sts_data <= std_logic_vector(addr_dly_reg);
+
+  m_axis_tdata  <= bram_porta_rddata;
+  m_axis_tvalid <= comp_reg;
+  m_axis_tlast  <= tlast_reg;
+
+  bram_porta_clk <= aclk;
+  bram_porta_rst <= not aresetn;
+  bram_porta_addr <= std_logic_vector(addr_next);
+
+end rtl;
diff --git a/cores/axis_bram_reader_v1_0/core_config.tcl b/cores/axis_bram_reader_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..bc9d829694dda11ac02202f2f2607f7759e48942
--- /dev/null
+++ b/cores/axis_bram_reader_v1_0/core_config.tcl
@@ -0,0 +1,35 @@
+set display_name {AXI4-Stream Block RAM Reader}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the M_AXIS data bus.}
+core_parameter BRAM_DATA_WIDTH {BRAM DATA WIDTH} {Width of the BRAM data port.}
+core_parameter BRAM_ADDR_WIDTH {BRAM ADDR WIDTH} {Width of the BRAM address port.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core m_axis]
+set_property NAME M_AXIS $bus
+set_property INTERFACE_MODE master $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE M_AXIS $parameter
+
+set bus [ipx::add_bus_interface BRAM_PORTA $core]
+set_property ABSTRACTION_TYPE_VLNV xilinx.com:interface:bram_rtl:1.0 $bus
+set_property BUS_TYPE_VLNV xilinx.com:interface:bram:1.0 $bus
+set_property INTERFACE_MODE master $bus
+foreach {logical physical} {
+  RST  bram_porta_rst
+  CLK  bram_porta_clk
+  ADDR bram_porta_addr
+  DOUT bram_porta_rddata
+} {
+  set_property PHYSICAL_NAME $physical [ipx::add_port_map $logical $bus]
+}
+
+set bus [ipx::get_bus_interfaces bram_porta_clk]
+set parameter [ipx::add_bus_parameter ASSOCIATED_BUSIF $bus]
+set_property VALUE BRAM_PORTA $parameter
diff --git a/cores/axis_bram_writer_v1_0/axis_bram_writer.vhd b/cores/axis_bram_writer_v1_0/axis_bram_writer.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ac290e411f2003e1b5bc5dabe32f1f08312c1e47
--- /dev/null
+++ b/cores/axis_bram_writer_v1_0/axis_bram_writer.vhd
@@ -0,0 +1,73 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axis_bram_writer is
+  generic (
+            BRAM_ADDR_WIDTH   : natural := 10;
+            BRAM_DATA_WIDTH   : natural := 32;
+            AXIS_TDATA_WIDTH  : natural := 32
+          );
+  port (
+         -- System signals
+         aclk             : in std_logic;
+         aresetn          : in std_logic;
+
+         sts_data         : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+
+         -- Slave side
+         s_axis_tready    : out std_logic;
+         s_axis_tdata     : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+         s_axis_tvalid    : in std_logic;
+
+         -- BRAM port
+         bram_porta_clk   : out std_logic;
+         bram_porta_rst   : out std_logic;
+         bram_porta_addr  : out std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+         bram_porta_wrdata: out std_logic_vector(BRAM_DATA_WIDTH-1 downto 0);
+         bram_porta_we    : out std_logic_vector(BRAM_DATA_WIDTH/8-1 downto 0)
+       );
+end axis_bram_writer;
+
+architecture rtl of axis_bram_writer is
+  signal addr_reg, addr_next : std_logic_vector(BRAM_ADDR_WIDTH-1 downto 0);
+  signal enbl_reg, enbl_next : std_logic;
+  signal s_aux1              : std_logic;
+
+begin
+
+  process(aclk)
+  begin
+    if rising_edge(aclk) then
+      if (aresetn = '0') then
+        addr_reg <= (others => '0');
+        enbl_reg <= '0';
+      else
+        addr_reg <= addr_next;
+        enbl_reg <= enbl_next;
+      end if;
+    end if;
+  end process;
+
+  -- Next state logic
+  enbl_next <= '1' when enbl_reg = '0' else
+               enbl_reg;
+
+  addr_next <= std_logic_vector(unsigned(addr_reg)+1) when (s_axis_tvalid = '1') and (enbl_reg = '1') else
+               addr_reg;
+
+  sts_data <= addr_reg;
+
+  s_axis_tready <= enbl_reg;
+
+  s_aux1 <= '1' when (s_axis_tvalid = '1') and (enbl_reg = '1') else 
+            '0';
+
+  bram_porta_clk    <= aclk;
+  bram_porta_rst    <= not aresetn;
+  bram_porta_addr   <= addr_reg;
+  bram_porta_wrdata <= s_axis_tdata;
+  bram_porta_we     <= ((BRAM_DATA_WIDTH/8-1) downto 0 => s_aux1); 
+
+end rtl;
diff --git a/cores/axis_bram_writer_v1_0/core_config.tcl b/cores/axis_bram_writer_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5f6bafdb0005c70dc4f2a71478f04c5115eb6886
--- /dev/null
+++ b/cores/axis_bram_writer_v1_0/core_config.tcl
@@ -0,0 +1,36 @@
+set display_name {AXI4-Stream Block RAM Writer}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the S_AXIS data bus.}
+core_parameter BRAM_DATA_WIDTH {BRAM DATA WIDTH} {Width of the BRAM data port.}
+core_parameter BRAM_ADDR_WIDTH {BRAM ADDR WIDTH} {Width of the BRAM address port.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axis]
+set_property NAME S_AXIS $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE S_AXIS $parameter
+
+set bus [ipx::add_bus_interface BRAM_PORTA $core]
+set_property ABSTRACTION_TYPE_VLNV xilinx.com:interface:bram_rtl:1.0 $bus
+set_property BUS_TYPE_VLNV xilinx.com:interface:bram:1.0 $bus
+set_property INTERFACE_MODE master $bus
+foreach {logical physical} {
+  RST  bram_porta_rst
+  CLK  bram_porta_clk
+  ADDR bram_porta_addr
+  DIN  bram_porta_wrdata
+  WE   bram_porta_we
+} {
+  set_property PHYSICAL_NAME $physical [ipx::add_port_map $logical $bus]
+}
+
+set bus [ipx::get_bus_interfaces bram_porta_clk]
+set parameter [ipx::add_bus_parameter ASSOCIATED_BUSIF $bus]
+set_property VALUE BRAM_PORTA $parameter
diff --git a/cores/axis_ram_writer_v1_0/axis_ram_writer.vhd b/cores/axis_ram_writer_v1_0/axis_ram_writer.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8203039efbb215110f313b8050c9305722fd34e1
--- /dev/null
+++ b/cores/axis_ram_writer_v1_0/axis_ram_writer.vhd
@@ -0,0 +1,164 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity axis_ram_writer is
+  generic (
+            ADDR_WIDTH       : natural := 20;
+            AXI_ID_WIDTH     : natural := 6;
+            AXI_ADDR_WIDTH   : natural := 32;
+            AXI_DATA_WIDTH   : natural := 64;
+            AXIS_TDATA_WIDTH : natural := 64
+          );
+  port (
+         -- System signals
+         aclk             : in std_logic;
+         aresetn          : in std_logic;
+
+         -- Configuration bits
+         cfg_data         : in std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);
+         sts_data         : out std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+         -- Master side
+         m_axi_awid       : out std_logic_vector(AXI_ID_WIDTH-1 downto 0);     -- AXI master: Write address ID
+         m_axi_awaddr     : out std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);   -- AXI master: Write address
+         m_axi_awlen      : out std_logic_vector(3 downto 0);                  -- AXI master: Write burst length
+         m_axi_awsize     : out std_logic_vector(2 downto 0);                  -- AXI master: Write burst size
+         m_axi_awburst    : out std_logic_vector(1 downto 0);                  -- AXI master: Write burst type
+         m_axi_awcache    : out std_logic_vector(3 downto 0);                  -- AXI master: Write memory type
+         m_axi_awvalid    : out std_logic;                                     -- AXI master: Write address valid
+         m_axi_awready    : in std_logic;                                      -- AXI master: Write address ready
+         m_axi_wid        : out std_logic_vector(AXI_ID_WIDTH-1 downto 0);     -- AXI master: Write data ID
+         m_axi_wdata      : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0);   -- AXI master: Write data
+         m_axi_wstrb      : out std_logic_vector(AXI_DATA_WIDTH/8-1 downto 0); -- AXI master: Write strobes
+         m_axi_wlast      : out std_logic;                                     -- AXI master: Write last
+         m_axi_wvalid     : out std_logic;                                     -- AXI master: Write valid
+         m_axi_wready     : in std_logic;                                      -- AXI master: Write ready
+         m_axi_bvalid     : in std_logic;                                      -- AXI master: Write response valid
+         m_axi_bready     : out std_logic;                                     -- AXI master: Write response ready
+
+         -- Slave side
+         s_axis_tready    : out std_logic;
+         s_axis_tdata     : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+         s_axis_tvalid    : in std_logic
+       );
+end axis_ram_writer;
+
+architecture rtl of axis_ram_writer is
+
+  function clogb2 (value: natural) return natural is
+  variable temp    : natural := value;
+  variable ret_val : natural := 1;
+  begin
+    while temp > 1 loop
+      ret_val := ret_val + 1;
+      temp    := temp / 2;
+    end loop;
+    return ret_val;
+  end function;
+
+  constant ADDR_SIZE : natural := clogb2((AXI_DATA_WIDTH/8) - 1);
+
+  signal int_awvalid_reg, int_awvalid_next : std_logic;
+  signal int_wvalid_reg, int_wvalid_next   : std_logic;
+  signal int_addr_reg, int_addr_next       : unsigned(ADDR_WIDTH-1 downto 0);
+  signal int_wid_reg, int_wid_next         : unsigned(AXI_ID_WIDTH-1 downto 0);
+
+  signal int_full_wire, int_empty_wire, int_rden_wire : std_logic;
+  signal int_wlast_wire, int_tready_wire   : std_logic;
+  signal int_wdata_wire                    : std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
+
+  signal tmp_s2                            : std_logic;
+  signal reset                             : std_logic;
+
+begin
+
+  int_tready_wire <= not int_full_wire;
+  int_wlast_wire <= '1' when (int_addr_reg(3 downto 0) = "1111") else '0';
+  int_rden_wire <= m_axi_wready and int_wvalid_reg;
+  tmp_s2 <= int_tready_wire and s_axis_tvalid;
+
+  reset <= not aresetn;
+
+  FIFO36E1_inst: FIFO36E1 
+  generic map(
+               FIRST_WORD_FALL_THROUGH => TRUE,
+               ALMOST_EMPTY_OFFSET => X"000F",
+               DATA_WIDTH => 72,
+               FIFO_MODE => "FIFO36_72"
+             ) 
+  port map (
+             ALMOSTEMPTY => int_empty_wire,
+             ALMOSTFULL  => open,
+             EMPTY       => open,
+             FULL        => int_full_wire,
+             DOP         => open,
+             DO          => int_wdata_wire,
+             INJECTDBITERR => '0', 
+             INJECTSBITERR => '0',
+             RDCLK       => aclk,
+             RDEN        => int_rden_wire,
+             REGCE       => '1',
+             RST         => reset,
+             RSTREG      => '0',
+             WRCLK       => aclk,
+             WREN        => tmp_s2,
+             DI          => s_axis_tdata,
+             DIP         => X"00"
+           );
+
+  process(aclk)
+  begin
+    if (rising_edge(aclk)) then
+      if (reset = '1') then
+        int_awvalid_reg <= '0';
+        int_wvalid_reg <= '0';
+        int_addr_reg <= (others => '0');
+        int_wid_reg <= (others => '0');
+      else
+        int_awvalid_reg <= int_awvalid_next;
+        int_wvalid_reg <= int_wvalid_next;
+        int_addr_reg <= int_addr_next;
+        int_wid_reg <= int_wid_next;
+      end if;
+    end if;
+  end process;
+
+  int_awvalid_next <= '1' when ((int_empty_wire = '0') and (int_awvalid_reg = '0') and (int_wvalid_reg = '0')) or 
+                      ((m_axi_wready = '1') and (int_wlast_wire = '1') and (int_empty_wire = '0')) else 
+                      '0' when ((m_axi_awready = '1') and (int_awvalid_reg = '1')) else
+                      int_awvalid_reg;
+
+  int_wvalid_next <= '1' when ((int_empty_wire = '0') and (int_awvalid_reg = '0') and (int_wvalid_reg = '0')) else 
+                     '0' when (m_axi_wready = '1') and (int_wlast_wire = '1') and (int_empty_wire = '1') else
+                     int_wvalid_reg;
+
+  int_addr_next <= int_addr_reg + 1 when (int_rden_wire = '1') else
+                   int_addr_reg;
+
+  int_wid_next <= int_wid_reg + 1 when (m_axi_wready = '1') and (int_wlast_wire = '1') else
+                  int_wid_reg;
+
+  sts_data      <= std_logic_vector(int_addr_reg);
+
+  m_axi_awid    <= std_logic_vector(int_wid_reg);
+  m_axi_awaddr  <= std_logic_vector(unsigned(cfg_data) + (int_addr_reg & (ADDR_SIZE-1 downto 0 => '0')));
+  m_axi_awlen   <= std_logic_vector(to_unsigned(15, m_axi_awlen'length));
+  m_axi_awsize  <= std_logic_vector(to_unsigned(ADDR_SIZE, m_axi_awsize'length));
+  m_axi_awburst <= "01";
+  m_axi_awcache <= "0011";
+  m_axi_awvalid <= int_awvalid_reg;
+  m_axi_wid     <= std_logic_vector(int_wid_reg);
+  m_axi_wdata   <= int_wdata_wire;
+  m_axi_wstrb   <= ((AXI_DATA_WIDTH/8-1) downto 0 => '1');
+  m_axi_wlast   <= int_wlast_wire;
+  m_axi_wvalid  <= int_wvalid_reg;
+  m_axi_bready  <= '1';
+
+  s_axis_tready <= int_tready_wire;
+
+end rtl;
diff --git a/cores/axis_ram_writer_v1_0/core_config.tcl b/cores/axis_ram_writer_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ef4f457b07574795b08f2ae5cf1409e2667244f1
--- /dev/null
+++ b/cores/axis_ram_writer_v1_0/core_config.tcl
@@ -0,0 +1,28 @@
+set display_name {AXI4-Stream RAM Writer}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXI_DATA_WIDTH {AXI DATA WIDTH} {Width of the AXI data bus.}
+core_parameter AXI_ADDR_WIDTH {AXI ADDR WIDTH} {Width of the AXI address bus.}
+core_parameter AXI_ID_WIDTH {AXI ID WIDTH} {Width of the AXI ID bus.}
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the S_AXIS data bus.}
+core_parameter ADDR_WIDTH {ADDR WIDTH} {Width of the address.}
+
+set address [ipx::get_address_spaces m_axi -of_objects $core]
+set_property NAME M_AXI $address
+
+set bus [ipx::get_bus_interfaces -of_objects $core m_axi]
+set_property NAME M_AXI $bus
+set_property INTERFACE_MODE master $bus
+set_property MASTER_ADDRESS_SPACE_REF M_AXI $bus
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axis]
+set_property NAME S_AXIS $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE M_AXI:S_AXIS $parameter
diff --git a/cores/axis_rp_adc_v1_0/axis_rp_adc.vhd b/cores/axis_rp_adc_v1_0/axis_rp_adc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..f82482587212ba79db04b7abd5bfa93268b888a9
--- /dev/null
+++ b/cores/axis_rp_adc_v1_0/axis_rp_adc.vhd
@@ -0,0 +1,57 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axis_rp_adc is
+  generic (
+  ADC_DATA_WIDTH : natural := 14;
+  AXIS_TDATA_WIDTH: natural := 32
+);
+port (
+  -- System signals
+  aclk : in std_logic;
+
+  -- ADC signals
+  adc_csn : out std_logic;
+  adc_dat_a : in std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+  adc_dat_b : in std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+
+  -- Master side
+  m_axis_tvalid : out std_logic;
+  m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0)
+);
+end axis_rp_adc;
+
+architecture rtl of axis_rp_adc is
+
+  constant PADDING_WIDTH : natural := AXIS_TDATA_WIDTH/2 - ADC_DATA_WIDTH;
+
+  signal int_dat_a_reg : std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+  signal int_dat_b_reg : std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+  signal dat_a_tmp, dat_b_tmp : std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+
+begin
+
+  process(aclk)
+  begin
+  if rising_edge(aclk) then 
+    int_dat_a_reg <= adc_dat_a;
+    int_dat_b_reg <= adc_dat_b;
+  end if;
+  end process;
+
+  adc_csn <= '1';
+
+  m_axis_tvalid <= '1';
+
+  --Format conversion
+  dat_a_tmp(ADC_DATA_WIDTH-1) <= not int_dat_a_reg(ADC_DATA_WIDTH-1);
+  dat_a_tmp(ADC_DATA_WIDTH-2 downto 0) <=  int_dat_a_reg(ADC_DATA_WIDTH-2 downto 0);
+  dat_b_tmp(ADC_DATA_WIDTH-1) <= not int_dat_b_reg(ADC_DATA_WIDTH-1);
+  dat_b_tmp(ADC_DATA_WIDTH-2 downto 0) <=  int_dat_b_reg(ADC_DATA_WIDTH-2 downto 0);
+  
+  --padding to m_axis_tdata size
+  m_axis_tdata <= ((PADDING_WIDTH-1) downto 0 => dat_b_tmp(ADC_DATA_WIDTH-1)) & dat_b_tmp & ((PADDING_WIDTH-1) downto 0 => dat_a_tmp(ADC_DATA_WIDTH-1)) & dat_a_tmp;
+
+end rtl;
diff --git a/cores/axis_rp_adc_v1_0/core_config.tcl b/cores/axis_rp_adc_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c61fb615ceb8d23657ddcf52b43bf52e5fa3b70b
--- /dev/null
+++ b/cores/axis_rp_adc_v1_0/core_config.tcl
@@ -0,0 +1,17 @@
+set display_name {AXI4-Stream Red Pitaya ADC}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the M_AXIS data bus.}
+core_parameter ADC_DATA_WIDTH {ADC DATA WIDTH} {Width of the ADC data bus.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core m_axis]
+set_property NAME M_AXIS $bus
+set_property INTERFACE_MODE master $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::add_bus_parameter ASSOCIATED_BUSIF $bus]
+set_property VALUE M_AXIS $parameter
diff --git a/cores/axis_rp_adc_v3_0/axis_rp_adc.vhd b/cores/axis_rp_adc_v3_0/axis_rp_adc.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..9d80e8cf2bab177627ec4d96ee1adfe5fa88809b
--- /dev/null
+++ b/cores/axis_rp_adc_v3_0/axis_rp_adc.vhd
@@ -0,0 +1,57 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axis_rp_adc is
+  generic (
+  ADC_DATA_WIDTH : natural := 14;
+  AXIS_TDATA_WIDTH: natural := 32
+);
+port (
+  -- System signals
+  aclk : in std_logic;
+
+  -- ADC signals
+  adc_csn : out std_logic;
+  adc_dat_a : in std_logic_vector((AXIS_TDATA_WIDTH/2)-1 downto 0);
+  adc_dat_b : in std_logic_vector((AXIS_TDATA_WIDTH/2)-1 downto 0);
+
+  -- Master side
+  m_axis_tvalid : out std_logic;
+  m_axis_tdata : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0)
+);
+end axis_rp_adc;
+
+architecture rtl of axis_rp_adc is
+
+  constant PADDING_WIDTH : natural := AXIS_TDATA_WIDTH/2 - ADC_DATA_WIDTH;
+
+  signal int_dat_a_reg : std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+  signal int_dat_b_reg : std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+  signal dat_a_tmp, dat_b_tmp : std_logic_vector(ADC_DATA_WIDTH-1 downto 0);
+
+begin
+
+  process(aclk)
+  begin
+  if rising_edge(aclk) then 
+    int_dat_a_reg <= adc_dat_a(16-1 downto PADDING_WIDTH);
+    int_dat_b_reg <= adc_dat_b(16-1 downto PADDING_WIDTH);
+  end if;
+  end process;
+
+  adc_csn <= '1';
+
+  m_axis_tvalid <= '1';
+
+  --Format conversion
+  dat_a_tmp(ADC_DATA_WIDTH-1) <= int_dat_a_reg(ADC_DATA_WIDTH-1);
+  dat_a_tmp(ADC_DATA_WIDTH-2 downto 0) <=  not int_dat_a_reg(ADC_DATA_WIDTH-2 downto 0);
+  dat_b_tmp(ADC_DATA_WIDTH-1) <= int_dat_b_reg(ADC_DATA_WIDTH-1);
+  dat_b_tmp(ADC_DATA_WIDTH-2 downto 0) <=  not int_dat_b_reg(ADC_DATA_WIDTH-2 downto 0);
+  
+  --padding to m_axis_tdata size
+  m_axis_tdata <= ((PADDING_WIDTH-1) downto 0 => dat_b_tmp(ADC_DATA_WIDTH-1)) & dat_b_tmp & ((PADDING_WIDTH-1) downto 0 => dat_a_tmp(ADC_DATA_WIDTH-1)) & dat_a_tmp;
+
+end rtl;
diff --git a/cores/axis_rp_adc_v3_0/core_config.tcl b/cores/axis_rp_adc_v3_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..c61fb615ceb8d23657ddcf52b43bf52e5fa3b70b
--- /dev/null
+++ b/cores/axis_rp_adc_v3_0/core_config.tcl
@@ -0,0 +1,17 @@
+set display_name {AXI4-Stream Red Pitaya ADC}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the M_AXIS data bus.}
+core_parameter ADC_DATA_WIDTH {ADC DATA WIDTH} {Width of the ADC data bus.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core m_axis]
+set_property NAME M_AXIS $bus
+set_property INTERFACE_MODE master $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::add_bus_parameter ASSOCIATED_BUSIF $bus]
+set_property VALUE M_AXIS $parameter
diff --git a/cores/axis_tlast_gen_v1_0/axis_tlast_gen.vhd b/cores/axis_tlast_gen_v1_0/axis_tlast_gen.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..512bf56d4e515daa445d2002b98b89946a52d065
--- /dev/null
+++ b/cores/axis_tlast_gen_v1_0/axis_tlast_gen.vhd
@@ -0,0 +1,67 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity axis_tlast_gen is
+  generic (
+  AXIS_TDATA_WIDTH : natural := 8;
+  PKT_CNTR_BITS    : natural := 8 -- number of bits of the packet counter
+);
+port (
+  -- System signals
+  aclk          : in std_logic;
+  aresetn       : in std_logic;
+
+  -- Control signals
+  pkt_length    : in std_logic_vector((PKT_CNTR_BITS-1) downto 0);
+
+  -- Master side
+  m_axis_tvalid : out std_logic;
+  m_axis_tready : in std_logic;
+  m_axis_tlast  : out std_logic;
+  m_axis_tdata  : out std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0);
+
+  -- Slave side
+  s_axis_tvalid : in std_logic;
+  s_axis_tready : out std_logic;
+  s_axis_tdata  : in std_logic_vector(AXIS_TDATA_WIDTH-1 downto 0)
+);
+end axis_tlast_gen;
+
+architecture rtl of axis_tlast_gen is
+
+  -- Internal signals
+  signal new_sample  : std_logic;
+  signal cnt         : std_logic_vector((PKT_CNTR_BITS-1) downto 0) := (others => '0');
+  signal axis_tlast  : std_logic;
+  signal axis_tready : std_logic;
+begin
+
+  -- Pass through control signals
+  s_axis_tready <= m_axis_tready;
+  m_axis_tvalid <= s_axis_tvalid;
+  m_axis_tdata  <= s_axis_tdata;
+
+  axis_tready <= m_axis_tready;
+  -- Count samples
+  new_sample <= s_axis_tvalid and axis_tready;
+
+  process(aclk)
+  begin
+    if rising_edge(aclk) then 
+      if (aresetn = '0' or (axis_tlast = '1' and new_sample = '1')) then
+          cnt <= (others => '0');
+      else
+        if (new_sample = '1') then
+          cnt <= std_logic_vector(unsigned(cnt) + 1);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  -- Generate tlast
+  axis_tlast <= '1' when (unsigned(cnt) = unsigned(unsigned(pkt_length)-1)) else '0';
+  m_axis_tlast <= axis_tlast;
+
+end rtl;
diff --git a/cores/axis_tlast_gen_v1_0/core_config.tcl b/cores/axis_tlast_gen_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f82d26a2056a23b7abbaa3e5a8305def590ce528
--- /dev/null
+++ b/cores/axis_tlast_gen_v1_0/core_config.tcl
@@ -0,0 +1,22 @@
+set display_name {AXI4-Stream Tlast Generator}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter AXIS_TDATA_WIDTH {AXIS TDATA WIDTH} {Width of the M_AXIS data bus.}
+core_parameter PKT_CNTR_BITS    {PKT CNTR BITS} {Number of bits of the packet counter.}
+
+set bus [ipx::get_bus_interfaces -of_objects $core m_axis]
+set_property NAME M_AXIS $bus
+set_property INTERFACE_MODE master $bus
+
+set bus [ipx::get_bus_interfaces -of_objects $core s_axis]
+set_property NAME S_AXIS $bus
+set_property INTERFACE_MODE slave $bus
+
+set bus [ipx::get_bus_interfaces aclk]
+set parameter [ipx::get_bus_parameters -of_objects $bus ASSOCIATED_BUSIF]
+set_property VALUE M_AXIS:S_AXIS $parameter
+
diff --git a/cores/dc_removal_v1_0/core_config.tcl b/cores/dc_removal_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b6d4f20b1d14950e57e94777fe5523cfd0965765
--- /dev/null
+++ b/cores/dc_removal_v1_0/core_config.tcl
@@ -0,0 +1,8 @@
+set display_name {Digital DC removal circuit}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter DATA_WIDTH {DATA WIDTH} {Width of the data bus.}
diff --git a/cores/dc_removal_v1_0/dc_removal.vhd b/cores/dc_removal_v1_0/dc_removal.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..bc0b25f1586c83d8d50e8127b1722e18469f3fed
--- /dev/null
+++ b/cores/dc_removal_v1_0/dc_removal.vhd
@@ -0,0 +1,92 @@
+-- See WP279 from Xilinx
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity dc_removal is
+				generic(
+											 DATA_WIDTH : integer := 16
+							 );
+				port (
+										 aclk    : in std_logic;
+										 aresetn : in std_logic;
+										 k_i     : in std_logic_vector(DATA_WIDTH-1 downto 0);
+										 data_i  : in std_logic_vector(DATA_WIDTH-1 downto 0);
+										 data_o  : out std_logic_vector(DATA_WIDTH-1 downto 0)
+						 );
+end dc_removal;
+
+architecture rtl of dc_removal is
+				signal k_reg, k_next     : std_logic_vector(DATA_WIDTH-1 downto 0);
+				signal d0_reg, d0_next   : std_logic_vector(DATA_WIDTH-1 downto 0);
+				signal d11_reg, d11_next : std_logic_vector(DATA_WIDTH-1 downto 0);
+				signal d12_reg, d12_next : std_logic_vector(DATA_WIDTH-1 downto 0);
+				signal d21_reg, d21_next : std_logic_vector(DATA_WIDTH-1 downto 0);
+				signal d22_reg, d22_next : std_logic_vector(2*DATA_WIDTH-1 downto 0);
+				signal d31_reg, d31_next : std_logic_vector(DATA_WIDTH-1 downto 0);
+				signal d32_reg, d32_next : std_logic_vector(2*DATA_WIDTH-1 downto 0);
+				signal d4_reg, d4_next   : std_logic_vector(DATA_WIDTH-1 downto 0);
+				signal mult_s            : std_logic_vector(2*DATA_WIDTH-1 downto 0);
+				signal sub_s             : std_logic_vector(DATA_WIDTH-1 downto 0);
+				signal sub2_s            : std_logic_vector(DATA_WIDTH-1 downto 0);
+				signal data_fbk          : std_logic_vector(DATA_WIDTH-1 downto 0);
+
+begin
+
+				process(aclk)
+				begin
+								if rising_edge(aclk) then
+												if aresetn = '0' then
+																k_reg   <= (others => '0');     
+																d0_reg  <= (others => '0');     
+																d11_reg <= (others => '0');     
+																d12_reg <= (others => '0');     
+																d21_reg <= (others => '0');     
+																d22_reg <= (others => '0');     
+																d31_reg <= (others => '0');     
+																d32_reg <= (others => '0');     
+																d4_reg  <= (others => '0');     
+												else
+																k_reg   <= k_next;
+																d0_reg  <= d0_next;
+																d11_reg <= d11_next;
+																d12_reg <= d12_next;
+																d21_reg <= d21_next;
+																d22_reg <= d22_next;
+																d31_reg <= d31_next;
+																d32_reg <= d32_next;
+																d4_reg  <= d4_next;
+												end if;
+								end if;
+				end process;
+
+				k_next <= k_i;
+
+				d0_next <= data_i;
+
+				d11_next <= d0_reg;
+
+				sub_s <= std_logic_vector(signed(d0_reg) - signed(data_fbk));
+
+				d12_next <= sub_s; 
+
+				d21_next <= d11_reg; 
+
+				mult_s <= std_logic_vector(signed(k_reg) * signed(d12_reg));
+
+				d22_next <= mult_s;
+
+				d31_next <= d21_reg; 
+
+				d32_next <= std_logic_vector(signed(d32_reg) + signed(d22_reg));
+
+				data_fbk <= d32_reg(2*DATA_WIDTH-1 downto DATA_WIDTH);
+
+				sub2_s <= std_logic_vector(signed(d31_reg) - signed(data_fbk));
+
+				d4_next <= sub2_s;
+
+				data_o <= d4_reg;
+
+end rtl;     
diff --git a/cores/port_slicer_v1_0/core_config.tcl b/cores/port_slicer_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..500225d0f778825d4f6890f40ac162dd54804489
--- /dev/null
+++ b/cores/port_slicer_v1_0/core_config.tcl
@@ -0,0 +1,10 @@
+set display_name {Port Slicer}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter DIN_WIDTH {DIN WIDTH} {Width of the input port.}
+core_parameter DIN_FROM {DIN FROM} {Index of the highest selected bit.}
+core_parameter DIN_TO {DIN TO} {Index of the lowest selected bit.}
diff --git a/cores/port_slicer_v1_0/port_slicer.vhd b/cores/port_slicer_v1_0/port_slicer.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..b0159258a79f0c5bb90bac1f08283d151a16aadb
--- /dev/null
+++ b/cores/port_slicer_v1_0/port_slicer.vhd
@@ -0,0 +1,23 @@
+library ieee;
+  
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity port_slicer is
+generic(
+  DIN_WIDTH : integer := 32;
+  DIN_FROM  : integer := 31;
+  DIN_TO    : integer := 0
+);
+port (
+  din     : in std_logic_vector(DIN_WIDTH-1 downto 0);
+  dout    : out std_logic_vector(DIN_FROM-DIN_TO downto 0)
+  );
+end port_slicer;
+
+architecture rtl of port_slicer is
+
+begin
+  dout <= din(DIN_FROM downto DIN_TO);
+
+end rtl;
diff --git a/cores/pps_gen_v1_0/core_config.tcl b/cores/pps_gen_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ecd0ba753672bdd7b6a6a0a9c8f41506a8fcf697
--- /dev/null
+++ b/cores/pps_gen_v1_0/core_config.tcl
@@ -0,0 +1,7 @@
+set display_name {LAGO PPS Generator}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
diff --git a/cores/pps_gen_v1_0/pps_gen.vhd b/cores/pps_gen_v1_0/pps_gen.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..6e479166e6c0c33f11b61d8e73e349a5df1e6ad5
--- /dev/null
+++ b/cores/pps_gen_v1_0/pps_gen.vhd
@@ -0,0 +1,131 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity pps_gen is
+generic (
+  CLK_FREQ : natural := 125000000
+);
+port (
+  -- System signals
+  aclk               : in std_logic;
+  aresetn            : in std_logic;
+
+  pps_i              : in  std_logic; -- GPS PPS input
+  gpsen_i            : in  std_logic; -- PPS enable 0 -> GPS, 1 -> False PPS 
+  pps_o              : out std_logic;
+  clk_cnt_pps_o      : out std_logic_vector(27-1 downto 0);
+  pps_gps_led_o      : out std_logic;
+  false_pps_led_o    : out std_logic;
+  int_o              : out std_logic
+);
+end pps_gen;
+
+architecture rtl of pps_gen is
+
+  --PPS related signals
+  -- clock counter in a second
+  signal one_sec_cnt: std_logic_vector(27-1 downto 0);      
+  -- counter for clock pulses between PPS, it goes to zero at every PPS pulse 
+  signal clk_cnt_pps : std_logic_vector(27-1 downto 0); 
+  signal pps         : std_logic;
+  signal false_pps   : std_logic := '0';
+
+  type pps_st_t is (ZERO, EDGE, ONE);
+  signal pps_st_reg, pps_st_next: pps_st_t;
+  signal one_clk_pps       : std_logic;
+  signal pps_ibuf          : std_logic;
+
+begin
+    
+  int_o <= one_clk_pps;
+ 
+  IBUF_inst : IBUF
+   port map (
+    O => pps_ibuf,
+    I => pps_i
+   );
+
+  pps_gps_led_o <= pps_ibuf when (gpsen_i = '0') else '0';
+
+  false_pps_led_o <=  false_pps when (gpsen_i = '1') else '0';
+
+  --PPS MUX 
+  pps             <=  false_pps when (gpsen_i = '1') else pps_ibuf;
+
+  pps_o           <= one_clk_pps;
+  clk_cnt_pps_o   <= clk_cnt_pps;
+
+  -- false PPS
+  process(aclk)
+  begin
+    if (rising_edge(aclk)) then
+      if (aresetn = '0') then
+        one_sec_cnt <= (others => '0');   
+        clk_cnt_pps <= (others => '0');   
+      else
+        if (unsigned(one_sec_cnt) = CLK_FREQ-1) then
+          one_sec_cnt <= (others => '0');
+        else
+          one_sec_cnt <= std_logic_vector(unsigned(one_sec_cnt) + 1);
+        end if;
+       
+        -- false PPS is UP for 200 ms
+        if (unsigned(one_sec_cnt) < CLK_FREQ/5) then
+          false_pps <= '1';
+        else
+          false_pps <= '0';
+        end if;
+        
+        if (one_clk_pps = '1') then 
+          clk_cnt_pps <=  (others => '0');
+        else
+          clk_cnt_pps <= std_logic_vector(unsigned(clk_cnt_pps) + 1);
+        end if;
+
+      end if;
+    end if;
+  end process;
+
+  -- edge detector
+  -- state register
+  process(aclk)
+  begin
+    if (rising_edge(aclk)) then
+    if (aresetn = '0') then
+        pps_st_reg <= ZERO;
+    else
+        pps_st_reg <= pps_st_next;
+    end if;
+    end if;
+  end process;
+
+  -- next-state/output logic
+  process(pps_st_reg, pps)
+  begin
+     pps_st_next <= pps_st_reg;
+     one_clk_pps <= '0';
+     case pps_st_reg is
+        when ZERO =>
+           if pps = '1' then
+              pps_st_next <= EDGE;
+           end if;
+        when EDGE =>
+           one_clk_pps <= '1';
+           if pps = '1' then
+              pps_st_next <= ONE;
+           else
+              pps_st_next <= ZERO;
+           end if;
+        when ONE =>
+           if pps = '0' then
+              pps_st_next <= ZERO;
+           end if;
+     end case;
+  end process;
+
+end architecture rtl;
diff --git a/cores/pps_gen_v1_1/core_config.tcl b/cores/pps_gen_v1_1/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ac7b403ebaaf2e92e60e397f4f07680452ad86bf
--- /dev/null
+++ b/cores/pps_gen_v1_1/core_config.tcl
@@ -0,0 +1,7 @@
+set display_name {LAGO PPS Generator v1r1}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
diff --git a/cores/pps_gen_v1_1/pps_gen.vhd b/cores/pps_gen_v1_1/pps_gen.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..e0a411916228a0659adb0d6e0463bf8394a00e81
--- /dev/null
+++ b/cores/pps_gen_v1_1/pps_gen.vhd
@@ -0,0 +1,138 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity pps_gen is
+generic (
+  CLK_FREQ : natural := 125000000
+);
+port (
+  -- System signals
+  aclk               : in std_logic;
+  aresetn            : in std_logic;
+  resetn_i           : in std_logic;
+
+  pps_i              : in  std_logic; -- GPS PPS input
+  gpsen_i            : in  std_logic; -- PPS enable 0 -> GPS, 1 -> False PPS 
+  pps_o              : out std_logic;
+  clk_cnt_pps_o      : out std_logic_vector(27-1 downto 0);
+  pps_gps_led_o      : out std_logic;
+  false_pps_led_o    : out std_logic;
+  pps_sig_o          : out std_logic;
+  int_o              : out std_logic
+);
+end pps_gen;
+
+architecture rtl of pps_gen is
+
+  --PPS related signals
+  -- clock counter in a second
+  signal one_sec_cnt: std_logic_vector(27-1 downto 0);      
+  -- counter for clock pulses between PPS, it goes to zero at every PPS pulse 
+  signal clk_cnt_pps : std_logic_vector(27-1 downto 0); 
+  signal pps         : std_logic;
+  signal false_pps   : std_logic := '0';
+
+  type pps_st_t is (ZERO, EDGE, ONE);
+  signal pps_st_reg, pps_st_next: pps_st_t;
+  signal one_clk_pps       : std_logic;
+  signal pps_ibuf          : std_logic;
+  signal rst_sig           : std_logic;
+
+begin
+
+  pps_sig_o <= '1' when (((pps_ibuf = '1') and (gpsen_i = '0')) or ((false_pps = '1') and (gpsen_i = '1'))) else '0';
+
+  rst_sig <= '1' when ((aresetn = '0') or (resetn_i = '0')) else '0';
+    
+  int_o <= one_clk_pps;
+ 
+  IBUF_inst : IBUF
+   port map (
+    O => pps_ibuf,
+    I => pps_i
+   );
+
+  pps_gps_led_o <= pps_ibuf when (gpsen_i = '0') else '0';
+
+  false_pps_led_o <=  false_pps when (gpsen_i = '1') else '0';
+
+  --PPS MUX 
+  pps             <=  false_pps when (gpsen_i = '1') else pps_ibuf;
+
+  pps_o           <= one_clk_pps;
+  clk_cnt_pps_o   <= clk_cnt_pps;
+
+  -- false PPS
+  process(aclk)
+  begin
+    if (rising_edge(aclk)) then
+      if (rst_sig = '1') then
+        one_sec_cnt <= (others => '0');   
+        clk_cnt_pps <= (others => '0');   
+      else
+        if (unsigned(one_sec_cnt) = CLK_FREQ-1) then
+          one_sec_cnt <= (others => '0');
+        else
+          one_sec_cnt <= std_logic_vector(unsigned(one_sec_cnt) + 1);
+        end if;
+       
+        -- false PPS is UP for 200 ms
+        if (unsigned(one_sec_cnt) < CLK_FREQ/5) then
+          false_pps <= '1';
+        else
+          false_pps <= '0';
+        end if;
+        
+        if (one_clk_pps = '1') then 
+          clk_cnt_pps <=  (others => '0');
+        else
+          clk_cnt_pps <= std_logic_vector(unsigned(clk_cnt_pps) + 1);
+        end if;
+
+      end if;
+    end if;
+  end process;
+
+  -- edge detector
+  -- state register
+  process(aclk)
+  begin
+    if (rising_edge(aclk)) then
+    if (aresetn = '0') then
+        pps_st_reg <= ZERO;
+    else
+        pps_st_reg <= pps_st_next;
+    end if;
+    end if;
+  end process;
+
+  -- next-state/output logic
+  process(pps_st_reg, pps)
+  begin
+     pps_st_next <= pps_st_reg;
+     one_clk_pps <= '0';
+     case pps_st_reg is
+        when ZERO =>
+           if pps = '1' then
+              pps_st_next <= EDGE;
+           end if;
+        when EDGE =>
+           one_clk_pps <= '1';
+           if pps = '1' then
+              pps_st_next <= ONE;
+           else
+              pps_st_next <= ZERO;
+           end if;
+        when ONE =>
+           if pps = '0' then
+              pps_st_next <= ZERO;
+           end if;
+     end case;
+  end process;
+
+end architecture rtl;
diff --git a/cores/pwm_gen_v1_0/core_config.tcl b/cores/pwm_gen_v1_0/core_config.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f7a308e0c7fe6f1b55e075c1b9973847da4aacbe
--- /dev/null
+++ b/cores/pwm_gen_v1_0/core_config.tcl
@@ -0,0 +1,9 @@
+set display_name {PWM Signal Generator}
+
+set core [ipx::current_core]
+
+set_property DISPLAY_NAME $display_name $core
+set_property DESCRIPTION $display_name $core
+
+core_parameter DATA_WIDTH {DATA WIDTH} {Width of the data bus.}
+core_parameter MAX_CNT {MAX COUNT} {Counter maximum count.}
diff --git a/cores/pwm_gen_v1_0/pwm_gen.vhd b/cores/pwm_gen_v1_0/pwm_gen.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..30750f038de27c2cae5d5fc58afdef93312d3c18
--- /dev/null
+++ b/cores/pwm_gen_v1_0/pwm_gen.vhd
@@ -0,0 +1,64 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pwm_rp is
+generic(
+  DATA_WIDTH : integer := 24;
+  MAX_CNT : integer := 156
+);
+port (
+  aclk    : in std_logic;
+  aresetn : in std_logic;
+  cfg_i   : in std_logic_vector(DATA_WIDTH-1 downto 0);
+  pwm_o   : out std_logic
+  );
+end pwm_rp;
+
+architecture rtl of pwm_rp is
+  signal bcnt_reg, bcnt_next : std_logic_vector(4-1 downto 0);
+  signal b_reg, b_next : std_logic_vector(16-1 downto 0); 
+  signal vcnt_reg, vcnt_next: std_logic_vector(8-1 downto 0);
+  signal v_reg, v_next, v_r_reg, v_r_next : std_logic_vector(8-1 downto 0);
+
+begin
+
+process(aclk)
+begin
+if rising_edge(aclk) then
+  if aresetn = '0' then
+    vcnt_reg <= (others => '0');     
+    bcnt_reg <= (others => '0');     
+    v_reg <= (others => '0');     
+    v_r_reg <= (others => '0');     
+    b_reg <= (others => '0');     
+  else
+    vcnt_reg <= vcnt_next;
+    bcnt_reg <= bcnt_next;
+    v_reg <= v_next;
+    v_r_reg <= v_r_next;
+    b_reg <= b_next;
+  end if;
+end if;
+end process;
+
+ vcnt_next <= (others => '0') when unsigned(vcnt_reg) = MAX_CNT else
+              std_logic_vector(unsigned(vcnt_reg)+1);
+              
+ bcnt_next <= std_logic_vector(unsigned(bcnt_reg) + 1) when unsigned(vcnt_reg) = MAX_CNT else
+              bcnt_reg;
+              
+ b_next    <= cfg_i(16-1 downto 0) when (unsigned(vcnt_reg) = MAX_CNT) and (bcnt_reg = "1111") else
+              "0" & b_reg(15 downto 1) when (unsigned(vcnt_reg) = MAX_CNT) and (bcnt_reg /= "1111") else
+              b_reg;
+
+ v_next    <= cfg_i(24-1 downto 16) when (unsigned(vcnt_reg) = MAX_CNT) and (bcnt_reg = "1111") else 
+              v_reg;
+
+ v_r_next  <= std_logic_vector(unsigned(v_reg) + 1) when b_reg(0) = '1' else
+              v_reg;
+              
+ pwm_o     <= '1' when (unsigned(vcnt_reg) <= unsigned(v_r_reg)) else '0';
+
+end rtl;     
diff --git a/settings.sh b/settings.sh
new file mode 100644
index 0000000000000000000000000000000000000000..0a43e7b9f70d4d08f9c42812a9fba7b52262b96a
--- /dev/null
+++ b/settings.sh
@@ -0,0 +1,40 @@
+export LC_CTYPE="en_US.UTF-8" 
+export LC_NUMERIC="en_US.UTF-8"
+
+export LC_TIME="en_US.UTF-8" 
+export LC_COLLATE="en_US.UTF-8" 
+export LC_MONETARY="en_US.UTF-8" 
+export LC_MESSAGES="en_US.UTF-8" 
+export LC_PAPER="en_US.UTF-8" 
+export LC_NAME="en_US.UTF-8" 
+export LC_ADDRESS="en_US.UTF-8" 
+export LC_TELEPHONE="en_US.UTF-8" 
+export LC_MEASUREMENT="en_US.UTF-8" 
+export LC_IDENTIFICATION="en_US.UTF-8" 
+export LC_ALL="en_US.UTF-8"
+################################################################################
+# setup Xilinx Vivado FPGA tools
+################################################################################
+
+. /tools/Xilinx/SDK/2018.3/settings64.sh
+#. /tools/Xilinx/Vivado/2018.3/settings64.sh
+#. /tools/Xilinx/Vivado/2019.2/settings64.sh
+
+################################################################################
+# setup cross compiler toolchain
+################################################################################
+
+export CROSS_COMPILE=arm-linux-gnueabihf-
+
+################################################################################
+# setup download cache directory, to avoid downloads
+################################################################################
+
+#export DL=dl
+
+################################################################################
+# common make procedure, should not be run by this script
+################################################################################
+
+#GIT_COMMIT_SHORT=`git rev-parse --short HEAD`
+#make REVISION=$GIT_COMMIT_SHORT
diff --git a/uEnv-ext4.txt b/uEnv-ext4.txt
new file mode 100644
index 0000000000000000000000000000000000000000..a063b3e09014bbd917a156a8b464a3b1729903d4
--- /dev/null
+++ b/uEnv-ext4.txt
@@ -0,0 +1,13 @@
+
+kernel_image=uImage
+
+devicetree_image=devicetree.dtb
+
+kernel_load_address=0x2080000
+
+devicetree_load_address=0x2000000
+
+bootcmd=fatload mmc 0 ${kernel_load_address} ${kernel_image} && fatload mmc 0 ${devicetree_load_address} ${devicetree_image} && bootm ${kernel_load_address} - ${devicetree_load_address}
+
+bootargs=console=ttyPS0,115200 uio_pdrv_genirq.of_id=generic-uio root=/dev/mmcblk0p2 ro rootfstype=ext4 earlyprintk rootwait
+
diff --git a/uEnv.txt b/uEnv.txt
new file mode 100644
index 0000000000000000000000000000000000000000..0680df09760d730c201da902a4222c929c92f59e
--- /dev/null
+++ b/uEnv.txt
@@ -0,0 +1,15 @@
+kernel_image=uImage
+
+devicetree_image=devicetree.dtb
+
+ramdisk_image=uInitrd
+
+kernel_load_address=0x2080000
+
+devicetree_load_address=0x2000000
+
+ramdisk_load_address=0x3000000
+
+bootcmd=fatload mmc 0 ${kernel_load_address} ${kernel_image} && fatload mmc 0 ${devicetree_load_address} ${devicetree_image} && load mmc 0 ${ramdisk_load_address} ${ramdisk_image} && bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}
+
+bootargs=console=ttyPS0,115200 earlyprintk modloop=modloop cma=36M