From 96b4b7f57ce7e8b7d527adb5831b719bdd761366 Mon Sep 17 00:00:00 2001
From: lharnaldi <lharnaldi@gmail.com>
Date: Thu, 21 Jun 2018 17:59:32 -0300
Subject: [PATCH] First commit of this repository.
---
GPSNFIFO.FMT | 1123 ++++
GPSNFIFO.VHD | 274 +
GPS_n_fifo.vhd | 441 ++
HP03_par_control.vhd | 347 +
HP_LAGO.FMT | 735 +++
HP_LAGO.VHD | 274 +
Makefile | 94 +
baseline.vhd | 142 +
baseline_control.prj | 1 +
baseline_control.xst | 5 +
bbfifo_16x8.vhd | 281 +
clk_40mhz.v | 66 +
clock_divider.v | 64 +
dcm_200mhz.v | 92 +
interfaz_spi.prj | 1 +
interfaz_spi.vhd | 214 +
interfaz_spi.xst | 5 +
ipcore_dir/DCM_33.v | 77 +
ipcore_dir/DCM_33.vhd | 96 +
ipcore_dir/DCM_33.xaw | 3 +
ipcore_dir/DCM_33_arwz.ucf | 17 +
ipcore_dir/DCM_33_flist.txt | 4 +
ipcore_dir/DCM_33_readme.txt | 19 +
ipcore_dir/DCM_33_xmdf.tcl | 48 +
ipcore_dir/_xmsgs/cg.xmsgs | 21 +
ipcore_dir/_xmsgs/pn_parser.xmsgs | 15 +
ipcore_dir/coregen.cgc | 167 +
ipcore_dir/coregen.cgp | 9 +
ipcore_dir/coregen.log | 63 +
ipcore_dir/coregen.rsp | 2 +
ipcore_dir/edit_fifo.tcl | 37 +
ipcore_dir/fifo.asy | 45 +
ipcore_dir/fifo.gise | 33 +
ipcore_dir/fifo.ncf | 0
ipcore_dir/fifo.ngc | 3 +
ipcore_dir/fifo.sym | 39 +
ipcore_dir/fifo.v | 175 +
ipcore_dir/fifo.veo | 52 +
ipcore_dir/fifo.vhd | 178 +
ipcore_dir/fifo.vho | 97 +
ipcore_dir/fifo.xco | 91 +
ipcore_dir/fifo.xco.bak | 84 +
ipcore_dir/fifo.xise | 386 ++
ipcore_dir/fifo_flist.txt | 14 +
ipcore_dir/fifo_generator_readme.txt | 165 +
ipcore_dir/fifo_generator_ug175.pdf | Bin 0 -> 8003 bytes
.../HierarchicalDesign/HDProject/HDProject | Bin 0 -> 251 bytes
.../HDProject/HDProject_StrTbl | Bin 0 -> 88 bytes
.../__stored_object_table__ | Bin 0 -> 60 bytes
.../PnAutoRun/Scripts/RunOnce_tcl | Bin 0 -> 27 bytes
.../PnAutoRun/Scripts/RunOnce_tcl_StrTbl | Bin 0 -> 3817 bytes
.../dpm_project_main/dpm_project_main | Bin 0 -> 25 bytes
.../dpm_project_main/dpm_project_main_StrTbl | Bin 0 -> 10 bytes
.../tmp/ise/__REGISTRY__/Autonym/regkeys | 0
.../HierarchicalDesign/HDProject/regkeys | 24 +
.../ise/__REGISTRY__/ProjectNavigator/regkeys | 3 +
.../__REGISTRY__/ProjectNavigator11/regkeys | 6 +
.../tmp/ise/__REGISTRY__/XSLTProcess/regkeys | 3 +
.../__REGISTRY__/_ProjRepoInternal_/regkeys | 21 +
.../tmp/ise/__REGISTRY__/bitgen/regkeys | 3 +
.../tmp/ise/__REGISTRY__/bitinit/regkeys | 3 +
.../tmp/ise/__REGISTRY__/common/regkeys | 15 +
.../tmp/ise/__REGISTRY__/cpldfit/regkeys | 3 +
.../tmp/ise/__REGISTRY__/dumpngdio/regkeys | 3 +
.../tmp/ise/__REGISTRY__/fuse/regkeys | 3 +
.../tmp/ise/__REGISTRY__/hprep6/regkeys | 3 +
.../tmp/ise/__REGISTRY__/idem/regkeys | 3 +
.../tmp/ise/__REGISTRY__/libgen/regkeys | 3 +
.../tmp/ise/__REGISTRY__/map/regkeys | 3 +
.../tmp/ise/__REGISTRY__/netgen/regkeys | 3 +
.../tmp/ise/__REGISTRY__/ngc2edif/regkeys | 3 +
.../tmp/ise/__REGISTRY__/ngcbuild/regkeys | 3 +
.../tmp/ise/__REGISTRY__/ngdbuild/regkeys | 3 +
.../tmp/ise/__REGISTRY__/par/regkeys | 3 +
.../tmp/ise/__REGISTRY__/platgen/regkeys | 3 +
.../tmp/ise/__REGISTRY__/runner/regkeys | 3 +
.../tmp/ise/__REGISTRY__/simgen/regkeys | 3 +
.../tmp/ise/__REGISTRY__/taengine/regkeys | 3 +
.../tmp/ise/__REGISTRY__/trce/regkeys | 3 +
.../tmp/ise/__REGISTRY__/tsim/regkeys | 3 +
.../tmp/ise/__REGISTRY__/vhpcomp/regkeys | 3 +
.../tmp/ise/__REGISTRY__/vlogcomp/regkeys | 3 +
.../tmp/ise/__REGISTRY__/xpwr/regkeys | 3 +
.../tmp/ise/__REGISTRY__/xst/regkeys | 3 +
ipcore_dir/fifo_usb_if_xdb/tmp/ise/version | 10 +
ipcore_dir/fifo_xmdf.tcl | 79 +
ipcore_dir/iseconfig/fifo_usb_if.projectmgr | 103 +
.../ISimEngine-DesignHierarchy.dbg | Bin 0 -> 35628 bytes
.../fifo_usb_if_isim_beh.exe | Bin 0 -> 303008 bytes
.../isimcrash.log | 0
.../isimkernel.log | 29 +
.../libPortability.dll | Bin 0 -> 1033728 bytes
.../fifo_usb_if_isim_beh.exe.sim/netId.dat | Bin 0 -> 92 bytes
.../fifo_usb_if_isim_beh.exe.sim/tmp_save/_1 | Bin 0 -> 18697 bytes
.../work/a_1176593161_2718564866.c | 31 +
.../work/a_1176593161_2718564866.didat | Bin 0 -> 9520 bytes
.../work/a_1176593161_2718564866.nt64.obj | Bin 0 -> 679 bytes
.../work/fifo_usb_if_isim_beh.exe_main.c | 48 +
.../fifo_usb_if_isim_beh.exe_main.nt64.obj | Bin 0 -> 2092 bytes
.../xilinxcorelib/a_1848741551_3212880686.c | 1090 ++++
.../a_1848741551_3212880686.didat | Bin 0 -> 31612 bytes
.../a_1848741551_3212880686.nt64.obj | Bin 0 -> 5937 bytes
.../xilinxcorelib/a_3173924170_3212880686.c | 2229 +++++++
.../a_3173924170_3212880686.didat | Bin 0 -> 13772 bytes
.../a_3173924170_3212880686.nt64.obj | Bin 0 -> 17809 bytes
.../xilinxcorelib/a_4048593843_3212880686.c | 5654 +++++++++++++++++
.../a_4048593843_3212880686.didat | Bin 0 -> 30484 bytes
.../a_4048593843_3212880686.nt64.obj | Bin 0 -> 32216 bytes
ipcore_dir/isim/isim_usage_statistics.html | 16 +
.../ieee/p_0017514958.didat | Bin 0 -> 3620 bytes
.../ieee/p_0774719531.didat | Bin 0 -> 2120 bytes
.../ieee/p_1242562249.didat | Bin 0 -> 8376 bytes
.../ieee/p_1367372525.didat | Bin 0 -> 15964 bytes
.../ieee/p_2592010699.didat | Bin 0 -> 5664 bytes
.../ieee/p_2717149903.didat | Bin 0 -> 12072 bytes
.../ieee/p_3039841270.didat | Bin 0 -> 5400 bytes
.../ieee/p_3499444699.didat | Bin 0 -> 4232 bytes
.../ieee/p_3564397177.didat | Bin 0 -> 4624 bytes
.../ieee/p_3620187407.didat | Bin 0 -> 2232 bytes
.../ieee/p_3972351953.didat | Bin 0 -> 8004 bytes
.../ieee/p_4165608084.didat | Bin 0 -> 4604 bytes
.../isim/precompiled.exe.sim/std/textio.didat | Bin 0 -> 2368 bytes
ipcore_dir/isim/temp/fifo_usb_if.vdb | Bin 0 -> 8343 bytes
ipcore_dir/isim/work/fifo_usb_if.vdb | Bin 0 -> 8338 bytes
ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs | 9 +
ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs | 15 +
ipcore_dir/tmp/_xmsgs/xst.xmsgs | 2274 +++++++
ipcore_dir/xaw2verilog.log | 1 +
ipcore_dir/xaw2vhdl.log | 1 +
kcpsm3.vhd | 1901 ++++++
kcuart_rx.vhd | 352 +
kcuart_tx.vhd | 394 ++
lago_fpga_vhdl.prj | 19 +
lago_fpga_vhdl.ucf | 179 +
lago_fpga_vhdl.vhd | 578 ++
lago_fpga_vhdl.vhd_orig | 699 ++
lago_fpga_vhdl.xise | 404 ++
lago_fpga_vhdl.xst | 57 +
lago_fpga_vhdl_1200.ucf | 183 +
nexys2_1200.batch | 6 +
nexys2_500.batch | 7 +
rampa_hv.vhd | 107 +
spi_dac.vhd | 178 +
trigger.vhd | 455 ++
uart_rx.vhd | 146 +
uart_tx.vhd | 148 +
usb_if_ctrl.vhd | 1144 ++++
147 files changed, 24789 insertions(+)
create mode 100644 GPSNFIFO.FMT
create mode 100755 GPSNFIFO.VHD
create mode 100644 GPS_n_fifo.vhd
create mode 100644 HP03_par_control.vhd
create mode 100644 HP_LAGO.FMT
create mode 100755 HP_LAGO.VHD
create mode 100755 Makefile
create mode 100644 baseline.vhd
create mode 100644 baseline_control.prj
create mode 100644 baseline_control.xst
create mode 100644 bbfifo_16x8.vhd
create mode 100755 clk_40mhz.v
create mode 100755 clock_divider.v
create mode 100755 dcm_200mhz.v
create mode 100644 interfaz_spi.prj
create mode 100644 interfaz_spi.vhd
create mode 100644 interfaz_spi.xst
create mode 100755 ipcore_dir/DCM_33.v
create mode 100755 ipcore_dir/DCM_33.vhd
create mode 100755 ipcore_dir/DCM_33.xaw
create mode 100755 ipcore_dir/DCM_33_arwz.ucf
create mode 100755 ipcore_dir/DCM_33_flist.txt
create mode 100755 ipcore_dir/DCM_33_readme.txt
create mode 100755 ipcore_dir/DCM_33_xmdf.tcl
create mode 100644 ipcore_dir/_xmsgs/cg.xmsgs
create mode 100644 ipcore_dir/_xmsgs/pn_parser.xmsgs
create mode 100644 ipcore_dir/coregen.cgc
create mode 100644 ipcore_dir/coregen.cgp
create mode 100644 ipcore_dir/coregen.log
create mode 100755 ipcore_dir/coregen.rsp
create mode 100644 ipcore_dir/edit_fifo.tcl
create mode 100644 ipcore_dir/fifo.asy
create mode 100644 ipcore_dir/fifo.gise
create mode 100644 ipcore_dir/fifo.ncf
create mode 100644 ipcore_dir/fifo.ngc
create mode 100644 ipcore_dir/fifo.sym
create mode 100644 ipcore_dir/fifo.v
create mode 100644 ipcore_dir/fifo.veo
create mode 100644 ipcore_dir/fifo.vhd
create mode 100644 ipcore_dir/fifo.vho
create mode 100644 ipcore_dir/fifo.xco
create mode 100644 ipcore_dir/fifo.xco.bak
create mode 100644 ipcore_dir/fifo.xise
create mode 100644 ipcore_dir/fifo_flist.txt
create mode 100644 ipcore_dir/fifo_generator_readme.txt
create mode 100644 ipcore_dir/fifo_generator_ug175.pdf
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/HDProject/HDProject_StrTbl
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/HierarchicalDesign/__stored_object_table__
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/PnAutoRun/Scripts/RunOnce_tcl_StrTbl
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/common/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/fuse/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/idem/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/libgen/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/map/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/netgen/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/par/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/platgen/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/runner/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/simgen/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/taengine/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/trce/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/tsim/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/xst/regkeys
create mode 100755 ipcore_dir/fifo_usb_if_xdb/tmp/ise/version
create mode 100644 ipcore_dir/fifo_xmdf.tcl
create mode 100755 ipcore_dir/iseconfig/fifo_usb_if.projectmgr
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/fifo_usb_if_isim_beh.exe
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/isimcrash.log
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/isimkernel.log
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/libPortability.dll
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/netId.dat
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/tmp_save/_1
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.c
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.didat
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.nt64.obj
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/fifo_usb_if_isim_beh.exe_main.c
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/fifo_usb_if_isim_beh.exe_main.nt64.obj
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_1848741551_3212880686.c
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_1848741551_3212880686.didat
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_1848741551_3212880686.nt64.obj
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.c
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.didat
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.nt64.obj
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.c
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.didat
create mode 100755 ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.nt64.obj
create mode 100755 ipcore_dir/isim/isim_usage_statistics.html
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_0017514958.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_0774719531.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_1242562249.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_1367372525.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_2592010699.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_2717149903.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_3039841270.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_3499444699.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_3564397177.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_3620187407.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_3972351953.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/ieee/p_4165608084.didat
create mode 100755 ipcore_dir/isim/precompiled.exe.sim/std/textio.didat
create mode 100755 ipcore_dir/isim/temp/fifo_usb_if.vdb
create mode 100755 ipcore_dir/isim/work/fifo_usb_if.vdb
create mode 100644 ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs
create mode 100644 ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
create mode 100644 ipcore_dir/tmp/_xmsgs/xst.xmsgs
create mode 100755 ipcore_dir/xaw2verilog.log
create mode 100755 ipcore_dir/xaw2vhdl.log
create mode 100644 kcpsm3.vhd
create mode 100644 kcuart_rx.vhd
create mode 100644 kcuart_tx.vhd
create mode 100644 lago_fpga_vhdl.prj
create mode 100755 lago_fpga_vhdl.ucf
create mode 100644 lago_fpga_vhdl.vhd
create mode 100644 lago_fpga_vhdl.vhd_orig
create mode 100755 lago_fpga_vhdl.xise
create mode 100644 lago_fpga_vhdl.xst
create mode 100755 lago_fpga_vhdl_1200.ucf
create mode 100644 nexys2_1200.batch
create mode 100644 nexys2_500.batch
create mode 100644 rampa_hv.vhd
create mode 100644 spi_dac.vhd
create mode 100644 trigger.vhd
create mode 100644 uart_rx.vhd
create mode 100644 uart_tx.vhd
create mode 100644 usb_if_ctrl.vhd
diff --git a/GPSNFIFO.FMT b/GPSNFIFO.FMT
new file mode 100644
index 0000000..e7c0fd4
--- /dev/null
+++ b/GPSNFIFO.FMT
@@ -0,0 +1,1123 @@
+ ;**************************************************************
+ ;Copyright (c) 2011
+ ;Title: GPS_Oncore_ctrl
+ ;Current version: v1r1
+ ;Function: Control for Oncore GPS receiver to function together
+ ; with new electronics from Lago Project.
+ ; It comunicates whit GPS receiver at 9600 bps and
+ ; writes external registers.
+ ;
+ ;Core: KCPSM3 (Spartan3E version)
+ ;Clock: 50MHz Crystal (Nexys2 clock)
+ ;Author: Horacio Arnaldi
+ ;Company: CAB - IB (CNEA)
+ ;Contact: (+54)-2944-445500
+ ;e-mail: lharnaldi@cab.cnea.gov.ar
+ ;Date: 2011-09-18
+ ;
+ ;**************************************************************
+ ;**************************************************************
+ ; Port definitions
+ ;**************************************************************
+ ;
+ ;
+ ;
+ CONSTANT status_port, 40 ;UART and USB status input
+ CONSTANT tx_half_full, 01 ; Transmitter half full - bit0
+ CONSTANT tx_full, 02 ; FIFO full - bit1
+ CONSTANT rx_data_present, 04 ; Receiver data present - bit2
+ CONSTANT rx_half_full, 08 ; FIFO half full - bit3
+ CONSTANT rx_full, 10 ; full - bit4
+ CONSTANT tx_usb_empty, 20 ; USB FIFO status port bit5
+ CONSTANT tx_usb_full, 40 ; bit6
+ CONSTANT spare, 80 ; - bit7
+ ;
+ ;Ports to write data acquired from GPS receiver
+ CONSTANT month_port, 00
+ CONSTANT day_port, 01
+ CONSTANT year1_port, 02
+ CONSTANT year2_port, 03
+ CONSTANT hours_port, 04
+ CONSTANT minutes_port, 05
+ CONSTANT seconds_port, 06
+ CONSTANT fract_sec1_port, 07
+ CONSTANT fract_sec2_port, 08
+ CONSTANT fract_sec3_port, 09
+ CONSTANT fract_sec4_port, 0A
+ CONSTANT latitude1_port, 0B
+ CONSTANT latitude2_port, 0C
+ CONSTANT latitude3_port, 0D
+ CONSTANT latitude4_port, 0E
+ CONSTANT longitude1_port, 0F
+ CONSTANT longitude2_port, 10
+ CONSTANT longitude3_port, 11
+ CONSTANT longitude4_port, 12
+ CONSTANT ellipsoid1_port, 13
+ CONSTANT ellipsoid2_port, 14
+ CONSTANT ellipsoid3_port, 15
+ CONSTANT ellipsoid4_port, 16
+ CONSTANT velocity1_port, 17
+ CONSTANT velocity2_port, 18
+ CONSTANT heading1_port, 19
+ CONSTANT heading2_port, 1A
+ CONSTANT geometry2_port, 1B
+ CONSTANT DOP_type_port, 1C
+ CONSTANT num_vis_sat_port, 1D
+ CONSTANT num_track_sat_port, 1E
+ CONSTANT sat_ID1_port, 1F ; Sat ID
+ CONSTANT chtm1_port, 20 ; Channel tracking mode
+ CONSTANT CNo1_port, 21 ; Carrier to noise density ratio
+ CONSTANT chsf1_port, 22 ; Channel status flag
+ CONSTANT sat_ID2_port, 23 ; Sat ID
+ CONSTANT chtm2_port, 24 ; Channel tracking mode
+ CONSTANT CNo2_port, 25 ; Carrier to noise density ratio
+ CONSTANT chsf2_port, 26 ; Channel status flag
+ CONSTANT sat_ID3_port, 27 ; Sat ID
+ CONSTANT chtm3_port, 28 ; Channel tracking mode
+ CONSTANT CNo3_port, 29 ; Carrier to noise density ratio
+ CONSTANT chsf3_port, 2A ; Channel status flag
+ CONSTANT sat_ID4_port, 2B ; Sat ID
+ CONSTANT chtm4_port, 2C ; Channel tracking mode
+ CONSTANT CNo4_port, 2D ; Carrier to noise density ratio
+ CONSTANT chsf4_port, 2E ; Channel status flag
+ CONSTANT sat_ID5_port, 2F ; Sat ID
+ CONSTANT chtm5_port, 30 ; Channel tracking mode
+ CONSTANT CNo5_port, 31 ; Carrier to noise density ratio
+ CONSTANT chsf5_port, 32 ; Channel status flag
+ CONSTANT sat_ID6_port, 33 ; Sat ID
+ CONSTANT chtm6_port, 34 ; Channel tracking mode
+ CONSTANT CNo6_port, 35 ; Carrier to noise density ratio
+ CONSTANT chsf6_port, 36 ; Channel status flag
+ CONSTANT sat_ID7_port, 37 ; Sat ID
+ CONSTANT chtm7_port, 38 ; Channel tracking mode
+ CONSTANT CNo7_port, 39 ; Carrier to noise density ratio
+ CONSTANT chsf7_port, 3A ; Channel status flag
+ CONSTANT sat_ID8_port, 3B ; Sat ID
+ CONSTANT chtm8_port, 3C ; Channel tracking mode
+ CONSTANT CNo8_port, 3D ; Carrier to noise density ratio
+ CONSTANT chsf8_port, 3E ; Channel status flag
+ CONSTANT rsf_port, 3F ; Reciver status flag
+ ;
+ CONSTANT UART_read_port, 80 ;UART Rx data input
+ ;
+ CONSTANT UART_write_port, C0 ;UART Tx data output
+ ;
+ ;CONSTANT USB_write_port, 40
+ ;
+ ;
+ ;***************************************************************
+ ;data constants
+ ;***************************************************************
+ ;
+ CONSTANT delay_1us_constant, 0B
+ ;
+ CONSTANT CMD_MASK, E0
+ CONSTANT STATUS_MASK, 1F
+ CONSTANT CLR_XCLR_MASK, FB
+ ;
+ ;
+ ;**************************************************************************************
+ ; Special Register usage
+ ;**************************************************************************************
+ ;
+ NAMEREG sF, UART_data ;used to pass data to and from the UART
+ NAMEREG s5, USB_data ;used to pass data to the USB
+ NAMEREG s6, USB_port ;used to pass data to the USB
+ ;
+ ;
+ ;
+ ;**************************************************************************************
+ ;Scratch Pad Memory Locations
+ ;**************************************************************************************
+ ;
+ ;Values read from receiver
+ ;
+ CONSTANT month, 00
+ CONSTANT day, 01
+ CONSTANT year1, 02
+ CONSTANT year2, 03
+ CONSTANT hours, 04
+ CONSTANT minutes, 05
+ CONSTANT seconds, 06
+ CONSTANT fract_sec1, 07
+ CONSTANT fract_sec2, 08
+ CONSTANT fract_sec3, 09
+ CONSTANT fract_sec4, 0A
+ CONSTANT latitude1, 0B
+ CONSTANT latitude2, 0C
+ CONSTANT latitude3, 0D
+ CONSTANT latitude4, 0E
+ CONSTANT longitude1, 0F
+ CONSTANT longitude2, 10
+ CONSTANT longitude3, 11
+ CONSTANT longitude4, 12
+ CONSTANT ellipsoid1, 13
+ CONSTANT ellipsoid2, 14
+ CONSTANT ellipsoid3, 15
+ CONSTANT ellipsoid4, 16
+ CONSTANT velocity1, 17
+ CONSTANT velocity2, 18
+ CONSTANT heading1, 19
+ CONSTANT heading2, 1A
+ CONSTANT geometry2, 1B
+ CONSTANT DOP_type, 1C
+ CONSTANT num_vis_sat, 1D
+ CONSTANT num_track_sat, 1E
+ CONSTANT sat_ID1, 1F ; Sat ID
+ CONSTANT chtm1, 20 ; Channel tracking mode
+ CONSTANT CNo1, 21 ; Carrier to noise density ratio
+ CONSTANT chsf1, 22 ; Channel status flag
+ CONSTANT sat_ID2, 23 ; Sat ID
+ CONSTANT chtm2, 24 ; Channel tracking mode
+ CONSTANT CNo2, 25 ; Carrier to noise density ratio
+ CONSTANT chsf2, 26 ; Channel status flag
+ CONSTANT sat_ID3, 27 ; Sat ID
+ CONSTANT chtm3, 28 ; Channel tracking mode
+ CONSTANT CNo3, 29 ; Carrier to noise density ratio
+ CONSTANT chsf3, 2A ; Channel status flag
+ CONSTANT sat_ID4, 2B ; Sat ID
+ CONSTANT chtm4, 2C ; Channel tracking mode
+ CONSTANT CNo4, 2D ; Carrier to noise density ratio
+ CONSTANT chsf4, 2E ; Channel status flag
+ CONSTANT sat_ID5, 2F ; Sat ID
+ CONSTANT chtm5, 30 ; Channel tracking mode
+ CONSTANT CNo5, 31 ; Carrier to noise density ratio
+ CONSTANT chsf5, 32 ; Channel status flag
+ CONSTANT sat_ID6, 33 ; Sat ID
+ CONSTANT chtm6, 34 ; Channel tracking mode
+ CONSTANT CNo6, 35 ; Carrier to noise density ratio
+ CONSTANT chsf6, 36 ; Channel status flag
+ CONSTANT sat_ID7, 37 ; Sat ID
+ CONSTANT chtm7, 38 ; Channel tracking mode
+ CONSTANT CNo7, 39 ; Carrier to noise density ratio
+ CONSTANT chsf7, 3A ; Channel status flag
+ CONSTANT sat_ID8, 3B ; Sat ID
+ CONSTANT chtm8, 3C ; Channel tracking mode
+ CONSTANT CNo8, 3D ; Carrier to noise density ratio
+ CONSTANT chsf8, 3E ; Channel status flag
+ CONSTANT rsf, 3F ; Reciver status flag
+ ;
+ ;
+ ;**************************************************************************************
+ ;Useful data constants
+ ;**************************************************************************************
+ ;
+ ;
+ ;ASCII table
+ ;
+ CONSTANT character_a, 61
+ CONSTANT character_b, 62
+ CONSTANT character_c, 63
+ CONSTANT character_d, 64
+ CONSTANT character_e, 65
+ CONSTANT character_f, 66
+ CONSTANT character_g, 67
+ CONSTANT character_h, 68
+ CONSTANT character_i, 69
+ CONSTANT character_j, 6A
+ CONSTANT character_k, 6B
+ CONSTANT character_l, 6C
+ CONSTANT character_m, 6D
+ CONSTANT character_n, 6E
+ CONSTANT character_o, 6F
+ CONSTANT character_p, 70
+ CONSTANT character_q, 71
+ CONSTANT character_r, 72
+ CONSTANT character_s, 73
+ CONSTANT character_t, 74
+ CONSTANT character_u, 75
+ CONSTANT character_v, 76
+ CONSTANT character_w, 77
+ CONSTANT character_x, 78
+ CONSTANT character_y, 79
+ CONSTANT character_z, 7A
+ CONSTANT character_A, 41
+ CONSTANT character_B, 42
+ CONSTANT character_C, 43
+ CONSTANT character_D, 44
+ CONSTANT character_E, 45
+ CONSTANT character_F, 46
+ CONSTANT character_G, 47
+ CONSTANT character_H, 48
+ CONSTANT character_I, 49
+ CONSTANT character_J, 4A
+ CONSTANT character_K, 4B
+ CONSTANT character_L, 4C
+ CONSTANT character_M, 4D
+ CONSTANT character_N, 4E
+ CONSTANT character_O, 4F
+ CONSTANT character_P, 50
+ CONSTANT character_Q, 51
+ CONSTANT character_R, 52
+ CONSTANT character_S, 53
+ CONSTANT character_T, 54
+ CONSTANT character_U, 55
+ CONSTANT character_V, 56
+ CONSTANT character_W, 57
+ CONSTANT character_X, 58
+ CONSTANT character_Y, 59
+ CONSTANT character_Z, 5A
+ CONSTANT character_0, 30
+ CONSTANT character_1, 31
+ CONSTANT character_2, 32
+ CONSTANT character_3, 33
+ CONSTANT character_4, 34
+ CONSTANT character_5, 35
+ CONSTANT character_6, 36
+ CONSTANT character_7, 37
+ CONSTANT character_8, 38
+ CONSTANT character_9, 39
+ CONSTANT character_arroba, 40 ;'@'
+ CONSTANT character_CR, 0D ;carriage return
+ CONSTANT character_LF, 0A ;line feed
+ CONSTANT character_colon, 3A
+ CONSTANT character_stop, 2E
+ CONSTANT character_semi_colon, 3B
+ CONSTANT character_minus, 2D
+ CONSTANT character_divide, 2F ;'/'
+ CONSTANT character_plus, 2B
+ CONSTANT character_comma, 2C
+ CONSTANT character_less_than, 3C
+ CONSTANT character_greater_than, 3E
+ CONSTANT character_equals, 3D
+ CONSTANT character_space, 20
+ CONSTANT character_question, 3F ;'?'
+ CONSTANT character_dollar, 24
+ CONSTANT character_exclaim, 21 ;'!'
+ CONSTANT character_BS, 08 ;Back Space command character
+ CONSTANT character_underscore, 5F ;_
+ ;
+ ;
+ ;
+ ;***************************************************************
+ ;Initialise the system
+ ;***************************************************************
+ ; Send command to set receiver to send every second status
+ ; data
+ cold_start: CALL delay_20ms ;initial delay
+ CALL delay_20ms ;5 x 20ms = 100ms
+ CALL delay_20ms
+ CALL delay_20ms ;
+ CALL delay_20ms
+ CALL mess_PSD ; Set data output for 1s
+ ; ;repetition
+ CALL mess_TRAIM ; Set 1PPS signal
+ CALL mess_PPSOFF ; Set 1PPS Offset
+ CALL mess_PPSCD ; Set 1PPS Cable Delay
+ CALL mess_PM ; Set Pulse Mode
+ CALL mess_GMTOFF ; Set GMT Offset
+ CALL mess_TM ; Set Time Mode
+ ;
+ ;
+ ;***************************************************************
+ ;main program
+ ;***************************************************************
+ ; It wait for a new data, save data into scratch pad memory
+ ; and then writes it into external FIFO if it is empty else
+ ; wait for an empty condition.
+ ;
+ loop: CALL read_char
+ COMPARE s0, character_arroba ; command init (@)
+ JUMP NZ, loop
+ CALL read_char ; read next character
+ COMPARE s0, character_arroba ; command test
+ JUMP NZ, loop
+ CALL read_char ; read next character
+ COMPARE s0, character_E ; command test
+ JUMP NZ, loop
+ CALL read_char ; read next character
+ COMPARE s0, character_a ; command test
+ JUMP NZ, loop
+ CALL read_char
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, month_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, day_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, year1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, year2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, hours_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, minutes_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, seconds_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, fract_sec1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, fract_sec2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, fract_sec3_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, fract_sec4_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, latitude1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, latitude2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, latitude3_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, latitude4_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, longitude1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, longitude2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, longitude3_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, longitude4_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, ellipsoid1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, ellipsoid2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, ellipsoid3_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, ellipsoid4_port
+ CALL USB_write
+ CALL read_char ; The nexy four characters are
+ CALL read_char ; not used, so we just read
+ CALL read_char ; them but not save.
+ CALL read_char ; read next character
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, velocity1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, velocity2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, heading1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, heading2_port
+ CALL USB_write
+ CALL read_char ; This character is disregarded
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, geometry2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, DOP_type_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, num_vis_sat_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, num_track_sat_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, sat_ID1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chtm1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, CNo1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chsf1_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, sat_ID2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chtm2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, CNo2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chsf2_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, sat_ID3_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chtm3_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, CNo3_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chsf3_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, sat_ID4_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chtm4_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, CNo4_port
+ CALL USB_write
+ CALL read_char ; read next character
+ STORE s0, chsf4 ; save data
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, sat_ID5_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chtm5_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, CNo5_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chsf5_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, sat_ID6_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chtm6_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, CNo6_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chsf6_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, sat_ID7_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chtm7_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, CNo7_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chsf7_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, sat_ID8_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chtm8_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, CNo8_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, chsf8_port
+ CALL USB_write
+ CALL read_char ; read next character
+ LOAD USB_data, s0 ; read next character
+ LOAD USB_port, rsf_port
+ CALL USB_write
+ CALL read_char ; read checksum character
+ CALL read_char ; read CR character
+ COMPARE s0, character_CR
+ JUMP NZ, loop ; return to loop if not CR
+ CALL read_char ; read LF character
+ COMPARE s0, character_LF
+ JUMP NZ, loop ; return to loop if not LF
+ JUMP loop ; Try again!
+ ;
+ ;
+ read_char: CALL read_from_UART
+ LOAD s0, UART_data
+ RETURN
+ ;
+ ;
+ USB_write: OUTPUT USB_data, (USB_port)
+ RETURN
+ ;
+ ;
+ ;
+ ;***********************************************************
+ ; Software delay Routines
+ ;***********************************************************
+ ;
+ ; Delay of 1us.
+ ;
+ ; Constant value defines reflects the clock applied to KCPSM3. Every instruction
+ ; executes in 2 clock cycles making the calculation highly predictable. The '6' in
+ ; the following equation even allows for 'CALL delay_1us' instruction in the initiating code.
+ ;
+ ; delay_1us_constant = (clock_rate - 6)/4 Where 'clock_rate' is in MHz
+ ;
+ ; Register used sA
+ ;
+ delay_1us: LOAD sA, delay_1us_constant
+ wait_1us: SUB sA, 01
+ JUMP NZ, wait_1us
+ RETURN
+ ;
+ ; Delay of 10 us
+ ;
+ ; Registers used sA, sB
+ ;
+ delay_10us: LOAD sB, 0A ;10 x 1us = 10us
+ wait_10us: CALL delay_1us
+ SUB sB, 01
+ JUMP NZ, wait_10us
+ RETURN
+ ;
+ ; Delay of 40us.
+ ;
+ ; Registers used sA, sB
+ ;
+ delay_40us: LOAD sB, 28 ;40 x 1us = 40us
+ wait_40us: CALL delay_1us
+ SUB sB, 01
+ JUMP NZ, wait_40us
+ RETURN
+ ;
+ ;
+ ; Delay of 1ms.
+ ;
+ ; Registers used sA, sB, sC
+ ;
+ delay_1ms: LOAD sC, 19 ;25 x 40us = 1ms
+ wait_1ms: CALL delay_40us
+ SUB sC, 01
+ JUMP NZ, wait_1ms
+ RETURN
+ ;
+ ; Delay of 20ms.
+ ;
+ ; Registers used sA, sB, sC, sD
+ ;
+ delay_20ms: LOAD sD, 14 ;20 x 1ms = 20ms
+ wait_20ms: CALL delay_1ms
+ SUB sD, 01
+ JUMP NZ, wait_20ms
+ RETURN
+ ;
+ ; Delay of approximately 1 second.
+ ;
+ ; Registers used sA, sB, sC, sD, sE
+ ;
+ delay_1s: LOAD sE, 14 ;50 x 20ms = 1000ms
+ wait_1s: CALL delay_20ms
+ SUB sE, 01
+ JUMP NZ, wait_1s
+ RETURN
+ ;
+ ;
+ ;
+ ;***********************************************************
+ ;UART communication routines
+ ;***********************************************************
+ ;
+ ;Read one character from the UART
+ ;
+ ;Character read will be returned in a register called 'UART_data'.
+ ;
+ ;The routine first tests the receiver FIFO buffer to see if data is present.
+ ;If the FIFO is empty, the routine waits until there is a character to read.
+ ;As this could take any amount of time the wait loop could include a call to a
+ ;subroutine which performs a useful function.
+ ;
+ ;
+ ;
+ ;Registers used s0 and UART_data
+ ;
+ read_from_UART: INPUT s0, status_port ;test Rx_FIFO buffer
+ TEST s0, rx_data_present ;wait if empty
+ JUMP NZ, read_character
+ JUMP read_from_UART
+ read_character: INPUT UART_data, UART_read_port ;read from FIFO
+ RETURN
+ ;
+ ;
+ ;
+ ;
+ ;Transmit one character to the UART
+ ;
+ ;Character supplied in register called 'UART_data'.
+ ;
+ ;The routine first tests the transmit FIFO buffer is empty.
+ ;If the FIFO currently has any data, the routine waits until it is empty.
+ ;Ultimately this means that only one character is sent at a time which
+ ;could be important if the PC at the other end of the link transmits
+ ;an XOFF and needs the flow of data to terminate as soon as possible.
+ ;
+ ;Registers used s0
+ ;
+ send_to_UART: INPUT s0, status_port ;test Tx_FIFO buffer
+ TEST s0, tx_full
+ JUMP Z, UART_write
+ JUMP send_to_UART
+ UART_write: OUTPUT UART_data, UART_write_port
+ RETURN
+ ;
+ ;Convert value provided in register s0 into ASCII characters
+ ;
+ ;The value provided must in the range 0 to 99 and will be converted into
+ ;two ASCII characters.
+ ; The number of 'tens' will be represented by an ASCII character returned in register s1.
+ ; The number of 'units' will be represented by an ASCII character returned in register s0.
+ ;
+ ;The ASCII representations of '0' to '9' are 30 to 39 hexadecimal which is simply 30 hex added to
+ ;the actual decimal value.
+ ;
+ ;Registers used s0 and s1.
+ ;
+ decimal_to_ASCII: LOAD s1, 30 ;load 'tens' counter with ASCII for '0'
+ test_for_ten: ADD s1, 01 ;increment 'tens' value
+ SUB s0, 0A ;try to subtract 10 from the supplied value
+ JUMP NC, test_for_ten ;repeat if subtraction was possible without underflow.
+ SUB s1, 01 ;'tens' value one less ten due to underflow
+ ADD s0, 3A ;restore units value (the remainder) and convert to ASCII
+ RETURN
+ ;
+ ;
+ ;
+ ;Convert character to upper case
+ ;
+ ;The character supplied in register s0.
+ ;If the character is in the range 'a' to 'z', it is converted
+ ;to the equivalent upper case character in the range 'A' to 'Z'.
+ ;All other characters remain unchanged.
+ ;
+ ;Registers used s0.
+ ;
+ upper_case: COMPARE s0, 61 ;eliminate character codes below 'a' (61 hex)
+ RETURN C
+ COMPARE s0, 7B ;eliminate character codes above 'z' (7A hex)
+ RETURN NC
+ AND s0, DF ;mask bit5 to convert to upper case
+ RETURN
+ ;
+ ;
+ ;Convert character '0' to '9' to numerical value in range 0 to 9
+ ;
+ ;The character supplied in register s0. If the character is in the
+ ;range '0' to '9', it is converted to the equivalent decimal value.
+ ;Characters not in the range '0' to '9' are signified by the return
+ ;with the CARRY flag set.
+ ;
+ ;Registers used s0.
+ ;
+ 1char_to_value: ADD s0, C6 ;reject character codes above '9' (39 hex)
+ RETURN C ;carry flag is set
+ SUB s0, F6 ;reject character codes below '0' (30 hex)
+ RETURN ;carry is set if value not in range
+ ;
+ ;
+ ;Determine the numerical value of a two character decimal string held in
+ ;scratch pad memory such the result is in the range 0 to 99 (00 to 63 hex).
+ ;
+ ;The string must be stored in two consecutive memory locations and the
+ ;location of the first (tens) character supplied in the s1 register.
+ ;The result is provided in register s2. Strings not using characters in the
+ ;range '0' to '9' are signified by the return with the CARRY flag set.
+ ;
+ ;Registers used s0, s1 and s2.
+ ;
+ 2char_to_value: FETCH s0, (s1) ;read 'tens' character
+ CALL 1char_to_value ;convert to numerical value
+ RETURN C ;bad character - CARRY set
+ LOAD s2, s0
+ SL0 s2 ;multiply 'tens' value by 10 (0A hex)
+ SL0 s2
+ ADD s2, s0
+ SL0 s2
+ ADD s1, 01 ;read 'units' character
+ FETCH s0, (s1)
+ CALL 1char_to_value ;convert to numerical value
+ RETURN C ;bad character - CARRY set
+ ADD s2, s0 ;add units to result and clear CARRY flag
+ RETURN
+ ;
+ ;
+ ;Convert hexadecimal value provided in register s0 into ASCII characters
+ ;
+ ;The value provided must be any value in the range 00 to FF and will be converted into
+ ;two ASCII characters.
+ ; The upper nibble will be represented by an ASCII character returned in register s2.
+ ; The lower nibble will be represented by an ASCII character returned in register s1.
+ ;
+ ;The ASCII representations of '0' to '9' are 30 to 39 hexadecimal which is simply 30 hex
+ ;added to the actual decimal value. The ASCII representations of 'A' to 'F' are 41 to 46
+ ;hexadecimal requiring a further addition of 07 to the 30 already added.
+ ;
+ ;Registers used s0, s1 and s2.
+ ;
+hex_byte_to_ASCII: LOAD s1, s0 ;remember value supplied
+ SR0 s0 ;isolate upper nibble
+ SR0 s0
+ SR0 s0
+ SR0 s0
+ CALL hex_to_ASCII ;convert
+ LOAD s2, s0 ;upper nibble value in s2
+ LOAD s0, s1 ;restore complete value
+ AND s0, 0F ;isolate lower nibble
+ CALL hex_to_ASCII ;convert
+ LOAD s1, s0 ;lower nibble value in s1
+ RETURN
+ ;
+ ;Convert hexadecimal value provided in register s0 into ASCII character
+ ;
+ ;Register used s0
+ ;
+ hex_to_ASCII: SUB s0, 0A ;test if value is in range 0 to 9
+ JUMP C, number_char
+ ADD s0, 07 ;ASCII char A to F in range 41 to 46
+ number_char: ADD s0, 3A ;ASCII char 0 to 9 in range 30 to 40
+ RETURN
+ ;
+ ;
+ ;Send the two character HEX value of the register contents 's0' to the UART
+ ;
+ ;Registers used s0, s1, s2
+ ;
+ send_hex_byte: CALL hex_byte_to_ASCII
+ LOAD UART_data, s2
+ CALL send_to_UART
+ LOAD UART_data, s1
+ CALL send_to_UART
+ RETURN
+ ;
+ ;
+ ;
+ ;Send the four character HEX value of the register contents [s9, s8] to the UART
+ ;
+ ;Registers used s0, s9, s8
+ ;
+ send_hex_2bytes: LOAD s0, s9
+ CALL send_hex_byte
+ LOAD s0, s8
+ CALL send_hex_byte
+ RETURN
+ ;
+ ;
+ ;Convert the HEX ASCII characters contained in 's3' and 's2' into
+ ;an equivalent hexadecimal value in register 's0'.
+ ; The upper nibble is represented by an ASCII character in register s3.
+ ; The lower nibble is represented by an ASCII character in register s2.
+ ;
+ ;Input characters must be in the range 00 to FF hexadecimal or the CARRY flag
+ ;will be set on return.
+ ;
+ ;Registers used s0, s2 and s3.
+ ;
+ASCII_byte_to_hex: LOAD s0, s3 ;Take upper nibble
+ CALL ASCII_to_hex ;convert to value
+ RETURN C ;reject if out of range
+ LOAD s3, s0 ;remember value
+ SL0 s3 ;multiply value by 16 to put in upper nibble
+ SL0 s3
+ SL0 s3
+ SL0 s3
+ LOAD s0, s2 ;Take lower nibble
+ CALL ASCII_to_hex ;convert to value
+ RETURN C ;reject if out of range
+ OR s0, s3 ;merge in the upper nibble with CARRY reset
+ RETURN
+ ;
+ ;
+ ;Routine to convert ASCII data in 's0' to an equivalent HEX value.
+ ;
+ ;If character is not valid for hex, then CARRY is set on return.
+ ;
+ ;Register used s0
+ ;
+ ASCII_to_hex: ADD s0, B9 ;test for above ASCII code 46 ('F')
+ RETURN C
+ SUB s0, E9 ;normalise 0 to 9 with A-F in 11 to 16 hex
+ RETURN C ;reject below ASCII code 30 ('0')
+ SUB s0, 11 ;isolate A-F down to 00 to 05 hex
+ JUMP NC, ASCII_letter
+ ADD s0, 07 ;test for above ASCII code 46 ('F')
+ RETURN C
+ SUB s0, F6 ;convert to range 00 to 09
+ RETURN
+ ASCII_letter: ADD s0, 0A ;convert to range 0A to 0F
+ RETURN
+ ;
+ ;
+ ;
+ ;Send Carriage Return to the UART
+ ;
+ send_CR: LOAD UART_data, character_CR
+ CALL send_to_UART
+ RETURN
+ ;
+ ;Send a space to the UART
+ ;
+ send_space: LOAD UART_data, character_space
+ CALL send_to_UART
+ RETURN
+ ;
+ ;
+ ;****************************************************************
+ ;Text messages
+ ;****************************************************************
+ ;
+ ; Position/Status/Data message
+ ; Send @@Ea01C<CR><LF>
+ ; 01 is for setting the response mode (once per second)
+ ; C is checksum for this message (25 hex)
+ ;
+ mess_PSD: CALL send_arroba
+ CALL send_arroba
+ LOAD UART_data, character_E
+ CALL send_to_UART
+ LOAD UART_data, character_a
+ CALL send_to_UART
+ LOAD UART_data, 01
+ CALL send_to_UART
+ LOAD UART_data, 25
+ CALL send_to_UART
+ CALL send_EOM
+ RETURN
+ ;
+ ;
+ ; Time Raim Setup and Status Message (page 94 of man)
+ ; Send @@En000000030100000100000000000000C<CR><LF>
+ ; 03 is for Time RAIM Algoritm (3..65535)
+ ; 01 is for setting (enable every time) the 1PPS signal
+ ; C is checksum for this message (28 hex)
+ ;
+ mess_TRAIM: CALL send_arroba
+ CALL send_arroba
+ LOAD UART_data, character_E
+ CALL send_to_UART
+ LOAD UART_data, character_n
+ CALL send_to_UART
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ LOAD UART_data, 03
+ CALL send_to_UART
+ LOAD UART_data, 01
+ CALL send_to_UART
+ CALL send_zero
+ CALL send_zero
+ LOAD UART_data, 01
+ CALL send_to_UART
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ LOAD UART_data, 28 ; Checksum
+ CALL send_to_UART
+ CALL send_EOM
+ RETURN
+ ;
+ ;
+ ;
+ ; 1PPS Offset message
+ ; Send @@Ay00000000C<CR><LF>
+ ;
+ ; C is checksum for this message (38 hex)
+ ;
+ mess_PPSOFF: CALL send_arroba
+ CALL send_arroba
+ LOAD UART_data, character_A
+ CALL send_to_UART
+ LOAD UART_data, character_y
+ CALL send_to_UART
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ LOAD UART_data, 38 ; Checksum
+ CALL send_to_UART
+ CALL send_EOM
+ RETURN
+ ;
+ ;
+ ; 1PPS Cable delay message
+ ; Send @@Az00000000C<CR><LF>
+ ;
+ ; C is checksum for this message (3B hex)
+ ;
+ mess_PPSCD: CALL send_arroba
+ CALL send_arroba
+ LOAD UART_data, character_A
+ CALL send_to_UART
+ LOAD UART_data, character_z
+ CALL send_to_UART
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ LOAD UART_data, 3B ; Checksum
+ CALL send_to_UART
+ CALL send_EOM
+ RETURN
+ ;
+ ;
+ ; Pulse Mode message
+ ; Send @@AP00C<CR><LF>
+ ;
+ ; C is checksum for this message (11 hex)
+ ;
+ mess_PM: CALL send_arroba
+ CALL send_arroba
+ LOAD UART_data, character_A
+ CALL send_to_UART
+ LOAD UART_data, character_P
+ CALL send_to_UART
+ CALL send_zero
+ LOAD UART_data, 11 ; Checksum
+ CALL send_to_UART
+ CALL send_EOM
+ RETURN
+ ;
+ ;
+ ; GMT Offset message
+ ; Send @@Ab000000C<CR><LF>
+ ;
+ ; C is checksum for this message (23 hex)
+ ;
+ mess_GMTOFF: CALL send_arroba
+ CALL send_arroba
+ LOAD UART_data, character_A
+ CALL send_to_UART
+ LOAD UART_data, character_b
+ CALL send_to_UART
+ CALL send_zero
+ CALL send_zero
+ CALL send_zero
+ LOAD UART_data, 23 ; Checksum
+ CALL send_to_UART
+ CALL send_EOM
+ RETURN
+ ;
+ ;
+ ; Time Mode message
+ ; Send @@Aw01C<CR><LF>
+ ;
+ ; C is checksum for this message (37 hex)
+ ;
+ mess_TM: CALL send_arroba
+ CALL send_arroba
+ LOAD UART_data, character_A
+ CALL send_to_UART
+ LOAD UART_data, character_w
+ CALL send_to_UART
+ LOAD UART_data, 01
+ CALL send_to_UART
+ LOAD UART_data, 37 ; Checksum
+ CALL send_to_UART
+ CALL send_EOM
+ RETURN
+ ;
+ ;
+ ; EOM End Of Message
+ ;
+ send_EOM: LOAD UART_data, character_CR
+ CALL send_to_UART
+ LOAD UART_data, character_LF
+ CALL send_to_UART
+ RETURN
+ ;
+ ;
+ send_arroba: LOAD UART_data, character_arroba
+ CALL send_to_UART
+ RETURN
+ ;
+ ;
+ send_zero: LOAD UART_data, 00
+ CALL send_to_UART
+ RETURN
+ ;
+ ;
+ ;**************************************************************************************
+ ; Interrupt Service Routine (ISR)
+ ;**************************************************************************************
+ ;
+ ; Interrupts are not used in this design. This is a place keeper only.
+ ;
+ ADDRESS 3FE
+ ISR: RETURNI ENABLE
+ ;
+ ;
+ ;**************************************************************************************
+ ; Interrupt Vector
+ ;**************************************************************************************
+ ;
+ ADDRESS 3FF
+ JUMP ISR
+ ;
+ ;
diff --git a/GPSNFIFO.VHD b/GPSNFIFO.VHD
new file mode 100755
index 0000000..0a5f396
--- /dev/null
+++ b/GPSNFIFO.VHD
@@ -0,0 +1,274 @@
+--
+-- Definition of a single port ROM for KCPSM3 program defined by gpsnfifo.psm
+--
+-- Generated by KCPSM3 Assembler 08Feb2012-16:15:03.
+--
+-- Standard IEEE libraries
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library unisim;
+use unisim.vcomponents.all;
+--
+--
+entity gpsnfifo is
+ Port ( address : in std_logic_vector(9 downto 0);
+ instruction : out std_logic_vector(17 downto 0);
+ clk : in std_logic);
+ end gpsnfifo;
+--
+architecture low_level_definition of gpsnfifo is
+--
+-- Attributes to define ROM contents during implementation synthesis.
+-- The information is repeated in the generic map for functional simulation
+--
+attribute INIT_00 : string;
+attribute INIT_01 : string;
+attribute INIT_02 : string;
+attribute INIT_03 : string;
+attribute INIT_04 : string;
+attribute INIT_05 : string;
+attribute INIT_06 : string;
+attribute INIT_07 : string;
+attribute INIT_08 : string;
+attribute INIT_09 : string;
+attribute INIT_0A : string;
+attribute INIT_0B : string;
+attribute INIT_0C : string;
+attribute INIT_0D : string;
+attribute INIT_0E : string;
+attribute INIT_0F : string;
+attribute INIT_10 : string;
+attribute INIT_11 : string;
+attribute INIT_12 : string;
+attribute INIT_13 : string;
+attribute INIT_14 : string;
+attribute INIT_15 : string;
+attribute INIT_16 : string;
+attribute INIT_17 : string;
+attribute INIT_18 : string;
+attribute INIT_19 : string;
+attribute INIT_1A : string;
+attribute INIT_1B : string;
+attribute INIT_1C : string;
+attribute INIT_1D : string;
+attribute INIT_1E : string;
+attribute INIT_1F : string;
+attribute INIT_20 : string;
+attribute INIT_21 : string;
+attribute INIT_22 : string;
+attribute INIT_23 : string;
+attribute INIT_24 : string;
+attribute INIT_25 : string;
+attribute INIT_26 : string;
+attribute INIT_27 : string;
+attribute INIT_28 : string;
+attribute INIT_29 : string;
+attribute INIT_2A : string;
+attribute INIT_2B : string;
+attribute INIT_2C : string;
+attribute INIT_2D : string;
+attribute INIT_2E : string;
+attribute INIT_2F : string;
+attribute INIT_30 : string;
+attribute INIT_31 : string;
+attribute INIT_32 : string;
+attribute INIT_33 : string;
+attribute INIT_34 : string;
+attribute INIT_35 : string;
+attribute INIT_36 : string;
+attribute INIT_37 : string;
+attribute INIT_38 : string;
+attribute INIT_39 : string;
+attribute INIT_3A : string;
+attribute INIT_3B : string;
+attribute INIT_3C : string;
+attribute INIT_3D : string;
+attribute INIT_3E : string;
+attribute INIT_3F : string;
+attribute INITP_00 : string;
+attribute INITP_01 : string;
+attribute INITP_02 : string;
+attribute INITP_03 : string;
+attribute INITP_04 : string;
+attribute INITP_05 : string;
+attribute INITP_06 : string;
+attribute INITP_07 : string;
+--
+-- Attributes to define ROM contents during implementation synthesis.
+--
+attribute INIT_00 of ram_1024_x_18 : label is "0123540C40400123020701FA01EF01E101D301B701AB013B013B013B013B013B";
+attribute INIT_01 of ram_1024_x_18 : label is "01260601150001230126060015000123540C40610123540C40450123540C4040";
+attribute INIT_02 of ram_1024_x_18 : label is "0126060515000123012606041500012301260603150001230126060215000123";
+attribute INIT_03 of ram_1024_x_18 : label is "0126060915000123012606081500012301260607150001230126060615000123";
+attribute INIT_04 of ram_1024_x_18 : label is "0126060D150001230126060C150001230126060B150001230126060A15000123";
+attribute INIT_05 of ram_1024_x_18 : label is "012606111500012301260610150001230126060F150001230126060E15000123";
+attribute INIT_06 of ram_1024_x_18 : label is "0126061515000123012606141500012301260613150001230126061215000123";
+attribute INIT_07 of ram_1024_x_18 : label is "0126061815000123012606171500012301230123012301230126061615000123";
+attribute INIT_08 of ram_1024_x_18 : label is "061C150001230126061B1500012301230126061A150001230126061915000123";
+attribute INIT_09 of ram_1024_x_18 : label is "0620150001230126061F150001230126061E150001230126061D150001230126";
+attribute INIT_0A of ram_1024_x_18 : label is "0624150001230126062315000123012606221500012301260621150001230126";
+attribute INIT_0B of ram_1024_x_18 : label is "0628150001230126062715000123012606261500012301260625150001230126";
+attribute INIT_0C of ram_1024_x_18 : label is "062C150001230126062B150001230126062A1500012301260629150001230126";
+attribute INIT_0D of ram_1024_x_18 : label is "012301260630150001230126062F15000123E02E01230126062D150001230126";
+attribute INIT_0E of ram_1024_x_18 : label is "0123012606341500012301260633150001230126063215000123012606311500";
+attribute INIT_0F of ram_1024_x_18 : label is "0123012606381500012301260637150001230126063615000123012606351500";
+attribute INIT_10 of ram_1024_x_18 : label is "01230126063C150001230126063B150001230126063A15000123012606391500";
+attribute INIT_11 of ram_1024_x_18 : label is "0123540C400D012301230126063F150001230126063E150001230126063D1500";
+attribute INIT_12 of ram_1024_x_18 : label is "552DCB0101280B0AA0005529CA010A0BA000D560A00010F00145400C540C400A";
+attribute INIT_13 of ram_1024_x_18 : label is "A000553CCD0101360D14A0005537CC0101310C19A0005532CB0101280B28A000";
+attribute INIT_14 of ram_1024_x_18 : label is "CFC0414B514F20024040A0004F804145554920044040A0005541CE01013B0E14";
+attribute INIT_15 of ram_1024_x_18 : label is "B80080C6A000A0DFBC00407BB8004061A000803AC1015D52C00A81010130A000";
+attribute INIT_16 of ram_1024_x_18 : label is "A0009200B800015E7010810102069200020602061200B800015E7010A000C0F6";
+attribute INIT_17 of ram_1024_x_18 : label is "803A8007597FC00AA0001100017CA00F10101200017C000E000E000E000E1100";
+attribute INIT_18 of ram_1024_x_18 : label is "1300B80001991030A0000181108001811090A000014B1F10014B1F200170A000";
+attribute INIT_19 of ram_1024_x_18 : label is "80075DA3C011B800C0E9B80080B9A000D030B800019910200306030603060306";
+attribute INIT_1A of ram_1024_x_18 : label is "0F61014B0F4502180218A000014B0F20A000014B0F0DA000800AA000C0F6B800";
+attribute INIT_1B of ram_1024_x_18 : label is "021B021B021B014B0F6E014B0F4502180218A0000213014B0F25014B0F01014B";
+attribute INIT_1C of ram_1024_x_18 : label is "0F28021B021B021B021B021B021B021B014B0F01021B021B014B0F01014B0F03";
+attribute INIT_1D of ram_1024_x_18 : label is "0213014B0F38021B021B021B021B014B0F79014B0F4102180218A0000213014B";
+attribute INIT_1E of ram_1024_x_18 : label is "0218A0000213014B0F3B021B021B021B021B014B0F7A014B0F4102180218A000";
+attribute INIT_1F of ram_1024_x_18 : label is "014B0F62014B0F4102180218A0000213014B0F11021B014B0F50014B0F410218";
+attribute INIT_20 of ram_1024_x_18 : label is "0F37014B0F01014B0F77014B0F4102180218A0000213014B0F23021B021B021B";
+attribute INIT_21 of ram_1024_x_18 : label is "00000000A000014B0F00A000014B0F40A000014B0F0A014B0F0DA0000213014B";
+attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3F of ram_1024_x_18 : label is "43FE800100000000000000000000000000000000000000000000000000000000";
+attribute INITP_00 of ram_1024_x_18 : label is "C3C3FFC3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3DF7DF7FFFFFF";
+attribute INITP_01 of ram_1024_x_18 : label is "F0F0F0F0F0F0F0F0F0F0EF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0FC3C3";
+attribute INITP_02 of ram_1024_x_18 : label is "5D8C0EA89B19A2C998999752BD23D2DCB72DCB72DCB4A8FDF7F0F0F0F0F0F0F0";
+attribute INITP_03 of ram_1024_x_18 : label is "CCFBCF33EF3FF33EF3FF33EF3FFFCFCCFF33EF3333ECB26676662CAA2CB32CCE";
+attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000B2CB32F3333EF3F";
+attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INITP_07 of ram_1024_x_18 : label is "F000000000000000000000000000000000000000000000000000000000000000";
+--
+begin
+--
+ --Instantiate the Xilinx primitive for a block RAM
+ ram_1024_x_18: RAMB16_S18
+ --synthesis translate_off
+ --INIT values repeated to define contents for functional simulation
+ generic map ( INIT_00 => X"0123540C40400123020701FA01EF01E101D301B701AB013B013B013B013B013B",
+ INIT_01 => X"01260601150001230126060015000123540C40610123540C40450123540C4040",
+ INIT_02 => X"0126060515000123012606041500012301260603150001230126060215000123",
+ INIT_03 => X"0126060915000123012606081500012301260607150001230126060615000123",
+ INIT_04 => X"0126060D150001230126060C150001230126060B150001230126060A15000123",
+ INIT_05 => X"012606111500012301260610150001230126060F150001230126060E15000123",
+ INIT_06 => X"0126061515000123012606141500012301260613150001230126061215000123",
+ INIT_07 => X"0126061815000123012606171500012301230123012301230126061615000123",
+ INIT_08 => X"061C150001230126061B1500012301230126061A150001230126061915000123",
+ INIT_09 => X"0620150001230126061F150001230126061E150001230126061D150001230126",
+ INIT_0A => X"0624150001230126062315000123012606221500012301260621150001230126",
+ INIT_0B => X"0628150001230126062715000123012606261500012301260625150001230126",
+ INIT_0C => X"062C150001230126062B150001230126062A1500012301260629150001230126",
+ INIT_0D => X"012301260630150001230126062F15000123E02E01230126062D150001230126",
+ INIT_0E => X"0123012606341500012301260633150001230126063215000123012606311500",
+ INIT_0F => X"0123012606381500012301260637150001230126063615000123012606351500",
+ INIT_10 => X"01230126063C150001230126063B150001230126063A15000123012606391500",
+ INIT_11 => X"0123540C400D012301230126063F150001230126063E150001230126063D1500",
+ INIT_12 => X"552DCB0101280B0AA0005529CA010A0BA000D560A00010F00145400C540C400A",
+ INIT_13 => X"A000553CCD0101360D14A0005537CC0101310C19A0005532CB0101280B28A000",
+ INIT_14 => X"CFC0414B514F20024040A0004F804145554920044040A0005541CE01013B0E14",
+ INIT_15 => X"B80080C6A000A0DFBC00407BB8004061A000803AC1015D52C00A81010130A000",
+ INIT_16 => X"A0009200B800015E7010810102069200020602061200B800015E7010A000C0F6",
+ INIT_17 => X"803A8007597FC00AA0001100017CA00F10101200017C000E000E000E000E1100",
+ INIT_18 => X"1300B80001991030A0000181108001811090A000014B1F10014B1F200170A000",
+ INIT_19 => X"80075DA3C011B800C0E9B80080B9A000D030B800019910200306030603060306",
+ INIT_1A => X"0F61014B0F4502180218A000014B0F20A000014B0F0DA000800AA000C0F6B800",
+ INIT_1B => X"021B021B021B014B0F6E014B0F4502180218A0000213014B0F25014B0F01014B",
+ INIT_1C => X"0F28021B021B021B021B021B021B021B014B0F01021B021B014B0F01014B0F03",
+ INIT_1D => X"0213014B0F38021B021B021B021B014B0F79014B0F4102180218A0000213014B",
+ INIT_1E => X"0218A0000213014B0F3B021B021B021B021B014B0F7A014B0F4102180218A000",
+ INIT_1F => X"014B0F62014B0F4102180218A0000213014B0F11021B014B0F50014B0F410218",
+ INIT_20 => X"0F37014B0F01014B0F77014B0F4102180218A0000213014B0F23021B021B021B",
+ INIT_21 => X"00000000A000014B0F00A000014B0F40A000014B0F0A014B0F0DA0000213014B",
+ INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3F => X"43FE800100000000000000000000000000000000000000000000000000000000",
+ INITP_00 => X"C3C3FFC3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3C3DF7DF7FFFFFF",
+ INITP_01 => X"F0F0F0F0F0F0F0F0F0F0EF0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0F0FC3C3",
+ INITP_02 => X"5D8C0EA89B19A2C998999752BD23D2DCB72DCB72DCB4A8FDF7F0F0F0F0F0F0F0",
+ INITP_03 => X"CCFBCF33EF3FF33EF3FF33EF3FFFCFCCFF33EF3333ECB26676662CAA2CB32CCE",
+ INITP_04 => X"0000000000000000000000000000000000000000000000000B2CB32F3333EF3F",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"F000000000000000000000000000000000000000000000000000000000000000")
+ --synthesis translate_on
+ port map( DI => "0000000000000000",
+ DIP => "00",
+ EN => '1',
+ WE => '0',
+ SSR => '0',
+ CLK => clk,
+ ADDR => address,
+ DO => instruction(15 downto 0),
+ DOP => instruction(17 downto 16));
+--
+end low_level_definition;
+--
+------------------------------------------------------------------------------------
+--
+-- END OF FILE gpsnfifo.vhd
+--
+------------------------------------------------------------------------------------
diff --git a/GPS_n_fifo.vhd b/GPS_n_fifo.vhd
new file mode 100644
index 0000000..43d875a
--- /dev/null
+++ b/GPS_n_fifo.vhd
@@ -0,0 +1,441 @@
+--
+-- Copyright (C) 2011 Horacio Arnaldi
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--
+------------------------------------------------------------------------------------
+--
+--
+entity Oncore_ctrl is
+ Port (
+ clk : in std_logic;
+ tx_female : out std_logic;
+ rx_female : in std_logic;
+ UTCnGPS : in std_logic;
+
+ -- Costants data output
+ month_port : out std_logic_vector(7 downto 0);
+ day_port : out std_logic_vector(7 downto 0);
+ year1_port : out std_logic_vector(7 downto 0);
+ year2_port : out std_logic_vector(7 downto 0);
+ hours_port : out std_logic_vector(7 downto 0);
+ minutes_port : out std_logic_vector(7 downto 0);
+ seconds_port : out std_logic_vector(7 downto 0);
+ fract_sec1_port : out std_logic_vector(7 downto 0);
+ fract_sec2_port : out std_logic_vector(7 downto 0);
+ fract_sec3_port : out std_logic_vector(7 downto 0);
+ fract_sec4_port : out std_logic_vector(7 downto 0);
+ latitude1_port : out std_logic_vector(7 downto 0);
+ latitude2_port : out std_logic_vector(7 downto 0);
+ latitude3_port : out std_logic_vector(7 downto 0);
+ latitude4_port : out std_logic_vector(7 downto 0);
+ longitude1_port : out std_logic_vector(7 downto 0);
+ longitude2_port : out std_logic_vector(7 downto 0);
+ longitude3_port : out std_logic_vector(7 downto 0);
+ longitude4_port : out std_logic_vector(7 downto 0);
+ ellipsoid1_port : out std_logic_vector(7 downto 0);
+ ellipsoid2_port : out std_logic_vector(7 downto 0);
+ ellipsoid3_port : out std_logic_vector(7 downto 0);
+ ellipsoid4_port : out std_logic_vector(7 downto 0);
+ velocity1_port : out std_logic_vector(7 downto 0);
+ velocity2_port : out std_logic_vector(7 downto 0);
+ heading1_port : out std_logic_vector(7 downto 0);
+ heading2_port : out std_logic_vector(7 downto 0);
+ geometry2_port : out std_logic_vector(7 downto 0);
+ DOP_type_port : out std_logic_vector(7 downto 0);
+ num_vis_sat_port : out std_logic_vector(7 downto 0);
+ num_track_sat_port : out std_logic_vector(7 downto 0);
+
+ sat_ID1_port : out std_logic_vector(7 downto 0);
+ chtm1_port : out std_logic_vector(7 downto 0);
+ CNo1_port : out std_logic_vector(7 downto 0);
+ chsf1_port : out std_logic_vector(7 downto 0);
+
+ sat_ID2_port : out std_logic_vector(7 downto 0);
+ chtm2_port : out std_logic_vector(7 downto 0);
+ CNo2_port : out std_logic_vector(7 downto 0);
+ chsf2_port : out std_logic_vector(7 downto 0);
+
+ sat_ID3_port : out std_logic_vector(7 downto 0);
+ chtm3_port : out std_logic_vector(7 downto 0);
+ CNo3_port : out std_logic_vector(7 downto 0);
+ chsf3_port : out std_logic_vector(7 downto 0);
+
+ sat_ID4_port : out std_logic_vector(7 downto 0);
+ chtm4_port : out std_logic_vector(7 downto 0);
+ CNo4_port : out std_logic_vector(7 downto 0);
+ chsf4_port : out std_logic_vector(7 downto 0);
+
+ sat_ID5_port : out std_logic_vector(7 downto 0);
+ chtm5_port : out std_logic_vector(7 downto 0);
+ CNo5_port : out std_logic_vector(7 downto 0);
+ chsf5_port : out std_logic_vector(7 downto 0);
+
+ sat_ID6_port : out std_logic_vector(7 downto 0);
+ chtm6_port : out std_logic_vector(7 downto 0);
+ CNo6_port : out std_logic_vector(7 downto 0);
+ chsf6_port : out std_logic_vector(7 downto 0);
+
+ sat_ID7_port : out std_logic_vector(7 downto 0);
+ chtm7_port : out std_logic_vector(7 downto 0);
+ CNo7_port : out std_logic_vector(7 downto 0);
+ chsf7_port : out std_logic_vector(7 downto 0);
+
+ sat_ID8_port : out std_logic_vector(7 downto 0);
+ chtm8_port : out std_logic_vector(7 downto 0);
+ CNo8_port : out std_logic_vector(7 downto 0);
+ chsf8_port : out std_logic_vector(7 downto 0);
+
+ rsf_port : out std_logic_vector(7 downto 0));
+end Oncore_ctrl;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of test architecture
+--
+architecture rtl of Oncore_ctrl is
+--
+------------------------------------------------------------------------------------
+
+--
+-- declaration of KCPSM3
+--
+ component kcpsm3
+ Port ( address : out std_logic_vector(9 downto 0);
+ instruction : in std_logic_vector(17 downto 0);
+ port_id : out std_logic_vector(7 downto 0);
+ write_strobe : out std_logic;
+ out_port : out std_logic_vector(7 downto 0);
+ read_strobe : out std_logic;
+ in_port : in std_logic_vector(7 downto 0);
+ interrupt : in std_logic;
+ interrupt_ack : out std_logic;
+ reset : in std_logic;
+ clk : in std_logic);
+ end component;
+--
+-- declaration of program ROM
+--
+ component gpsnfifo
+ Port ( address : in std_logic_vector(9 downto 0);
+ instruction : out std_logic_vector(17 downto 0);
+ clk : in std_logic);
+ end component;
+--
+------------------------------------------------------------------------------------
+--
+--
+-- declaration of UART transmitter with integral 16 byte FIFO buffer.
+--
+ component uart_tx
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ write_buffer : in std_logic;
+ reset_buffer : in std_logic;
+ en_16_x_baud : in std_logic;
+ serial_out : out std_logic;
+ buffer_full : out std_logic;
+ buffer_half_full : out std_logic;
+ clk : in std_logic);
+ end component;
+--
+-- declaration of UART Receiver with integral 16 byte FIFO buffer
+--
+ component uart_rx
+ Port ( serial_in : in std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ read_buffer : in std_logic;
+ reset_buffer : in std_logic;
+ en_16_x_baud : in std_logic;
+ buffer_data_present : out std_logic;
+ buffer_full : out std_logic;
+ buffer_half_full : out std_logic;
+ clk : in std_logic);
+ end component;
+--
+-- Signals used to connect KCPSM3 to program ROM and I/O logic
+--
+signal address : std_logic_vector(9 downto 0);
+signal instruction : std_logic_vector(17 downto 0);
+signal port_id : std_logic_vector(7 downto 0);
+signal out_port : std_logic_vector(7 downto 0);
+signal in_port : std_logic_vector(7 downto 0);
+signal swrite_strobe : std_logic;
+signal sread_strobe : std_logic;
+signal interrupt : std_logic;
+signal interrupt_ack : std_logic;
+signal kcpsm3_reset : std_logic;
+--
+-- Signals for connection of peripherals
+--
+signal status_port : std_logic_vector(7 downto 0);
+--
+-- Signals for interrupt generation
+--
+--signal interrupt_count : integer range 0 to 1526 :=0;
+--signal interrupt_event : std_logic;
+--
+-- Signals for UART connections
+--
+signal baud_count : integer range 0 to 325 :=0;
+signal en_16_x_baud : std_logic;
+signal write_to_uart : std_logic;
+signal tx_full : std_logic;
+signal tx_half_full : std_logic;
+signal read_from_uart : std_logic;
+signal rx_data : std_logic_vector(7 downto 0);
+signal rx_data_present : std_logic;
+signal rx_full : std_logic;
+signal rx_half_full : std_logic;
+--
+--
+--
+begin
+
+ ----------------------------------------------------------------------------------------------------------------------------------
+ -- KCPSM3 and the program memory
+ ----------------------------------------------------------------------------------------------------------------------------------
+ --
+
+ processor: kcpsm3
+ port map( address => address,
+ instruction => instruction,
+ port_id => port_id,
+ write_strobe => swrite_strobe,
+ out_port => out_port,
+ read_strobe => sread_strobe,
+ in_port => in_port,
+ interrupt => interrupt,
+ interrupt_ack => interrupt_ack,
+ reset => kcpsm3_reset,
+ clk => clk);
+
+ program_rom: gpsnfifo
+ port map( address => address,
+ instruction => instruction,
+ clk => clk);
+
+ --
+ --
+ -- Interrupt is not used in this version of the design.
+ --
+ interrupt <= interrupt_ack;
+ --
+ --
+ --
+ ----------------------------------------------------------------------------------------------------------------------------------
+ -- KCPSM3 input ports
+ ----------------------------------------------------------------------------------------------------------------------------------
+ --
+ --
+ -- UART FIFO status signals to form a bus
+ --
+
+ status_port <= UTCnGPS & "00" & rx_full & rx_half_full & rx_data_present & tx_full & tx_half_full;
+
+ --
+ --
+ -- The inputs connect via a pipelined multiplexer
+ --
+ input_ports: process(clk)
+ begin
+ if clk'event and clk='1' then
+
+ case port_id(7 downto 6) is
+
+
+ -- read status signals at address 00 hex
+ when "01" => in_port <= status_port;
+
+ -- read UART receive data at address 01 hex
+ when "10" => in_port <= rx_data;
+
+ -- Don't care used for all other addresses to ensure minimum logic implementation
+ when others => in_port <= "XXXXXXXX";
+
+ end case;
+
+ -- Form read strobe for UART receiver FIFO buffer at address 01 hex.
+ -- The fact that the read strobe will occur after the actual data is read by
+ -- the KCPSM3 is acceptable because it is really means 'I have read you'!
+
+ if (sread_strobe='1' and port_id(7 downto 6)="10") then
+ read_from_uart <= '1';
+ else
+ read_from_uart <= '0';
+ end if;
+
+ end if;
+
+ end process input_ports;
+
+ --
+ ----------------------------------------------------------------------------------------------------------------------------------
+ -- KCPSM3 output ports
+ ----------------------------------------------------------------------------------------------------------------------------------
+ --
+
+ -- adding the output registers to the processor
+
+ output_ports: process(clk)
+ begin
+
+ if clk'event and clk='1' then
+ if swrite_strobe='1' then
+
+ case port_id is--(5 downto 0) is
+
+ when x"00" => month_port <= out_port;
+ when x"01" => day_port <= out_port;
+ when x"02" => year1_port <= out_port;
+ when x"03" => year2_port <= out_port;
+ when x"04" => hours_port <= out_port;
+ when x"05" => minutes_port <= out_port;
+ when x"06" => seconds_port <= out_port;
+ when x"07" => fract_sec1_port <= out_port;
+ when x"08" => fract_sec2_port <= out_port;
+ when x"09" => fract_sec3_port <= out_port;
+ when x"0A" => fract_sec4_port <= out_port;
+ when x"0B" => latitude1_port <= out_port;
+ when x"0C" => latitude2_port <= out_port;
+ when x"0D" => latitude3_port <= out_port;
+ when x"0E" => latitude4_port <= out_port;
+ when x"0F" => longitude1_port <= out_port;
+ when x"10" => longitude2_port <= out_port;
+ when x"11" => longitude3_port <= out_port;
+ when x"12" => longitude4_port <= out_port;
+ when x"13" => ellipsoid1_port <= out_port;
+ when x"14" => ellipsoid2_port <= out_port;
+ when x"15" => ellipsoid3_port <= out_port;
+ when x"16" => ellipsoid4_port <= out_port;
+ when x"17" => velocity1_port <= out_port;
+ when x"18" => velocity2_port <= out_port;
+ when x"19" => heading1_port <= out_port;
+ when x"1A" => heading2_port <= out_port;
+ when x"1B" => geometry2_port <= out_port;
+ when x"1C" => DOP_type_port <= out_port;
+ when x"1D" => num_vis_sat_port <= out_port;
+ when x"1E" => num_track_sat_port <= out_port;
+ when x"1F" => sat_ID1_port <= out_port;
+ when x"20" => chtm1_port <= out_port;
+ when x"21" => CNo1_port <= out_port;
+ when x"22" => chsf1_port <= out_port;
+ when x"23" => sat_ID2_port <= out_port;
+ when x"24" => chtm2_port <= out_port;
+ when x"25" => CNo2_port <= out_port;
+ when x"26" => chsf2_port <= out_port;
+ when x"27" => sat_ID3_port <= out_port;
+ when x"28" => chtm3_port <= out_port;
+ when x"29" => CNo3_port <= out_port;
+ when x"2A" => chsf3_port <= out_port;
+ when x"2B" => sat_ID4_port <= out_port;
+ when x"2C" => chtm4_port <= out_port;
+ when x"2D" => CNo4_port <= out_port;
+ when x"2E" => chsf4_port <= out_port;
+ when x"2F" => sat_ID5_port <= out_port;
+ when x"30" => chtm5_port <= out_port;
+ when x"31" => CNo5_port <= out_port;
+ when x"32" => chsf5_port <= out_port;
+ when x"33" => sat_ID6_port <= out_port;
+ when x"34" => chtm6_port <= out_port;
+ when x"35" => CNo6_port <= out_port;
+ when x"36" => chsf6_port <= out_port;
+ when x"37" => sat_ID7_port <= out_port;
+ when x"38" => chtm7_port <= out_port;
+ when x"39" => CNo7_port <= out_port;
+ when x"3A" => chsf7_port <= out_port;
+ when x"3B" => sat_ID8_port <= out_port;
+ when x"3C" => chtm8_port <= out_port;
+ when x"3D" => CNo8_port <= out_port;
+ when x"3E" => chsf8_port <= out_port;
+ when x"3F" => rsf_port <= out_port;
+
+ -- Don't care used for all other addresses to
+ -- ensure minimum logic implementation
+ when others =>
+
+ end case;
+
+ end if;
+
+ end if;
+
+ end process output_ports;
+
+ --
+ -- write to UART transmitter FIFO buffer at address 20 hex.
+ -- This is a combinatorial decode because the FIFO is the 'port register'.
+ --
+
+ write_to_uart <= '1' when (swrite_strobe='1' and port_id(7 downto 6) ="11") else '0';
+
+
+ --
+ ----------------------------------------------------------------------------------------------------------------------------------
+ -- UART
+ ----------------------------------------------------------------------------------------------------------------------------------
+ --
+ -- Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
+ -- Each contains an embedded 16-byte FIFO buffer.
+ --
+
+ transmit: uart_tx
+ port map ( data_in => out_port,
+ write_buffer => write_to_uart,
+ reset_buffer => '0',
+ en_16_x_baud => en_16_x_baud,
+ serial_out => tx_female,
+ buffer_full => tx_full,
+ buffer_half_full => tx_half_full,
+ clk => clk );
+
+ receive: uart_rx
+ port map ( serial_in => rx_female,
+ data_out => rx_data,
+ read_buffer => read_from_uart,
+ reset_buffer => '0',
+ en_16_x_baud => en_16_x_baud,
+ buffer_data_present => rx_data_present,
+ buffer_full => rx_full,
+ buffer_half_full => rx_half_full,
+ clk => clk );
+
+ --
+ -- Set baud rate to 9600 for the UART communications
+ -- Requires en_16_x_baud to be 153600Hz which is a single cycle pulse every 326 cycles at 50MHz
+ --
+
+ baud_timer: process(clk)
+ begin
+ if clk'event and clk='1' then
+ if baud_count=325 then
+ baud_count <= 0;
+ en_16_x_baud <= '1';
+ else
+ baud_count <= baud_count + 1;
+ en_16_x_baud <= '0';
+ end if;
+ end if;
+ end process baud_timer;
+
+ --
+ --
+ ----------------------------------------------------------------------------------------------------------------------------------
+
+end rtl;
diff --git a/HP03_par_control.vhd b/HP03_par_control.vhd
new file mode 100644
index 0000000..dff5910
--- /dev/null
+++ b/HP03_par_control.vhd
@@ -0,0 +1,347 @@
+--
+-- Copyright (C) 2011 Horacio Arnaldi
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--
+------------------------------------------------------------------------------------
+--
+--
+entity HP03_cntrl is
+ Port ( clk : in std_logic;
+ -- I2C and HP03 related signals
+ SDA : inout std_logic;
+ SCL : out std_logic;
+ XCLR : out std_logic;
+ MCLK : out std_logic;
+ -- Costants data output
+ C1 : out std_logic_vector(15 downto 0);
+ C2 : out std_logic_vector(15 downto 0);
+ C3 : out std_logic_vector(15 downto 0);
+ C4 : out std_logic_vector(15 downto 0);
+ C5 : out std_logic_vector(15 downto 0);
+ C6 : out std_logic_vector(15 downto 0);
+ C7 : out std_logic_vector(15 downto 0);
+ A : out std_logic_vector(7 downto 0);
+ B : out std_logic_vector(7 downto 0);
+ C : out std_logic_vector(7 downto 0);
+ D : out std_logic_vector(7 downto 0);
+ -- ADC data output
+ -- Pressure data
+ D1 : out std_logic_vector(15 downto 0);
+ -- Temperature data
+ D2 : out std_logic_vector(15 downto 0));
+ end HP03_cntrl;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of test architecture
+--
+architecture rtl of HP03_cntrl is
+--
+------------------------------------------------------------------------------------
+
+--
+-- declaration of KCPSM3
+--
+ component kcpsm3
+ Port ( address : out std_logic_vector(9 downto 0);
+ instruction : in std_logic_vector(17 downto 0);
+ port_id : out std_logic_vector(7 downto 0);
+ write_strobe : out std_logic;
+ out_port : out std_logic_vector(7 downto 0);
+ read_strobe : out std_logic;
+ in_port : in std_logic_vector(7 downto 0);
+ interrupt : in std_logic;
+ interrupt_ack : out std_logic;
+ reset : in std_logic;
+ clk : in std_logic);
+ end component;
+--
+-- declaration of program ROM
+--
+ component hp_lago
+ Port ( address : in std_logic_vector(9 downto 0);
+ instruction : out std_logic_vector(17 downto 0);
+ clk : in std_logic);
+ end component;
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used to connect KCPSM3 to program ROM and I/O logic
+--
+signal address : std_logic_vector(9 downto 0);
+signal instruction : std_logic_vector(17 downto 0);
+signal port_id : std_logic_vector(7 downto 0);
+signal out_port : std_logic_vector(7 downto 0);
+signal in_port : std_logic_vector(7 downto 0);
+signal swrite_strobe : std_logic;
+signal sread_strobe : std_logic;
+signal interrupt : std_logic;
+signal interrupt_ack : std_logic;
+signal kcpsm3_reset : std_logic;
+--
+-- Signals for connection of peripherals
+--
+-- Signals for mclk generation
+--
+signal mclk_count : integer range 0 to 763 :=0; --32khz
+signal mclk_int : std_logic;
+--
+signal sC1_msb, sC1_lsb : std_logic_vector(7 downto 0);
+signal sC2_msb, sC2_lsb : std_logic_vector(7 downto 0);
+signal sC3_msb, sC3_lsb : std_logic_vector(7 downto 0);
+signal sC4_msb, sC4_lsb : std_logic_vector(7 downto 0);
+signal sC5_msb, sC5_lsb : std_logic_vector(7 downto 0);
+signal sC6_msb, sC6_lsb : std_logic_vector(7 downto 0);
+signal sC7_msb, sC7_lsb : std_logic_vector(7 downto 0);
+signal sA, sB : std_logic_vector(7 downto 0);
+signal sC, sD : std_logic_vector(7 downto 0);
+signal sD1_msb, sD1_lsb : std_logic_vector(7 downto 0);
+signal sD2_msb, sD2_lsb : std_logic_vector(7 downto 0);
+-- Signal to connect to HP03 SDA interface
+--
+signal drive_hp_wire, sSCL, sXCLR : std_logic;
+--
+--
+begin
+ --
+ ----------------------------------------------------------------------------------------------------------------------------------
+ -- Open Collector Bidirectional data interface to HP03
+ ----------------------------------------------------------------------------------------------------------------------------------
+ --
+ -- The I2C interface is an open collector interface with an external pull-up resistor
+ -- fitted on the board.
+ --
+ -- To transmit a Low signal, the output buffer must be enabled with a data value of '0'.
+ -- To transmit a High, the output buffer is disabled (tri-state) and the external
+ -- pull-up generates the '1'.
+ -- Receiving a bit is again performed with the output buffer disabled.
+ --
+ --
+ SDA <= '0' when (drive_hp_wire='0') else 'Z';
+ SCL <= sSCL;
+ XCLR <= sXCLR;
+ --
+ C1 <= sC1_msb & sC1_lsb;
+ C2 <= sC2_msb & sC2_lsb;
+ C3 <= sC3_msb & sC3_lsb;
+ C4 <= sC4_msb & sC4_lsb;
+ C5 <= sC5_msb & sC5_lsb;
+ C6 <= sC6_msb & sC6_lsb;
+ C7 <= sC7_msb & sC7_lsb;
+ A <= sA;
+ B <= sB;
+ C <= sC;
+ D <= sD;
+ D1 <= sD1_msb & sD1_lsb;
+ D2 <= sD2_msb & sD2_lsb;
+ --
+ -------------------------------------------------------------------------------------------
+ -- KCPSM3 and the program memory
+ -------------------------------------------------------------------------------------------
+ --
+ processor: kcpsm3
+ port map( address => address,
+ instruction => instruction,
+ port_id => port_id,
+ write_strobe => swrite_strobe,
+ out_port => out_port,
+ read_strobe => sread_strobe,
+ in_port => in_port,
+ interrupt => interrupt,
+ interrupt_ack => interrupt_ack,
+ reset => kcpsm3_reset,
+ clk => clk);
+
+ program_rom: hp_lago
+ port map( address => address,
+ instruction => instruction,
+ clk => clk);
+ --
+ --
+ -------------------------------------------------------------------------------------------
+ -- Interrupt
+ -------------------------------------------------------------------------------------------
+ --
+ --
+ -- Interrupt is not used in this version of the design.
+ --
+ interrupt <= interrupt_ack;
+ --
+ -------------------------------------------------------------------------------------------
+ -- KCPSM3 input ports
+ -------------------------------------------------------------------------------------------
+ --
+ input_ports: process(clk)
+ begin
+ if clk'event and clk = '1' then
+ if port_id(5) = '1' then
+ in_port <= "0000000" & SDA;
+ else
+ in_port <= "XXXXXXXX";
+ end if;
+ end if;
+
+ end process input_ports;
+ --
+ -------------------------------------------------------------------------------------------
+ -- KCPSM3 output ports
+ -------------------------------------------------------------------------------------------
+ --
+ -- adding the output registers to the processor
+
+ output_ports: process(clk)
+ begin
+
+ if clk'event and clk='1' then
+ if swrite_strobe='1' then
+ if port_id(6) = '1' then
+ drive_hp_wire <= out_port(0);
+ sSCL <= out_port(1);
+ sXCLR <= out_port(2);
+ end if;
+
+ case port_id(4 downto 0) is
+ -- Write C1_msb constant at address 01 hex
+ when "00001" =>
+ sC1_msb <= out_port
+;
+ -- Write C1_lsb constant at address 02 hex
+ when "00010" =>
+ sC1_lsb <= out_port;
+
+ -- Write C2_msb constant at address 03 hex
+ when "00011" =>
+ sC2_msb <= out_port;
+
+ -- Write C2_lsb constant at address 04 hex
+ when "00100" =>
+ sC2_lsb <= out_port;
+
+ -- Write C3_msb constant at address 05 hex
+ when "00101" =>
+ sC3_msb <= out_port;
+
+ -- Write C3_lsb constant at address 06 hex
+ when "00110" =>
+ sC3_lsb <= out_port;
+
+ -- Write C4_msb constant at address 07 hex
+ when "00111" =>
+ sC4_msb <= out_port;
+
+ -- Write C4_lsb constant at address 08 hex
+ when "01000" =>
+ sC4_lsb <= out_port;
+ -- Write C5_msb constant at address 09 hex
+ when "01001" =>
+ sC5_msb <= out_port;
+ -- Write C5_lsb constant at address 0A hex
+ when "01010" =>
+ sC5_lsb <= out_port;
+ -- Write C6_msb constant at address 0B hex
+ when "01011" =>
+ sC6_msb <= out_port;
+ -- Write C6_lsb constant at address 0C hex
+ when "01100" =>
+ sC6_lsb <= out_port;
+ -- Write C7_msb constant at address 0D hex
+ when "01101" =>
+ sC7_msb <= out_port;
+ -- Write C7_lsb constant at address 0E hex
+ when "01110" =>
+ sC7_lsb <= out_port;
+ -- Write A constant at address 0F hex
+ when "01111" =>
+ sA <= out_port;
+ -- Write B constant at address 10 hex
+ when "10000" =>
+ sB <= out_port;
+ -- Write C constant at address 11 hex
+ when "10001" =>
+ sC <= out_port;
+ -- Write D constant at address 12 hex
+ when "10010" =>
+ sD <= out_port;
+ -- Write ADC data D1_msb at address 13 hex
+ when "10011" =>
+ sD1_msb <= out_port;
+ -- Write ADC data D1_lsb at address 14 hex
+ when "10100" =>
+ sD1_lsb <= out_port;
+ -- Write ADC data D2_msb at address 15 hex
+ when "10101" =>
+ sD2_msb <= out_port;
+ -- Write ADC data D2_lsb at address 16 hex
+ when "10110" =>
+ sD2_lsb <= out_port;
+ -- Don't care used for all other addresses to
+ -- ensure minimum logic implementation
+ when others =>
+ sC1_msb <= "XXXXXXXX";
+ sC1_lsb <= "XXXXXXXX";
+ sC2_msb <= "XXXXXXXX";
+ sC2_lsb <= "XXXXXXXX";
+ sC3_msb <= "XXXXXXXX";
+ sC3_lsb <= "XXXXXXXX";
+ sC4_msb <= "XXXXXXXX";
+ sC4_lsb <= "XXXXXXXX";
+ sC5_msb <= "XXXXXXXX";
+ sC5_lsb <= "XXXXXXXX";
+ sC6_msb <= "XXXXXXXX";
+ sC6_lsb <= "XXXXXXXX";
+ sC7_msb <= "XXXXXXXX";
+ sC7_lsb <= "XXXXXXXX";
+ sA <= "XXXXXXXX";
+ sB <= "XXXXXXXX";
+ sC <= "XXXXXXXX";
+ sD <= "XXXXXXXX";
+ sD1_msb <= "XXXXXXXX";
+ sD1_lsb <= "XXXXXXXX";
+ sD2_msb <= "XXXXXXXX";
+ sD2_lsb <= "XXXXXXXX";
+
+ end case;
+
+ end if;
+
+ end if;
+
+ end process output_ports;
+
+ -- Set MCLK to drive HP03
+ --
+ mclk_timer: process(clk)
+ begin
+ if clk'event and clk='1' then
+ if mclk_count=763 then
+ mclk_count <= 0;
+ mclk_int <= not mclk_int;
+ else
+ mclk_count <= mclk_count + 1;
+ mclk_int <= mclk_int;
+ end if;
+ end if;
+ end process mclk_timer;
+ MCLK <= mclk_int;
+ --
+ ---------------------------------------------------------------------------------
+
+end rtl;
diff --git a/HP_LAGO.FMT b/HP_LAGO.FMT
new file mode 100644
index 0000000..bdfecc1
--- /dev/null
+++ b/HP_LAGO.FMT
@@ -0,0 +1,735 @@
+ ;***********************************************************
+ ;copyright (c) 2011
+ ;Title: HP03 simple example based on PicoBlaze MCU
+ ;Current version: v1r2
+ ;Function: Calculate pressure, altitude and temperature
+ ;Core: KCPSM3 (Spartan3E version)
+ ;Clock: 50MHz Crystal (Nexys2 clock)
+ ;Author: Horacio Arnaldi
+ ;Company: CAB - IB (CNEA)
+ ;Contact: (+54)-2944-445500
+ ;e-mail: lharnaldi@cab.cnea.gov.ar
+ ;Date: 2011-05-23 v1r1
+ ; 2011-09-14 v1r2
+ ;
+ ;***********************************************************
+ ;
+ ;***********************************************************
+ ;Routine declarations
+ ;***********************************************************
+ ; IIC_ReadCalData ;
+ ; ReadTPAD
+ ; Read_Tempreture
+ ; Read_Pressure
+ ; CalculatePressTemp
+ ; CalculateAltitude
+ ; IIC_ReadByte
+ ; IIC_WriteByte
+ ; IIC_Start
+ ; IIC_Stop
+ ; IIC_ACK
+ ; IIC_NoAck
+ ; IIC_SDA_HIGH
+ ; IIC_SDA_LOW
+ ; IIC_SCL_HIGH
+ ; IIC_SCL_LOW
+ ; IIC_XCLR_LOW
+ ; IIC_XCLR_HIGH
+ ;
+ ;***************************************************
+ ;port definitions
+ ;***************************************************
+ CONSTANT C1_msb_port, 01 ;
+ CONSTANT C1_lsb_port, 02 ;
+ CONSTANT C2_msb_port, 03 ;
+ CONSTANT C2_lsb_port, 04 ;
+ CONSTANT C3_msb_port, 05 ;
+ CONSTANT C3_lsb_port, 06 ;
+ CONSTANT C4_msb_port, 07 ;
+ CONSTANT C4_lsb_port, 08 ;
+ CONSTANT C5_msb_port, 09 ;
+ CONSTANT C5_lsb_port, 0A ;
+ CONSTANT C6_lsb_port, 0B ;
+ CONSTANT C6_msb_port, 0C ;
+ CONSTANT C7_lsb_port, 0D ;
+ CONSTANT C7_msb_port, 0E ;
+ CONSTANT A_port, 0F ;
+ CONSTANT B_port, 10 ;
+ CONSTANT C_port, 11 ;
+ CONSTANT D_port, 12 ;
+ CONSTANT D1_msb_port, 13 ;
+ CONSTANT D1_lsb_port, 14 ;
+ CONSTANT D2_msb_port, 15 ;
+ CONSTANT D2_lsb_port, 16 ;
+ ;
+ CONSTANT IIC_in_port, 20 ; Read signal from HP03 device
+ CONSTANT IIC_out_port, 40 ; Drive signal to HP03 device (open collector)
+ CONSTANT SDA_wire, 01 ; Signal is bit0 in both cases
+ CONSTANT SCL_wire, 02
+ CONSTANT XCLR, 04
+ ;
+ ;
+ ;**************************************************************************************
+ ; Special Register usage
+ ;**************************************************************************************
+ ;
+ NAMEREG sF, UART_data ;used to pass data to and from the UART
+ ;
+ ;
+ ;
+ ;**************************************************
+ ;scratch pad memory locations
+ ;**************************************************
+ ;Values read from EEPROM
+ ;Compensations coefficients and ADC values
+ ;
+ CONSTANT C1_msb, 00 ;Sensitivity coefficient
+ CONSTANT C1_lsb, 01
+ CONSTANT C2_msb, 02 ;Offset coefficient
+ CONSTANT C2_lsb, 03
+ CONSTANT C3_msb, 04 ;Temperature Coefficient of Sensitivity
+ CONSTANT C3_lsb, 05
+ CONSTANT C4_msb, 06 ;Temperature Coefficient of Offset
+ CONSTANT C4_lsb, 07
+ CONSTANT C5_msb, 08 ;Reference Temperature
+ CONSTANT C5_lsb, 09
+ CONSTANT C6_msb, 0A ;Temperature Coefficient of Temperature
+ CONSTANT C6_lsb, 0B
+ CONSTANT C7_msb, 0C ;Offset Fine Tuning
+ CONSTANT C7_lsb, 0D
+ CONSTANT A_A, 0E ;Sensor Specific Parameter
+ CONSTANT B_B, 0F ;Sensor Specific Parameter
+ CONSTANT C_C, 10 ;Sensor Specific Parameter
+ CONSTANT D_D, 11 ;Sensor Specific Parameter
+ CONSTANT D1_msb, 12 ;ADC pressure measured MSB and LSB
+ CONSTANT D1_lsb, 13 ;
+ CONSTANT D2_msb, 14 ;ADC temperature meassured MSB and LSB
+ CONSTANT D2_lsb, 15 ;
+ ;
+ CONSTANT IIC_control_status, 16 ;control status bits
+ ;
+ ;***************************************************
+ ;data constants
+ ;***************************************************
+ ;chip addresses
+ CONSTANT eeprom_addr_A0, A0
+ CONSTANT eeprom_addr_A1, A1
+ CONSTANT eeprom_start_addr, 10
+ CONSTANT AD_addr_EE, EE
+ CONSTANT AD_addr_FF, FF
+ CONSTANT AD_addr_F0, F0
+ CONSTANT AD_addr_E8, E8
+ CONSTANT AD_addr_FD, FD
+ CONSTANT AD_addr_EF, EF
+ ;
+ CONSTANT delay_1us_constant, 0B
+ ;
+ CONSTANT CLR_SCL_MASK, FD
+ CONSTANT CLR_SDA_MASK, FE
+ CONSTANT CLR_XCLR_MASK, FB
+ ;
+ ;*******************************************************************
+ ;main program
+ ;*******************************************************************
+ ; It is in an infinity loop.
+ ; Read constants, send them just once, read ADC values,
+ ; wait a minute and read ADC values again and so on.
+ ; It continuoulsy update external registers to be read from
+ ; other logic.
+ ;******************************************************************
+ cold_start: CALL IIC_init
+ CALL delay_20ms ;initial delay
+ CALL delay_20ms
+ CALL delay_20ms
+ CALL delay_20ms
+ CALL delay_20ms
+ CALL IIC_ReadCalData ;read calibration data
+ ;
+ ;
+ ;Main loop
+ ;
+ warm_start: CALL send_constants ; first of all, send constants
+ loop: CALL read_PTADC ; read AD values
+ CALL delay_1s ; wait for 10 seconds
+ CALL delay_1s
+ CALL delay_1s
+ CALL delay_1s
+ CALL delay_1s
+ CALL delay_1s
+ CALL delay_1s
+ CALL delay_1s
+ CALL delay_1s
+ CALL delay_1s
+ JUMP loop ; do it again!
+ ;
+ ;
+ ;
+ ;***********************************************************
+ ; Initialize IIC bus
+ ;***********************************************************
+ ;
+ ;This routine should be used to initialise the IIC bus.
+ ;The SCL clock is made high.
+ ;Device selections are made inactive as follows
+ ; SDA = 1
+ ; SCL = 1
+ ; XCLR = 0 Initially low
+ ;
+ ;
+ IIC_init: LOAD s0, 03 ;normally 03
+ OUTPUT s0, IIC_out_port
+ STORE s0, IIC_control_status ;preserve status
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;routine: IIC_ReadCalData
+ ; function: read calibration data from eeprom chip
+ ; output register:
+ ;
+ ; temp register: s0
+ ;*******************************************************************
+ ;
+ ;
+ IIC_ReadCalData: CALL IIC_Start ;perform a start condition
+ LOAD s0, eeprom_addr_A0
+ CALL IIC_WriteByte
+ LOAD s0, eeprom_start_addr
+ CALL IIC_WriteByte
+ CALL IIC_Start
+ LOAD s0, eeprom_addr_A1
+ CALL IIC_WriteByte
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C1_msb ;save C1 msb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C1_lsb ;save C1 lsb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C2_msb ;save C2 msb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C2_lsb ;save C2 lsb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C3_msb ;save C3 msb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C3_lsb ;save C3 lsb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C4_msb ;save C4 msb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C4_lsb ;save C4 lsb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C5_msb ;save C5 msb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C5_lsb ;save C5 lsb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C6_msb ;save C6 msb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C6_lsb ;save C6 lsb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C7_msb ;save C7 msb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C7_lsb ;save C7 lsb to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, A_A ;save A_A to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, B_B ;save B_B to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, C_C ;save C_C to mem
+ CALL IIC_ACK
+ ;
+ CALL IIC_ReadByte
+ STORE s0, D_D ;save D_D to mem
+ CALL IIC_NoACK ;no ack
+ CALL IIC_Stop ;stop receibing data
+ ;
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: ReadPTADC
+ ; Function: Read D1 and D2 from HP03
+ ; Input regicter:
+ ; Output register:
+ ;*******************************************************************
+ ;
+ read_PTADC: CALL IIC_XCLR_HIGH ;set XCLR
+ CALL delay_1ms
+ CALL delay_1ms
+ CALL read_pressure ;data in D1_msb, D1_lsb
+ CALL read_temperature ;data in D2_msb, D2_lsb
+ CALL IIC_XCLR_LOW
+ ;
+ send_pressure: FETCH s9, D1_msb
+ OUTPUT s9, D1_msb_port
+ FETCH s8, D1_lsb
+ OUTPUT s8, D1_lsb_port
+ ;
+ ;
+send_temperature: FETCH s9, D2_msb
+ OUTPUT s9, D2_msb_port
+ FETCH s8, D2_lsb
+ OUTPUT s8, D2_lsb_port
+ RETURN
+ ;
+ ;
+ send_constants: FETCH s0, C1_msb
+ OUTPUT s0, C1_msb_port
+ FETCH s0, C1_lsb
+ OUTPUT s0, C1_lsb_port
+ ;
+ ;
+ FETCH s0, C2_msb
+ OUTPUT s0, C2_msb_port
+ FETCH s0, C2_lsb
+ OUTPUT s0, C2_lsb_port
+ ;
+ ;
+ FETCH s0, C3_msb
+ OUTPUT s0, C3_msb_port
+ FETCH s0, C3_lsb
+ OUTPUT s0, C3_lsb_port
+ ;
+ ;
+ FETCH s0, C4_msb
+ OUTPUT s0, C4_msb_port
+ FETCH s0, C4_lsb
+ OUTPUT s0, C4_lsb_port
+ ;
+ ;
+ FETCH s0, C5_msb
+ OUTPUT s0, C5_msb_port
+ FETCH s0, C5_lsb
+ OUTPUT s0, C5_lsb_port
+ ;
+ ;
+ FETCH s0, C6_msb
+ OUTPUT s0, C6_msb_port
+ FETCH s0, C6_lsb
+ OUTPUT s0, C6_lsb_port
+ ;
+ ;
+ FETCH s0, C7_msb
+ OUTPUT s0, C7_msb_port
+ FETCH s0, C7_lsb
+ OUTPUT s0, C7_lsb_port
+ ;
+ ;
+ FETCH s0, A_A
+ OUTPUT s0, A_port
+ ;
+ ;
+ FETCH s0, B_B
+ OUTPUT s0, B_port
+ ;
+ ;
+ FETCH s0, C_C
+ OUTPUT s0, C_port
+ ;
+ ;
+ FETCH s0, D_D
+ OUTPUT s0, D_port
+ ;
+ ;
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: Read_pressure
+ ; Function: read pressure value from HP03
+ ; Store result in D1_msb and D1_lsb registers
+ ; Output register: D1_msb, D1_lsb
+ ; Temp register: s0
+ ;*******************************************************************
+ ;
+ read_pressure: CALL IIC_Start ;perform start condition
+ LOAD s0, AD_addr_EE ;write EE address
+ CALL IIC_WriteByte
+ LOAD s0, AD_addr_FF ;write FF address
+ CALL IIC_WriteByte
+ LOAD s0, AD_addr_F0 ;write F0 address
+ CALL IIC_WriteByte
+ CALL IIC_Stop
+ CALL delay_20ms ;
+ CALL delay_20ms
+ CALL IIC_Start
+ LOAD s0, AD_addr_EE ;write EE address
+ CALL IIC_WriteByte
+ LOAD s0, AD_addr_FD ;write FD address
+ CALL IIC_WriteByte
+ CALL IIC_Start
+ LOAD s0, AD_addr_EF ;write EF address
+ CALL IIC_WriteByte
+ CALL IIC_ReadByte ;read pressure MSB
+ STORE s0, D1_msb ;save MSB in D1_msb register
+ CALL IIC_ACK
+ CALL IIC_ReadByte ;read pressure LSB
+ STORE s0, D1_lsb ;save LSB in D1_lsb register
+ CALL IIC_NoACK
+ CALL IIC_Stop
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: Read_temperature
+ ; Function: read pressure value from HP03
+ ; Store result in D2_msb and D2_lsb registers
+ ; Output register: D2_msb, D2_lsb
+ ; Temp register: s0
+ ;*******************************************************************
+ ;
+read_temperature: CALL IIC_Start ;perform start condition
+ LOAD s0, AD_addr_EE ;write EE address
+ CALL IIC_WriteByte
+ LOAD s0, AD_addr_FF ;write FF address
+ CALL IIC_WriteByte
+ LOAD s0, AD_addr_E8 ;write E8 address
+ CALL IIC_WriteByte
+ CALL IIC_Stop
+ CALL delay_20ms ;
+ CALL delay_20ms ;
+ CALL IIC_Start
+ LOAD s0, AD_addr_EE ;write EE address
+ CALL IIC_WriteByte
+ LOAD s0, AD_addr_FD ;write FD address
+ CALL IIC_WriteByte
+ CALL IIC_Start
+ LOAD s0, AD_addr_EF ;write EF address
+ CALL IIC_WriteByte
+ CALL IIC_ReadByte ;read temperature MSB
+ STORE s0, D2_msb ;save MSB in D2_msb register
+ CALL IIC_ACK
+ CALL IIC_ReadByte ;read temperature LSB
+ STORE s0, D2_lsb ;save LSB in D2_lsb register
+ CALL IIC_NoACK
+ CALL IIC_Stop
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_ReadByte
+ ; function: Read a byte from iic chips
+ ; output register: s0
+ ;
+ ; temp register: s2, s3
+ ;*******************************************************************
+ ;
+ IIC_ReadByte: CALL IIC_SDA_HIGH ;set SDA
+ CALL delay_10us ;wait 10 us
+ LOAD s3, 08 ;load index for 8 bits
+ IIC_Read_Next: INPUT s2, IIC_in_port
+ TEST s2, SDA_wire ;test SDA state, status -> carry
+ SLA s0 ;Carry shifted into LSBit
+ CALL IIC_SCL_LOW ;
+ CALL delay_10us ;wait 10 us
+ CALL IIC_SCL_HIGH ;
+ CALL delay_10us ;wait 10 us
+ CALL delay_10us
+ CALL IIC_SCL_LOW
+ CALL delay_10us
+ SUB s3, 01
+ JUMP NZ, IIC_Read_Next
+ RETURN
+ ;
+ ;
+ ;************************************************************************
+ ;Routine: IIC_WriteByte
+ ; function: write a byte to iic chips
+ ; input register: s0
+ ;
+ ; temp register: s2
+ ;*******************************************************************
+ IIC_WriteByte: LOAD s2, 08 ;initialize loop index to 8
+ ;
+ IIC_Write_Next: CALL IIC_SCL_LOW
+ CALL delay_10us
+ SL0 s0 ; Move data bit -> carry
+ JUMP C, IIC_Send1 ; Jump if bit high
+ ;
+ IIC_Send0: CALL IIC_SDA_LOW ; Set to output, data low so SDA = 0
+ CALL delay_10us ; reflect in output
+ JUMP I2C_Sx ; Jump over next instruction
+ ;
+ IIC_Send1: CALL IIC_SDA_HIGH ; Set to input, SDA = 1 due to pull-up
+ CALL delay_10us ; reflect in output
+ ;
+ I2C_Sx: CALL IIC_SCL_HIGH
+ CALL delay_10us
+ CALL IIC_SCL_LOW
+ SUB s2, 01 ; Decrement I2C bit counter
+ JUMP NZ, IIC_Write_Next ; Loop until 8 bits are sent
+ ;
+ CALL IIC_SDA_HIGH
+ CALL delay_10us
+ CALL IIC_SCL_LOW
+ CALL delay_10us
+ CALL IIC_SCL_HIGH
+ CALL delay_10us
+ CALL IIC_SCL_LOW
+ CALL delay_10us
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_Start
+ ; function: perform a start condition
+ ;*******************************************************************
+ IIC_Start: CALL IIC_SDA_HIGH
+ CALL delay_10us
+ CALL IIC_SCL_HIGH
+ CALL delay_10us
+ CALL IIC_SDA_LOW
+ CALL delay_10us
+ CALL IIC_SCL_LOW
+ CALL delay_10us
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_Stop
+ ; function: perform a stop condition
+ ;*******************************************************************
+ IIC_Stop: CALL IIC_SCL_LOW
+ CALL delay_10us
+ CALL IIC_SDA_LOW
+ CALL delay_10us
+ CALL IIC_SCL_HIGH
+ CALL delay_10us
+ CALL IIC_SDA_HIGH
+ CALL delay_10us
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_ACK
+ ; function: perform an ack condition
+ ;*******************************************************************
+ IIC_ACK: CALL IIC_SDA_LOW
+ CALL delay_10us
+ CALL IIC_SCL_HIGH
+ CALL delay_10us
+ CALL IIC_SCL_LOW
+ CALL delay_10us
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_NoACK
+ ; function: perform an nack condition
+ ;*******************************************************************
+ IIC_NoACK: CALL IIC_SDA_HIGH
+ CALL delay_10us
+ CALL IIC_SCL_HIGH
+ CALL delay_10us
+ CALL IIC_SCL_LOW
+ CALL delay_10us
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_SDA_HIGH
+ ; function: set SDA
+ ; input register: IIC_control_status
+ ; output register: IIC_port
+ ;
+ ; temp register: s1
+ ;*******************************************************************
+ IIC_SDA_HIGH: FETCH s1, IIC_control_status ;read control status bits
+ OR s1, SDA_wire ;set SDA pin
+ OUTPUT s1, IIC_out_port
+ STORE s1, IIC_control_status ;preserve status
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_SDA_LOW
+ ; function: clear SDA
+ ; input register: IIC_control_status
+ ; output register: IIC_out_port
+ ;
+ ; temp register: s1
+ ;*******************************************************************
+ IIC_SDA_LOW: FETCH s1, IIC_control_status ;read control status bits
+ AND s1, CLR_SDA_MASK ;clear SDA pin
+ OUTPUT s1, IIC_out_port
+ STORE s1, IIC_control_status ;preserve status
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_SCL_HIGH
+ ; function: set SCL
+ ; input register: s0
+ ; output register:
+ ;
+ ; temp register: i
+ ;*******************************************************************
+ IIC_SCL_HIGH: FETCH s1, IIC_control_status ;read control status bits
+ OR s1, SCL_wire ;set SCL pin
+ OUTPUT s1, IIC_out_port
+ STORE s1, IIC_control_status ;preserve status
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_SCL_LOW
+ ; function: set SDA
+ ; temp register: s1
+ ;*******************************************************************
+ IIC_SCL_LOW: FETCH s1, IIC_control_status ;read control status bits
+ AND s1, CLR_SCL_MASK ;clear SCL pin
+ OUTPUT s1, IIC_out_port
+ STORE s1, IIC_control_status ;preserve status
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_XCLR_HIGH
+ ; function: set XCLR
+ ; input register: s0
+ ; output register:
+ ;
+ ; temp register: i
+ ;*******************************************************************
+ IIC_XCLR_HIGH: FETCH s1, IIC_control_status ;read control status bits
+ OR s1, XCLR ;set XCLR pin
+ OUTPUT s1, IIC_out_port
+ STORE s1, IIC_control_status ;preserve status
+ RETURN
+ ;
+ ;
+ ;*******************************************************************
+ ;Routine: IIC_XCLR_LOW
+ ; function: clear XCLR
+ ; input register: s0
+ ; output register:
+ ;
+ ; temp register: i
+ ;*******************************************************************
+ IIC_XCLR_LOW: FETCH s1, IIC_control_status ;read control status bits
+ AND s1, CLR_XCLR_MASK ;clear SCL pin
+ OUTPUT s1, IIC_out_port
+ STORE s1, IIC_control_status ;preserve status
+ RETURN
+ ;
+ ;
+ ;**************************************************************************************
+ ; Software delay Routines
+ ;**************************************************************************************
+ ;
+ ; Delay of 1us.
+ ;
+ ; Constant value defines reflects the clock applied to KCPSM3. Every instruction
+ ; executes in 2 clock cycles making the calculation highly predictable. The '6' in
+ ; the following equation even allows for 'CALL delay_1us' instruction in the initiating code.
+ ;
+ ; delay_1us_constant = (clock_rate - 6)/4 Where 'clock_rate' is in MHz
+ ;
+ ; Register used sA
+ ;
+ delay_1us: LOAD sA, delay_1us_constant
+ wait_1us: SUB sA, 01
+ JUMP NZ, wait_1us
+ RETURN
+ ;
+ ; Delay of 10 us
+ ;
+ ; Registers used sA, sB
+ ;
+ delay_10us: LOAD sB, 0A ;10 x 1us = 10us
+ wait_10us: CALL delay_1us
+ SUB sB, 01
+ JUMP NZ, wait_10us
+ RETURN
+ ;
+ ; Delay of 40us.
+ ;
+ ; Registers used sA, sB
+ ;
+ delay_40us: LOAD sB, 28 ;40 x 1us = 40us
+ wait_40us: CALL delay_1us
+ SUB sB, 01
+ JUMP NZ, wait_40us
+ RETURN
+ ;
+ ;
+ ; Delay of 1ms.
+ ;
+ ; Registers used sA, sB, sC
+ ;
+ delay_1ms: LOAD sC, 19 ;25 x 40us = 1ms
+ wait_1ms: CALL delay_40us
+ SUB sC, 01
+ JUMP NZ, wait_1ms
+ RETURN
+ ;
+ ; Delay of 20ms.
+ ;
+ ; Registers used sA, sB, sC, sD
+ ;
+ delay_20ms: LOAD sD, 14 ;20 x 1ms = 20ms
+ wait_20ms: CALL delay_1ms
+ SUB sD, 01
+ JUMP NZ, wait_20ms
+ RETURN
+ ;
+ ; Delay of approximately 1 second.
+ ;
+ ; Registers used sA, sB, sC, sD, sE
+ ;
+ delay_1s: LOAD sE, 14 ;50 x 20ms = 1000ms
+ wait_1s: CALL delay_20ms
+ SUB sE, 01
+ JUMP NZ, wait_1s
+ RETURN
+ ;
+ ;
+ ;
+ ;**************************************************************************************
+ ; Interrupt Service Routine (ISR)
+ ;**************************************************************************************
+ ;
+ ; Interrupts are not used in this design. This is a place keeper only.
+ ;
+ ADDRESS 3FE
+ ISR: RETURNI ENABLE
+ ;
+ ;
+ ;**************************************************************************************
+ ; Interrupt Vector
+ ;**************************************************************************************
+ ;
+ ADDRESS 3FF
+ JUMP ISR
+ ;
+ ;
diff --git a/HP_LAGO.VHD b/HP_LAGO.VHD
new file mode 100755
index 0000000..abcfb17
--- /dev/null
+++ b/HP_LAGO.VHD
@@ -0,0 +1,274 @@
+--
+-- Definition of a single port ROM for KCPSM3 program defined by hp_lago.psm
+--
+-- Generated by KCPSM3 Assembler 03Oct2011-14:33:25.
+--
+-- Standard IEEE libraries
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library unisim;
+use unisim.vcomponents.all;
+--
+--
+entity hp_lago is
+ Port ( address : in std_logic_vector(9 downto 0);
+ instruction : out std_logic_vector(17 downto 0);
+ clk : in std_logic);
+ end hp_lago;
+--
+architecture low_level_definition of hp_lago is
+--
+-- Attributes to define ROM contents during implementation synthesis.
+-- The information is repeated in the generic map for functional simulation
+--
+attribute INIT_00 : string;
+attribute INIT_01 : string;
+attribute INIT_02 : string;
+attribute INIT_03 : string;
+attribute INIT_04 : string;
+attribute INIT_05 : string;
+attribute INIT_06 : string;
+attribute INIT_07 : string;
+attribute INIT_08 : string;
+attribute INIT_09 : string;
+attribute INIT_0A : string;
+attribute INIT_0B : string;
+attribute INIT_0C : string;
+attribute INIT_0D : string;
+attribute INIT_0E : string;
+attribute INIT_0F : string;
+attribute INIT_10 : string;
+attribute INIT_11 : string;
+attribute INIT_12 : string;
+attribute INIT_13 : string;
+attribute INIT_14 : string;
+attribute INIT_15 : string;
+attribute INIT_16 : string;
+attribute INIT_17 : string;
+attribute INIT_18 : string;
+attribute INIT_19 : string;
+attribute INIT_1A : string;
+attribute INIT_1B : string;
+attribute INIT_1C : string;
+attribute INIT_1D : string;
+attribute INIT_1E : string;
+attribute INIT_1F : string;
+attribute INIT_20 : string;
+attribute INIT_21 : string;
+attribute INIT_22 : string;
+attribute INIT_23 : string;
+attribute INIT_24 : string;
+attribute INIT_25 : string;
+attribute INIT_26 : string;
+attribute INIT_27 : string;
+attribute INIT_28 : string;
+attribute INIT_29 : string;
+attribute INIT_2A : string;
+attribute INIT_2B : string;
+attribute INIT_2C : string;
+attribute INIT_2D : string;
+attribute INIT_2E : string;
+attribute INIT_2F : string;
+attribute INIT_30 : string;
+attribute INIT_31 : string;
+attribute INIT_32 : string;
+attribute INIT_33 : string;
+attribute INIT_34 : string;
+attribute INIT_35 : string;
+attribute INIT_36 : string;
+attribute INIT_37 : string;
+attribute INIT_38 : string;
+attribute INIT_39 : string;
+attribute INIT_3A : string;
+attribute INIT_3B : string;
+attribute INIT_3C : string;
+attribute INIT_3D : string;
+attribute INIT_3E : string;
+attribute INIT_3F : string;
+attribute INITP_00 : string;
+attribute INITP_01 : string;
+attribute INITP_02 : string;
+attribute INITP_03 : string;
+attribute INITP_04 : string;
+attribute INITP_05 : string;
+attribute INITP_06 : string;
+attribute INITP_07 : string;
+--
+-- Attributes to define ROM contents during implementation synthesis.
+--
+attribute INIT_00 of ram_1024_x_18 : label is "00DFA000E016C040000340080135004F005E000F01300130013001300130000B";
+attribute INIT_01 of ram_1024_x_18 : label is "00F1E00200B700F1E00100B700F1E00000B700C700A100DF00C7001000C700A0";
+attribute INIT_02 of ram_1024_x_18 : label is "00B700F1E00700B700F1E00600B700F1E00500B700F1E00400B700F1E00300B7";
+attribute INIT_03 of ram_1024_x_18 : label is "E00D00B700F1E00C00B700F1E00B00B700F1E00A00B700F1E00900B700F1E008";
+attribute INIT_04 of ram_1024_x_18 : label is "0113A00000E800F8E01100B700F1E01000B700F1E00F00B700F1E00E00B700F1";
+attribute INIT_05 of ram_1024_x_18 : label is "C0016000A000C8166815C9156914C8146813C91369120118009D0083012B012B";
+attribute INIT_06 of ram_1024_x_18 : label is "C0096008C0086007C0076006C0066005C0056004C0046003C0036002C0026001";
+attribute INIT_07 of ram_1024_x_18 : label is "C0116010C010600FC00F600EC00D600DC00E600CC00B600BC00C600AC00A6009";
+attribute INIT_08 of ram_1024_x_18 : label is "00C700EE00DF0130013000E800C700F000C700FF00C700EE00DFA000C0126011";
+attribute INIT_09 of ram_1024_x_18 : label is "00C700EE00DFA00000E800F8E01300B700F1E01200B700C700EF00DF00C700FD";
+attribute INIT_0A of ram_1024_x_18 : label is "00B700C700EF00DF00C700FD00C700EE00DF0130013000E800C700E800C700FF";
+attribute INIT_0B of ram_1024_x_18 : label is "01090121010E0000220142200308012100FFA00000E800F8E01500B700F1E014";
+attribute INIT_0C of ram_1024_x_18 : label is "00FF40D10121010458CF00060121010E0208A00054BAC3010121010E01210121";
+attribute INIT_0D of ram_1024_x_18 : label is "00FFA0000121010E012101090121010E012100FF54C8C201010E012101090121";
+attribute INIT_0E of ram_1024_x_18 : label is "012100FF01210109012101040121010EA0000121010E01210104012101090121";
+attribute INIT_0F of ram_1024_x_18 : label is "6116A0000121010E01210109012100FFA0000121010E0121010901210104A000";
+attribute INIT_10 of ram_1024_x_18 : label is "A1FD6116A000E116C140C1026116A000E116C140A1FE6116A000E116C140C101";
+attribute INIT_11 of ram_1024_x_18 : label is "551ECA010A0BA000E116C140A1FB6116A000E116C140C1046116A000E116C140";
+attribute INIT_12 of ram_1024_x_18 : label is "A000552CCC0101260C19A0005527CB01011D0B28A0005522CB01011D0B0AA000";
+attribute INIT_13 of ram_1024_x_18 : label is "000000000000000000000000A0005536CE0101300E14A0005531CD01012B0D14";
+attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INIT_3F of ram_1024_x_18 : label is "43FE800100000000000000000000000000000000000000000000000000000000";
+attribute INITP_00 of ram_1024_x_18 : label is "88888888888888888A2223FFEFBEFBEFBEFBEFBEFBEFBEFBEFBEF3CCEA3FFFFF";
+attribute INITP_01 of ram_1024_x_18 : label is "2FFFBFFEFFFFBFFFEFFFFDFFFFEF2DFFFE43EFBEF3CCFFCCCEFBEF3CCFFCCCE8";
+attribute INITP_02 of ram_1024_x_18 : label is "00000000000000000000000000000000000B72DCB72DCB72D2A0A82A0A82A0A8";
+attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
+attribute INITP_07 of ram_1024_x_18 : label is "F000000000000000000000000000000000000000000000000000000000000000";
+--
+begin
+--
+ --Instantiate the Xilinx primitive for a block RAM
+ ram_1024_x_18: RAMB16_S18
+ --synthesis translate_off
+ --INIT values repeated to define contents for functional simulation
+ generic map ( INIT_00 => X"00DFA000E016C040000340080135004F005E000F01300130013001300130000B",
+ INIT_01 => X"00F1E00200B700F1E00100B700F1E00000B700C700A100DF00C7001000C700A0",
+ INIT_02 => X"00B700F1E00700B700F1E00600B700F1E00500B700F1E00400B700F1E00300B7",
+ INIT_03 => X"E00D00B700F1E00C00B700F1E00B00B700F1E00A00B700F1E00900B700F1E008",
+ INIT_04 => X"0113A00000E800F8E01100B700F1E01000B700F1E00F00B700F1E00E00B700F1",
+ INIT_05 => X"C0016000A000C8166815C9156914C8146813C91369120118009D0083012B012B",
+ INIT_06 => X"C0096008C0086007C0076006C0066005C0056004C0046003C0036002C0026001",
+ INIT_07 => X"C0116010C010600FC00F600EC00D600DC00E600CC00B600BC00C600AC00A6009",
+ INIT_08 => X"00C700EE00DF0130013000E800C700F000C700FF00C700EE00DFA000C0126011",
+ INIT_09 => X"00C700EE00DFA00000E800F8E01300B700F1E01200B700C700EF00DF00C700FD",
+ INIT_0A => X"00B700C700EF00DF00C700FD00C700EE00DF0130013000E800C700E800C700FF",
+ INIT_0B => X"01090121010E0000220142200308012100FFA00000E800F8E01500B700F1E014",
+ INIT_0C => X"00FF40D10121010458CF00060121010E0208A00054BAC3010121010E01210121",
+ INIT_0D => X"00FFA0000121010E012101090121010E012100FF54C8C201010E012101090121",
+ INIT_0E => X"012100FF01210109012101040121010EA0000121010E01210104012101090121",
+ INIT_0F => X"6116A0000121010E01210109012100FFA0000121010E0121010901210104A000",
+ INIT_10 => X"A1FD6116A000E116C140C1026116A000E116C140A1FE6116A000E116C140C101",
+ INIT_11 => X"551ECA010A0BA000E116C140A1FB6116A000E116C140C1046116A000E116C140",
+ INIT_12 => X"A000552CCC0101260C19A0005527CB01011D0B28A0005522CB01011D0B0AA000",
+ INIT_13 => X"000000000000000000000000A0005536CE0101300E14A0005531CD01012B0D14",
+ INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INIT_3F => X"43FE800100000000000000000000000000000000000000000000000000000000",
+ INITP_00 => X"88888888888888888A2223FFEFBEFBEFBEFBEFBEFBEFBEFBEFBEF3CCEA3FFFFF",
+ INITP_01 => X"2FFFBFFEFFFFBFFFEFFFFDFFFFEF2DFFFE43EFBEF3CCFFCCCEFBEF3CCFFCCCE8",
+ INITP_02 => X"00000000000000000000000000000000000B72DCB72DCB72D2A0A82A0A82A0A8",
+ INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+ INITP_07 => X"F000000000000000000000000000000000000000000000000000000000000000")
+ --synthesis translate_on
+ port map( DI => "0000000000000000",
+ DIP => "00",
+ EN => '1',
+ WE => '0',
+ SSR => '0',
+ CLK => clk,
+ ADDR => address,
+ DO => instruction(15 downto 0),
+ DOP => instruction(17 downto 16));
+--
+end low_level_definition;
+--
+------------------------------------------------------------------------------------
+--
+-- END OF FILE hp_lago.vhd
+--
+------------------------------------------------------------------------------------
diff --git a/Makefile b/Makefile
new file mode 100755
index 0000000..c5f3e51
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,94 @@
+#========================================================
+# Makefile para crear firmwares para las placas Nexys2 =
+# =
+# Es necesario correr al menos una vez el proyecto en =
+# soft ISE de Xilinx y luego, a partir de allà realizar =
+# proyectos con este make. =
+# Para seleccionar si se quiere grabar el firmware en =
+# la FPGA o en la memoria EEPROM, es necesario correr =
+# =
+# make STARTUP_CLK=x =
+# Donde x puede ser jtag o cclk =
+# =
+# Horacio Arnaldi =
+# DPR Lab =
+# 05/12/2011 =
+# Última revisión: 19/01/2012 =
+# =
+#========================================================
+TOP_LEVEL = lago_fpga_vhdl
+GATES = 500
+PLATFORM = nexys2_$(GATES)
+STARTUP_CLK = jtag
+
+ifeq ($(PLATFORM),nexys2_500)
+ FPGA = xc3s500e-fg320-4
+endif
+ifeq ($(PLATFORM),nexys2_1200)
+ FPGA = xc3s1200e-fg320-4
+endif
+ifeq ($(STARTUP_CLK),jtag)
+ CLOCK = JtagClk
+
+endif
+ifeq ($(STARTUP_CLK),cclk)
+ CLOCK = CClk
+endif
+
+all: $(TOP_LEVEL).xsvf
+
+report: $(TOP_LEVEL).twr
+
+# This assumes that the "XILINX" environment variable is set
+$(TOP_LEVEL).xsvf: $(PLATFORM).batch $(TOP_LEVEL).bit
+ cat $< | sed s#\$${XILINX}#$(subst \,/,$(XILINX))#g > temp.batch
+ impact -batch temp.batch
+ rm -f temp.batch
+
+$(TOP_LEVEL).bit: $(TOP_LEVEL).ut $(TOP_LEVEL).ncd
+ bitgen -intstyle ise -f $+
+
+$(TOP_LEVEL).twr: $(TOP_LEVEL).ncd $(TOP_LEVEL).ucf
+ trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml ${TOP_LEVEL}.twx $< -o $@ ${TOP_LEVEL}.pcf -ucf $(TOP_LEVEL).ucf
+
+$(TOP_LEVEL).ncd: $(TOP_LEVEL)_map.ncd
+ par -w -intstyle ise -ol high -t 1 $< $@ ${TOP_LEVEL}.pcf
+
+$(TOP_LEVEL)_map.ncd: $(TOP_LEVEL).ngd
+ map -intstyle ise -p $(FPGA) -cm area -ir off -pr off -c 100 -o $@ $< ${TOP_LEVEL}.pcf
+
+$(TOP_LEVEL).ngd: $(TOP_LEVEL).ngc $(TOP_LEVEL).ucf
+ ngdbuild -intstyle ise -dd _ngo -sd ipcore_dir -nt timestamp -uc $(TOP_LEVEL).ucf -p $(FPGA) $< $@
+
+$(TOP_LEVEL).ngc: $(TOP_LEVEL).xst $(TOP_LEVEL).prj
+ mkdir -p xst/projnav.tmp
+ xst -intstyle ise -ifn $< -ofn $(TOP_LEVEL).syr
+
+$(TOP_LEVEL).ut:
+ echo "-w" > $@
+ echo "-g DebugBitstream:No" >> $@
+ echo "-g Binary:no" >> $@
+ echo "-g CRC:Enable" >> $@
+ echo "-g ConfigRate:1" >> $@
+ echo "-g ProgPin:PullUp" >> $@
+ echo "-g DonePin:PullUp" >> $@
+ echo "-g TckPin:PullUp" >> $@
+ echo "-g TdiPin:PullUp" >> $@
+ echo "-g TdoPin:PullUp" >> $@
+ echo "-g TmsPin:PullUp" >> $@
+ echo "-g UnusedPin:PullDown" >> $@
+ echo "-g UserID:0xFFFFFFFF" >> $@
+ echo "-g DCMShutdown:Disable" >> $@
+ echo "-g StartUpClk:$(CLOCK)" >> $@
+ echo "-g DONE_cycle:4" >> $@
+ echo "-g GTS_cycle:5" >> $@
+ echo "-g GWE_cycle:6" >> $@
+ echo "-g LCK_cycle:NoWait" >> $@
+ echo "-g Security:None" >> $@
+ echo "-g DonePipe:No" >> $@
+ echo "-g DriveDone:No" >> $@
+
+clean: FORCE
+ rm -rf *.ut *.xsvf *.csvf _ngo *.bgn *.drc *.ncd *.ntrc_log *.twr *.csv *.html fx2fpga_xdb _xmsgs *.bit *.gise *.ngc *.pad *.ptwx *.twx *.ngm *.txt *.xml *.xrpt *.bld *.ise *.ngd *.par *.stx *.map *.twr auto_project_xdb *.cmd_log *.lso *.ngr *.pcf *.syr *.unroutes *.xpi *.mrp xst *.log *.cmd *.xwbt iseconfig xlnx_auto_0_xdb
+
+FORCE:
diff --git a/baseline.vhd b/baseline.vhd
new file mode 100644
index 0000000..43ab3ae
--- /dev/null
+++ b/baseline.vhd
@@ -0,0 +1,142 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+--
+entity baseline_control is
+ generic(
+ W : natural; --:=5; -- numero de bits de direcciones. 2**W = 32 direcciones para W=5
+ ADCBITS : natural; -- := 10; -- numero de bits en los datos
+ RBITS : natural; -- := 12; -- numero de bits de los registros
+ REFRESH_RATE : natural; -- := 80000; -- 80000 clk implican un refresh rate de 2ms (80000 * 25 ns = 2ms)
+ NCH : natural --:= 3 -- numero de canales de la electronica
+ );
+
+ port(
+ clk_40mhz : in std_logic;
+ reset : in std_logic;
+ ptick_2ms : out std_logic;
+ data_adc1 : in std_logic_vector(ADCBITS-1 downto 0);
+ data_adc2 : in std_logic_vector(ADCBITS-1 downto 0);
+ data_adc3 : in std_logic_vector(ADCBITS-1 downto 0);
+ baseline1 : out std_logic_vector(RBITS-1 downto 0);
+ baseline2 : out std_logic_vector(RBITS-1 downto 0);
+ baseline3 : out std_logic_vector(RBITS-1 downto 0)
+ );
+end baseline_control;
+
+architecture rtl of baseline_control is
+
+ signal cont_promedio_reg, cont_promedio_next : unsigned((2**W-1) downto 0);
+ signal adc1_sum_reg, adc1_sum_next : unsigned((2**W-1) downto 0);
+ signal adc2_sum_reg, adc2_sum_next : unsigned((2**W-1) downto 0);
+ signal adc3_sum_reg, adc3_sum_next : unsigned((2**W-1) downto 0);
+ signal adc1_prom_reg, adc1_prom_next : unsigned((2**W-1) downto 0);
+ signal adc2_prom_reg, adc2_prom_next : unsigned((2**W-1) downto 0);
+ signal adc3_prom_reg, adc3_prom_next : unsigned((2**W-1) downto 0);
+ signal baseline1_buff_reg, baseline1_buff_next : unsigned((RBITS-1) downto 0);
+ signal baseline2_buff_reg, baseline2_buff_next : unsigned((RBITS-1) downto 0);
+ signal baseline3_buff_reg, baseline3_buff_next : unsigned((RBITS-1) downto 0);
+ signal max_tick : std_logic;
+
+begin
+
+ ptick_2ms <= max_tick;
+ --registers
+ process(clk_40mhz, reset)
+ begin
+ if (reset = '1') then
+ cont_promedio_reg <= (others => '0');
+ adc1_sum_reg <= (others => '0');
+ adc2_sum_reg <= (others => '0');
+ adc3_sum_reg <= (others => '0');
+ adc1_prom_reg <= (others => '0');
+ adc2_prom_reg <= (others => '0');
+ adc3_prom_reg <= (others => '0');
+ baseline1_buff_reg <= (others => '0');
+ baseline2_buff_reg <= (others => '0');
+ baseline3_buff_reg <= (others => '0');
+ elsif (clk_40mhz'event and clk_40mhz = '1') then
+ cont_promedio_reg <= cont_promedio_next;
+ adc1_sum_reg <= adc1_sum_next;
+ adc2_sum_reg <= adc2_sum_next;
+ adc3_sum_reg <= adc3_sum_next;
+ adc1_prom_reg <= adc1_prom_next;
+ adc2_prom_reg <= adc2_prom_next;
+ adc3_prom_reg <= adc3_prom_next;
+ baseline1_buff_reg <= baseline1_buff_next;
+ baseline2_buff_reg <= baseline2_buff_next;
+ baseline3_buff_reg <= baseline3_buff_next;
+ end if;
+ end process;
+
+ --next state logic
+ cont_promedio_next <= (others => '0') when (cont_promedio_reg = (REFRESH_RATE-1)) else
+ cont_promedio_reg + 1;
+
+ max_tick <= '1' when (cont_promedio_reg = (REFRESH_RATE-1)) else '0';
+
+ adc1_sum_next <= (others => '0') when (max_tick = '1') else
+ adc1_sum_reg + unsigned(data_adc1);
+ adc2_sum_next <= (others => '0') when (max_tick = '1') else
+ adc2_sum_reg + unsigned(data_adc2);
+ adc3_sum_next <= (others => '0') when (max_tick = '1') else
+ adc3_sum_reg + unsigned(data_adc3);
+
+ adc1_prom_next <= adc1_sum_reg when (max_tick = '1') else
+ adc1_prom_reg;
+ adc2_prom_next <= adc2_sum_reg when (max_tick = '1') else
+ adc2_prom_reg;
+ adc3_prom_next <= adc3_sum_reg when (max_tick = '1') else
+ adc3_prom_reg;
+
+ process(max_tick, adc1_prom_reg)
+ begin
+ if (max_tick = '1') then
+ if (adc1_prom_reg > 4000000) then --4000000 = 50*80000, con 50 el nivel de baseline buscado
+ baseline1_buff_next <= baseline1_buff_reg + 1;
+ elsif (adc1_prom_reg < 4000000) then
+ baseline1_buff_next <= baseline1_buff_reg - 1;
+ else
+ baseline1_buff_next <= baseline1_buff_reg;
+ end if;
+ else
+ baseline1_buff_next <= baseline1_buff_reg;
+ end if;
+ end process;
+
+ process(max_tick, adc2_prom_reg)
+ begin
+ if (max_tick = '1') then
+ if (adc2_prom_reg > 4000000) then
+ baseline2_buff_next <= baseline2_buff_reg + 1;
+ elsif (adc2_prom_reg < 4000000) then
+ baseline2_buff_next <= baseline2_buff_reg - 1;
+ else
+ baseline2_buff_next <= baseline2_buff_reg;
+ end if;
+ else
+ baseline2_buff_next <= baseline2_buff_reg;
+ end if;
+ end process;
+
+ process(max_tick, adc3_prom_reg)
+ begin
+ if (max_tick = '1') then
+ if (adc3_prom_reg > 4000000) then
+ baseline3_buff_next <= baseline3_buff_reg + 1;
+ elsif (adc3_prom_reg < 4000000) then
+ baseline3_buff_next <= baseline3_buff_reg - 1;
+ else
+ baseline3_buff_next <= baseline3_buff_reg;
+ end if;
+ else
+ baseline3_buff_next <= baseline3_buff_reg;
+ end if;
+ end process;
+
+ -- output
+ baseline1 <= std_logic_vector(baseline1_buff_reg);
+ baseline2 <= std_logic_vector(baseline2_buff_reg);
+ baseline3 <= std_logic_vector(baseline3_buff_reg);
+
+end architecture;
diff --git a/baseline_control.prj b/baseline_control.prj
new file mode 100644
index 0000000..17d52a9
--- /dev/null
+++ b/baseline_control.prj
@@ -0,0 +1 @@
+vhdl work "baseline.vhd"
diff --git a/baseline_control.xst b/baseline_control.xst
new file mode 100644
index 0000000..e87063a
--- /dev/null
+++ b/baseline_control.xst
@@ -0,0 +1,5 @@
+set -tmpdir "/home/horacio/work/lago/lago-fpga-vhdl/xst/projnav.tmp"
+set -xsthdpdir "/home/horacio/work/lago/lago-fpga-vhdl/xst"
+elaborate
+-ifn baseline_control.prj
+-ifmt mixed
diff --git a/bbfifo_16x8.vhd b/bbfifo_16x8.vhd
new file mode 100644
index 0000000..8ef61e6
--- /dev/null
+++ b/bbfifo_16x8.vhd
@@ -0,0 +1,281 @@
+-- 'Bucket Brigade' FIFO
+-- 16 deep
+-- 8-bit data
+--
+-- Version : 1.10
+-- Version Date : 3rd December 2003
+-- Reason : '--translate' directives changed to '--synthesis translate' directives
+--
+-- Version : 1.00
+-- Version Date : 14th October 2002
+--
+-- Start of design entry : 14th October 2002
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Futhermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for BBFIFO_16x8
+--
+entity bbfifo_16x8 is
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ reset : in std_logic;
+ write : in std_logic;
+ read : in std_logic;
+ full : out std_logic;
+ half_full : out std_logic;
+ data_present : out std_logic;
+ clk : in std_logic);
+ end bbfifo_16x8;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for BBFIFO_16x8
+--
+architecture low_level_definition of bbfifo_16x8 is
+--
+------------------------------------------------------------------------------------
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in BBFIFO_16x8
+--
+------------------------------------------------------------------------------------
+--
+signal pointer : std_logic_vector(3 downto 0);
+signal next_count : std_logic_vector(3 downto 0);
+signal half_count : std_logic_vector(3 downto 0);
+signal count_carry : std_logic_vector(2 downto 0);
+
+signal pointer_zero : std_logic;
+signal pointer_full : std_logic;
+signal decode_data_present : std_logic;
+signal data_present_int : std_logic;
+signal valid_write : std_logic;
+--
+--
+------------------------------------------------------------------------------------
+--
+-- Attributes to define LUT contents during implementation
+-- The information is repeated in the generic map for functional simulation--
+--
+------------------------------------------------------------------------------------
+--
+attribute INIT : string;
+attribute INIT of zero_lut : label is "0001";
+attribute INIT of full_lut : label is "8000";
+attribute INIT of dp_lut : label is "BFA0";
+attribute INIT of valid_lut : label is "C4";
+--
+------------------------------------------------------------------------------------
+--
+-- Start of BBFIFO_16x8 circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+
+ -- SRL16E data storage
+
+ data_width_loop: for i in 0 to 7 generate
+ --
+ attribute INIT : string;
+ attribute INIT of data_srl : label is "0000";
+ --
+ begin
+
+ data_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => data_in(i),
+ CE => valid_write,
+ CLK => clk,
+ A0 => pointer(0),
+ A1 => pointer(1),
+ A2 => pointer(2),
+ A3 => pointer(3),
+ Q => data_out(i) );
+
+ end generate data_width_loop;
+
+ -- 4-bit counter to act as data pointer
+ -- Counter is clock enabled by 'data_present'
+ -- Counter will be reset when 'reset' is active
+ -- Counter will increment when 'valid_write' is active
+
+ count_width_loop: for i in 0 to 3 generate
+ --
+ attribute INIT : string;
+ attribute INIT of count_lut : label is "6606";
+ --
+ begin
+
+ register_bit: FDRE
+ port map ( D => next_count(i),
+ Q => pointer(i),
+ CE => data_present_int,
+ R => reset,
+ C => clk);
+
+ count_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"6606")
+ --synthesis translate_on
+ port map( I0 => pointer(i),
+ I1 => read,
+ I2 => pointer_zero,
+ I3 => write,
+ O => half_count(i));
+
+ lsb_count: if i=0 generate
+ begin
+
+ count_muxcy: MUXCY
+ port map( DI => pointer(i),
+ CI => valid_write,
+ S => half_count(i),
+ O => count_carry(i));
+
+ count_xor: XORCY
+ port map( LI => half_count(i),
+ CI => valid_write,
+ O => next_count(i));
+
+ end generate lsb_count;
+
+ mid_count: if i>0 and i<3 generate
+ begin
+
+ count_muxcy: MUXCY
+ port map( DI => pointer(i),
+ CI => count_carry(i-1),
+ S => half_count(i),
+ O => count_carry(i));
+
+ count_xor: XORCY
+ port map( LI => half_count(i),
+ CI => count_carry(i-1),
+ O => next_count(i));
+
+ end generate mid_count;
+
+ upper_count: if i=3 generate
+ begin
+
+ count_xor: XORCY
+ port map( LI => half_count(i),
+ CI => count_carry(i-1),
+ O => next_count(i));
+
+ end generate upper_count;
+
+ end generate count_width_loop;
+
+
+ -- Detect when pointer is zero and maximum
+
+ zero_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0001")
+ --synthesis translate_on
+ port map( I0 => pointer(0),
+ I1 => pointer(1),
+ I2 => pointer(2),
+ I3 => pointer(3),
+ O => pointer_zero );
+
+
+ full_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"8000")
+ --synthesis translate_on
+ port map( I0 => pointer(0),
+ I1 => pointer(1),
+ I2 => pointer(2),
+ I3 => pointer(3),
+ O => pointer_full );
+
+
+ -- Data Present status
+
+ dp_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"BFA0")
+ --synthesis translate_on
+ port map( I0 => write,
+ I1 => read,
+ I2 => pointer_zero,
+ I3 => data_present_int,
+ O => decode_data_present );
+
+ dp_flop: FDR
+ port map ( D => decode_data_present,
+ Q => data_present_int,
+ R => reset,
+ C => clk);
+
+ -- Valid write signal
+
+ valid_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"C4")
+ --synthesis translate_on
+ port map( I0 => pointer_full,
+ I1 => write,
+ I2 => read,
+ O => valid_write );
+
+
+ -- assign internal signals to outputs
+
+ full <= pointer_full;
+ half_full <= pointer(3);
+ data_present <= data_present_int;
+
+end low_level_definition;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE BBFIFO_16x8.VHD
+--
+------------------------------------------------------------------------------------
+
+
diff --git a/clk_40mhz.v b/clk_40mhz.v
new file mode 100755
index 0000000..a38a628
--- /dev/null
+++ b/clk_40mhz.v
@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 09:14:13 05/06/2011
+// Design Name:
+// Module Name: clk_40mhz
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+module clk_40mhz(clk_50mhz,clk_40mhz);
+
+//Entradas
+input wire clk_50mhz;
+
+//Salidas
+output reg clk_40mhz;
+
+//Variables Internas
+wire clk_200mhz;
+reg [7:0] contador;
+
+//Inicio
+initial
+begin
+ clk_40mhz=0;
+ contador = 8'b00000000;
+end
+
+//instanciacion del DCM
+dcm_200mhz i_dcm_200mhz (.CLKIN_IN(clk_50mhz),.RST_IN(1'b0),.CLKFX_OUT(clk_200mhz),.CLKIN_IBUFG_OUT(),.CLK0_OUT(),.CLK2X_OUT(),.LOCKED_OUT());
+
+always @(posedge clk_200mhz)
+begin
+ contador = contador + 1;
+ if(contador == 5)
+ contador = 0;
+ //if(contador >= 3)
+ //begin
+ // contador = 0;
+ // clk_40mhz = ~clk_40mhz;
+ //end
+end
+
+always @(posedge clk_200mhz)
+begin
+ case(contador)
+ 8'b00000001: clk_40mhz=1; //1
+ 8'b00000010: clk_40mhz=1; //2
+ 8'b00000011: clk_40mhz=1; //3
+ 8'b00000100: clk_40mhz=0; //4
+ 8'b00000101: clk_40mhz=0; //5
+ default: clk_40mhz = 0;
+ endcase
+end
+endmodule
diff --git a/clock_divider.v b/clock_divider.v
new file mode 100755
index 0000000..77ae403
--- /dev/null
+++ b/clock_divider.v
@@ -0,0 +1,64 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Laboratorio de Particulas - Centro Atomico Bariloche
+// Engineer: Miguel Sofo Haro
+//
+// Create Date: 14:13:56 10/29/2010
+// Design Name:
+// Module Name: clock_divider
+// Project Name:
+// Target Devices:
+// Tool versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+// A partir del clock global de la FPGA, el proposito del modulo es generar
+// una señal de clock de frecuencia inferior (< frecuencia del clock global)
+//
+//////////////////////////////////////////////////////////////////////////////////
+module clock_divider
+(
+ input wire global_clock,
+ output reg clock
+);
+
+//Parameters,
+parameter o_freq_MHz = 10; //Output clock frecuency in MHz
+parameter gc_freq_MHz = 50; //Global clock frecuency in MHz
+
+//Local Paramters
+localparam first_trigger = ((gc_freq_MHz/o_freq_MHz)+1)/2;
+localparam second_trigger = (gc_freq_MHz/o_freq_MHz)+1;
+
+//Internal Variables
+reg [31:0] counter;
+
+//Initial Variables Values
+initial
+begin
+ counter = 0;
+ clock = 0;
+end
+//Circuit
+always @(posedge global_clock)
+begin
+ counter = counter + 1;
+ if(counter == first_trigger)
+ begin
+ clock = ~clock;
+ end
+ else
+ begin
+ if(counter == second_trigger)
+ begin
+ counter = 0;
+ clock = ~clock;
+ end
+ end
+end
+endmodule
diff --git a/dcm_200mhz.v b/dcm_200mhz.v
new file mode 100755
index 0000000..7b82f17
--- /dev/null
+++ b/dcm_200mhz.v
@@ -0,0 +1,92 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version : 10.1.03
+// \ \ Application : xaw2verilog
+// / / Filename : dcm_200mhz.v
+// /___/ /\ Timestamp : 05/05/2011 18:51:54
+// \ \ / \
+// \___\/\___\
+//
+//Command: xaw2verilog -st C:\Xilinx\10.1\ISE\dcm_200mhz.xaw C:\Xilinx\10.1\ISE\dcm_200mhz
+//Design Name: dcm_200mhz
+//Device: xc3s500e-fg320-4
+//
+// Module dcm_200mhz
+// Generated by Xilinx Architecture Wizard
+// Written for synthesis tool: XST
+// Period Jitter (unit interval) for block DCM_SP_INST = 0.14 UI
+// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 0.70 ns
+`timescale 1ns / 1ps
+
+module dcm_200mhz(CLKIN_IN,
+ RST_IN,
+ CLKFX_OUT,
+ CLKIN_IBUFG_OUT,
+ CLK0_OUT,
+ CLK2X_OUT,
+ LOCKED_OUT);
+
+ input CLKIN_IN;
+ input RST_IN;
+ output CLKFX_OUT;
+ output CLKIN_IBUFG_OUT;
+ output CLK0_OUT;
+ output CLK2X_OUT;
+ output LOCKED_OUT;
+
+ wire CLKFB_IN;
+ wire CLKFX_BUF;
+ wire CLKIN_IBUFG;
+ wire CLK0_BUF;
+ wire CLK2X_BUF;
+ wire GND_BIT;
+
+ assign GND_BIT = 0;
+ assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
+ assign CLK2X_OUT = CLKFB_IN;
+ BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
+ .O(CLKFX_OUT));
+ assign CLKIN_IBUFG = CLKIN_IN;
+ //IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),.O(CLKIN_IBUFG));
+ BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
+ .O(CLK0_OUT));
+ BUFG CLK2X_BUFG_INST (.I(CLK2X_BUF),
+ .O(CLKFB_IN));
+ DCM_SP DCM_SP_INST (.CLKFB(CLKFB_IN),
+ .CLKIN(CLKIN_IBUFG),
+ .DSSEN(GND_BIT),
+ .PSCLK(GND_BIT),
+ .PSEN(GND_BIT),
+ .PSINCDEC(GND_BIT),
+ .RST(RST_IN),
+ .CLKDV(),
+ .CLKFX(CLKFX_BUF),
+ .CLKFX180(),
+ .CLK0(CLK0_BUF),
+ .CLK2X(CLK2X_BUF),
+ .CLK2X180(),
+ .CLK90(),
+ .CLK180(),
+ .CLK270(),
+ .LOCKED(LOCKED_OUT),
+ .PSDONE(),
+ .STATUS());
+ defparam DCM_SP_INST.CLK_FEEDBACK = "2X";
+ defparam DCM_SP_INST.CLKDV_DIVIDE = 2.0;
+ defparam DCM_SP_INST.CLKFX_DIVIDE = 1;
+ defparam DCM_SP_INST.CLKFX_MULTIPLY = 4;
+ defparam DCM_SP_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+ defparam DCM_SP_INST.CLKIN_PERIOD = 20.000;
+ defparam DCM_SP_INST.CLKOUT_PHASE_SHIFT = "NONE";
+ defparam DCM_SP_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+ defparam DCM_SP_INST.DFS_FREQUENCY_MODE = "LOW";
+ defparam DCM_SP_INST.DLL_FREQUENCY_MODE = "LOW";
+ defparam DCM_SP_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+ defparam DCM_SP_INST.FACTORY_JF = 16'hC080;
+ defparam DCM_SP_INST.PHASE_SHIFT = 0;
+ defparam DCM_SP_INST.STARTUP_WAIT = "FALSE";
+endmodule
diff --git a/interfaz_spi.prj b/interfaz_spi.prj
new file mode 100644
index 0000000..f8c7001
--- /dev/null
+++ b/interfaz_spi.prj
@@ -0,0 +1 @@
+vhdl work "interfaz_spi.vhd"
diff --git a/interfaz_spi.vhd b/interfaz_spi.vhd
new file mode 100644
index 0000000..04a8162
--- /dev/null
+++ b/interfaz_spi.vhd
@@ -0,0 +1,214 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity interfaz_spi is
+ generic(
+ iCLK : boolean := false;
+ iCNV : boolean := false;
+ iDIN : boolean := false;
+ iDOU : boolean := false;
+ NB : positive := 16; -- number of bits of DAC
+ NDIV : positive := 10 -- divide the clock to get the spi clock
+ );
+ port (
+ --Entradas
+ clk : in std_logic; -- global clock input. 40 MHz en este caso, para estar en orden con baseline_ctrl
+ reset : in std_logic;
+ ptick_2ms : in std_logic; -- Con esta señal se sincroniza todo cada 2ms
+ data_dac1 : in std_logic_vector(11 downto 0);
+ data_dac2 : in std_logic_vector(11 downto 0);
+ data_dac3 : in std_logic_vector(11 downto 0);
+ data_dac4 : in std_logic_vector(11 downto 0);
+ --Señales a la E2PROM
+ cs_e2prom : out std_logic;
+ --Señales al DAC MAX5501
+ spi_sdo : out std_logic;
+ spi_clk : out std_logic;
+ spi_csn : out std_logic
+ );
+end entity interfaz_spi;
+
+architecture rtl of interfaz_spi is
+
+ type state_type is (STATE_IDLE,
+ STATE_INIT_TX,
+ STATE_SPI_IDLE,
+ STATE_SPI_CLK0,
+ STATE_SPI_CLK1,
+ STATE_SPI_FINISH);
+ signal state_reg, state_next : state_type;
+
+ signal rdy : std_logic;
+ signal busy : std_logic;
+ signal load_reg, load_next : std_logic;
+ signal spi_conv : std_logic;
+ signal spi_clk_i : std_logic;
+ signal start_reg, start_next : std_logic;
+ signal shift_out : std_logic;
+
+ signal dac1_buff_reg, dac1_buff_next : unsigned(11 downto 0);
+ signal dac2_buff_reg, dac2_buff_next : unsigned(11 downto 0);
+ signal dac3_buff_reg, dac3_buff_next : unsigned(11 downto 0);
+ signal dac4_buff_reg, dac4_buff_next : unsigned(11 downto 0);
+
+ signal sel_reg, sel_next : std_logic_vector(1 downto 0);
+ signal mux_signal : std_logic_vector(NB-1 downto 0);
+ constant DAC1 : std_logic_vector(1 downto 0) := "00"; -- selector de DAC1
+ constant DAC2 : std_logic_vector(1 downto 0) := "01"; -- selector de DAC2
+ constant DAC3 : std_logic_vector(1 downto 0) := "10"; -- selector de DAC3
+ constant DAC4 : std_logic_vector(1 downto 0) := "11"; -- selector de DAC4
+
+ signal bits_reg, bits_next : integer range 0 to NB-1;
+ signal bcnt_reg, bcnt_next : integer range 0 to NDIV-1;
+ signal data_reg, data_next : std_logic_vector(NB-1 downto 0);
+ signal count_reg, count_next : unsigned(1 downto 0);
+
+begin
+
+ dac1_buff_next <= unsigned(data_dac1) when (ptick_2ms = '1') else dac1_buff_reg;
+ dac2_buff_next <= unsigned(data_dac2) when (ptick_2ms = '1') else dac2_buff_reg;
+ dac3_buff_next <= unsigned(data_dac3) when (ptick_2ms = '1') else dac3_buff_reg;
+ dac4_buff_next <= unsigned(data_dac4) when (ptick_2ms = '1') else dac4_buff_reg;
+
+ --regusters
+ process(clk, reset)
+ begin
+ if (reset ='1') then
+ state_reg <= STATE_IDLE;
+ data_reg <= (others => '0');
+ dac1_buff_reg <= (others => '0');
+ dac2_buff_reg <= (others => '0');
+ dac3_buff_reg <= (others => '0');
+ dac4_buff_reg <= (others => '0');
+ count_reg <= (others => '0');
+ sel_reg <= (others => '0');
+ start_reg <= '0';
+ load_reg <= '0';
+ bcnt_reg <= 0;
+ bits_reg <= 0;
+ elsif rising_edge(clk) then
+ state_reg <= state_next;
+ data_reg <= data_next;
+ dac1_buff_reg <= dac1_buff_next;
+ dac2_buff_reg <= dac2_buff_next;
+ dac3_buff_reg <= dac3_buff_next;
+ dac4_buff_reg <= dac4_buff_next;
+ count_reg <= count_next;
+ sel_reg <= sel_next;
+ start_reg <= start_next;
+ load_reg <= load_next;
+ bcnt_reg <= bcnt_next;
+ bits_reg <= bits_next;
+ end if;
+ end process;
+
+ --next state logic
+ --MUX
+ with sel_reg select
+ mux_signal <= "1011" & std_logic_vector(dac1_buff_reg) when DAC1,--"00", -- Canal C DAC. Baseline canal 3
+ "1111" & std_logic_vector(dac2_buff_reg) when DAC2,--"01", -- Canal D DAC. Baseline canal 2
+ "0111" & std_logic_vector(dac3_buff_reg) when DAC3,--"10", -- Canal B DAC. HV canal 1
+ "0011" & std_logic_vector(dac4_buff_reg) when others; -- Canal A DAC. Baseline canal 1
+
+ data_next <= mux_signal when (load_reg = '1') else
+ data_reg(data_reg'high-1 downto 0) & data_reg(data_reg'high) when (shift_out = '1') else
+ data_reg;
+
+ -- maquina de estados que maneja todo
+ process(state_reg, ptick_2ms)
+ begin
+ state_next <= state_reg;
+ start_next <= '0';
+ load_next <= '0';
+ sel_next <= sel_reg;
+ count_next <= count_reg;
+ shift_out <= '0';
+ spi_clk_i <= '0';
+ spi_conv <= '1';
+ rdy <= '0';
+ busy <= '0';
+ bcnt_next <= 0;
+ bits_next <= bits_reg;
+ case state_reg is
+
+ when STATE_IDLE =>
+ count_next <= (others => '0');
+ sel_next <= DAC1;
+ if (ptick_2ms = '1') then
+ state_next <= STATE_INIT_TX;
+ else
+ state_next <= STATE_IDLE;
+ end if;
+
+ when STATE_INIT_TX =>
+ if (busy = '0') then
+ count_next <= count_reg + 1;
+ start_next <= '1';
+ load_next <= '1';
+ state_next <= STATE_SPI_IDLE;
+ if ( count_reg = 0 ) then
+ sel_next <= DAC1;
+ elsif ( count_reg = 1 ) then
+ sel_next <= DAC2;
+ elsif ( count_reg = 2 ) then
+ sel_next <= DAC3;
+ else
+ sel_next <= DAC4;
+ end if;
+ else
+ state_next <= STATE_INIT_TX;
+ end if;
+
+ when STATE_SPI_IDLE =>
+ if (start_reg <= '1') then
+ shift_out <= '1';
+ state_next <= STATE_SPI_CLK0;
+ end if;
+
+ when STATE_SPI_CLK0 =>
+ busy <= '1';
+ bcnt_next <= bcnt_reg+1;
+ spi_conv <= '0';
+ if (bcnt_reg = NDIV/2) then
+ state_next <= STATE_SPI_CLK1;
+ end if;
+
+ when STATE_SPI_CLK1 =>
+ busy <= '1';
+ bcnt_next <= bcnt_reg+1;
+ spi_clk_i <= '1';
+ spi_conv <= '0';
+ if (bcnt_reg = NDIV-1) then
+ bits_next <= bits_reg+1;
+ if (bits_reg = NB-1) then
+ rdy <= '1';
+ state_next <= STATE_SPI_FINISH;
+ else
+ shift_out <= '1';
+ state_next <= STATE_SPI_CLK0;
+ end if;
+ end if;
+
+ when STATE_SPI_FINISH =>
+ busy <= '1';
+ bcnt_next <= bcnt_reg+1;
+ if (bcnt_reg = NDIV-1) then
+ if (count_reg = 4) then
+ state_next <= STATE_IDLE;
+ else
+ state_next <= STATE_INIT_TX;
+ end if;
+ end if;
+ end case;
+ end process;
+
+ --output
+ spi_sdo <= not data_reg(data_reg'high) when iDOU else data_reg(data_reg'high);
+
+ spi_clk <= not spi_clk_i when iCLK else spi_clk_i;
+ spi_csn <= not spi_conv when iCNV else spi_conv;
+
+ cs_e2prom <= '1';
+
+end architecture;
diff --git a/interfaz_spi.xst b/interfaz_spi.xst
new file mode 100644
index 0000000..211ff21
--- /dev/null
+++ b/interfaz_spi.xst
@@ -0,0 +1,5 @@
+set -tmpdir "/home/horacio/work/lago/lago-fpga-vhdl/xst/projnav.tmp"
+set -xsthdpdir "/home/horacio/work/lago/lago-fpga-vhdl/xst"
+elaborate
+-ifn interfaz_spi.prj
+-ifmt mixed
diff --git a/ipcore_dir/DCM_33.v b/ipcore_dir/DCM_33.v
new file mode 100755
index 0000000..8234878
--- /dev/null
+++ b/ipcore_dir/DCM_33.v
@@ -0,0 +1,77 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version : 12.2
+// \ \ Application : xaw2verilog
+// / / Filename : DCM_33.v
+// /___/ /\ Timestamp : 06/02/2011 10:09:32
+// \ \ / \
+// \___\/\___\
+//
+//Command: xaw2verilog -st /media/Linux/LAGO/pruebas_vhdl/lago02/ipcore_dir/./DCM_33.xaw /media/Linux/LAGO/pruebas_vhdl/lago02/ipcore_dir/./DCM_33
+//Design Name: DCM_33
+//Device: xc3s500e-4fg320
+//
+// Module DCM_33
+// Generated by Xilinx Architecture Wizard
+// Written for synthesis tool: XST
+`timescale 1ns / 1ps
+
+module DCM_33(CLKIN_IN,
+ RST_IN,
+ CLKDV_OUT,
+ CLKIN_IBUFG_OUT,
+ CLK0_OUT,
+ LOCKED_OUT);
+
+ input CLKIN_IN;
+ input RST_IN;
+ output CLKDV_OUT;
+ output CLKIN_IBUFG_OUT;
+ output CLK0_OUT;
+ output LOCKED_OUT;
+
+ wire CLKDV_BUF;
+ wire CLKFB_IN;
+ wire CLKIN_IBUFG;
+ wire CLK0_BUF;
+ wire GND_BIT;
+
+ assign GND_BIT = 0;
+ assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
+ assign CLK0_OUT = CLKFB_IN;
+ BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
+ .O(CLKDV_OUT));
+ IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
+ .O(CLKIN_IBUFG));
+ BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
+ .O(CLKFB_IN));
+ DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(1.5), .CLKFX_DIVIDE(1),
+ .CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
+ .CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
+ .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
+ .DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
+ .FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
+ DCM_SP_INST (.CLKFB(CLKFB_IN),
+ .CLKIN(CLKIN_IBUFG),
+ .DSSEN(GND_BIT),
+ .PSCLK(GND_BIT),
+ .PSEN(GND_BIT),
+ .PSINCDEC(GND_BIT),
+ .RST(RST_IN),
+ .CLKDV(CLKDV_BUF),
+ .CLKFX(),
+ .CLKFX180(),
+ .CLK0(CLK0_BUF),
+ .CLK2X(),
+ .CLK2X180(),
+ .CLK90(),
+ .CLK180(),
+ .CLK270(),
+ .LOCKED(LOCKED_OUT),
+ .PSDONE(),
+ .STATUS());
+endmodule
diff --git a/ipcore_dir/DCM_33.vhd b/ipcore_dir/DCM_33.vhd
new file mode 100755
index 0000000..d9cd2fc
--- /dev/null
+++ b/ipcore_dir/DCM_33.vhd
@@ -0,0 +1,96 @@
+--------------------------------------------------------------------------------
+-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
+--------------------------------------------------------------------------------
+-- ____ ____
+-- / /\/ /
+-- /___/ \ / Vendor: Xilinx
+-- \ \ \/ Version : 12.2
+-- \ \ Application : xaw2vhdl
+-- / / Filename : DCM_33.vhd
+-- /___/ /\ Timestamp : 06/02/2011 10:11:46
+-- \ \ / \
+-- \___\/\___\
+--
+--Command: xaw2vhdl-st /media/Linux/LAGO/pruebas_vhdl/lago02/ipcore_dir/./DCM_33.xaw /media/Linux/LAGO/pruebas_vhdl/lago02/ipcore_dir/./DCM_33
+--Design Name: DCM_33
+--Device: xc3s500e-4fg320
+--
+-- Module DCM_33
+-- Generated by Xilinx Architecture Wizard
+-- Written for synthesis tool: XST
+
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+library UNISIM;
+use UNISIM.Vcomponents.ALL;
+
+entity DCM_33 is
+ port ( CLKIN_IN : in std_logic;
+ RST_IN : in std_logic;
+ CLKDV_OUT : out std_logic;
+ CLKIN_IBUFG_OUT : out std_logic;
+ CLK0_OUT : out std_logic;
+ LOCKED_OUT : out std_logic);
+end DCM_33;
+
+architecture BEHAVIORAL of DCM_33 is
+ signal CLKDV_BUF : std_logic;
+ signal CLKFB_IN : std_logic;
+ signal CLKIN_IBUFG : std_logic;
+ signal CLK0_BUF : std_logic;
+ signal GND_BIT : std_logic;
+begin
+ GND_BIT <= '0';
+ CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
+ CLK0_OUT <= CLKFB_IN;
+ CLKDV_BUFG_INST : BUFG
+ port map (I=>CLKDV_BUF,
+ O=>CLKDV_OUT);
+
+ CLKIN_IBUFG_INST : IBUFG
+ port map (I=>CLKIN_IN,
+ O=>CLKIN_IBUFG);
+
+ CLK0_BUFG_INST : BUFG
+ port map (I=>CLK0_BUF,
+ O=>CLKFB_IN);
+
+ DCM_SP_INST : DCM_SP
+ generic map( CLK_FEEDBACK => "1X",
+ CLKDV_DIVIDE => 1.5,
+ CLKFX_DIVIDE => 1,
+ CLKFX_MULTIPLY => 4,
+ CLKIN_DIVIDE_BY_2 => FALSE,
+ CLKIN_PERIOD => 20.000,
+ CLKOUT_PHASE_SHIFT => "NONE",
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
+ DFS_FREQUENCY_MODE => "LOW",
+ DLL_FREQUENCY_MODE => "LOW",
+ DUTY_CYCLE_CORRECTION => TRUE,
+ FACTORY_JF => x"C080",
+ PHASE_SHIFT => 0,
+ STARTUP_WAIT => FALSE)
+ port map (CLKFB=>CLKFB_IN,
+ CLKIN=>CLKIN_IBUFG,
+ DSSEN=>GND_BIT,
+ PSCLK=>GND_BIT,
+ PSEN=>GND_BIT,
+ PSINCDEC=>GND_BIT,
+ RST=>RST_IN,
+ CLKDV=>CLKDV_BUF,
+ CLKFX=>open,
+ CLKFX180=>open,
+ CLK0=>CLK0_BUF,
+ CLK2X=>open,
+ CLK2X180=>open,
+ CLK90=>open,
+ CLK180=>open,
+ CLK270=>open,
+ LOCKED=>LOCKED_OUT,
+ PSDONE=>open,
+ STATUS=>open);
+
+end BEHAVIORAL;
+
+
diff --git a/ipcore_dir/DCM_33.xaw b/ipcore_dir/DCM_33.xaw
new file mode 100755
index 0000000..fb08cee
--- /dev/null
+++ b/ipcore_dir/DCM_33.xaw
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
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diff --git a/ipcore_dir/DCM_33_arwz.ucf b/ipcore_dir/DCM_33_arwz.ucf
new file mode 100755
index 0000000..0676726
--- /dev/null
+++ b/ipcore_dir/DCM_33_arwz.ucf
@@ -0,0 +1,17 @@
+# Generated by Xilinx Architecture Wizard
+# --- UCF Template Only ---
+# Cut and paste these attributes into the project's UCF file, if desired
+INST DCM_SP_INST CLK_FEEDBACK = 1X;
+INST DCM_SP_INST CLKDV_DIVIDE = 1.5;
+INST DCM_SP_INST CLKFX_DIVIDE = 1;
+INST DCM_SP_INST CLKFX_MULTIPLY = 4;
+INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;
+INST DCM_SP_INST CLKIN_PERIOD = 20.000;
+INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;
+INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
+INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;
+INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;
+INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;
+INST DCM_SP_INST FACTORY_JF = C080;
+INST DCM_SP_INST PHASE_SHIFT = 0;
+INST DCM_SP_INST STARTUP_WAIT = FALSE;
diff --git a/ipcore_dir/DCM_33_flist.txt b/ipcore_dir/DCM_33_flist.txt
new file mode 100755
index 0000000..19d2f1e
--- /dev/null
+++ b/ipcore_dir/DCM_33_flist.txt
@@ -0,0 +1,4 @@
+# Output products list for <DCM_33>
+DCM_33_flist.txt
+DCM_33_readme.txt
+DCM_33_xmdf.tcl
diff --git a/ipcore_dir/DCM_33_readme.txt b/ipcore_dir/DCM_33_readme.txt
new file mode 100755
index 0000000..e8e3d1f
--- /dev/null
+++ b/ipcore_dir/DCM_33_readme.txt
@@ -0,0 +1,19 @@
+The following files were generated for 'DCM_33' in directory
+/media/Linux/LAGO/pruebas_vhdl/lago02/ipcore_dir/
+
+DCM_33_readme.txt:
+ Text file indicating the files generated and how they are used.
+
+DCM_33_xmdf.tcl:
+ ISE Project Navigator interface file. ISE uses this file to determine
+ how the files output by CORE Generator for the core can be integrated
+ into your ISE project.
+
+DCM_33_flist.txt:
+ Text file listing all of the output files produced when a customized
+ core was generated in the CORE Generator.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/ipcore_dir/DCM_33_xmdf.tcl b/ipcore_dir/DCM_33_xmdf.tcl
new file mode 100755
index 0000000..bfb22cb
--- /dev/null
+++ b/ipcore_dir/DCM_33_xmdf.tcl
@@ -0,0 +1,48 @@
+# The package naming convention is <core_name>_xmdf
+package provide DCM_33_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::DCM_33_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::DCM_33_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name DCM_33
+}
+# ::DCM_33_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::DCM_33_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path DCM_33_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module DCM_33
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/ipcore_dir/_xmsgs/cg.xmsgs b/ipcore_dir/_xmsgs/cg.xmsgs
new file mode 100644
index 0000000..a0540da
--- /dev/null
+++ b/ipcore_dir/_xmsgs/cg.xmsgs
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+
+<msg type="warning" file="sim" num="89" delta="new" >A core named <<arg fmt="%s" index="1">fifo</arg>> already exists in the output directory. Output products for this core may be overwritten.
+</msg>
+
+<msg type="info" file="sim" num="949" delta="new" >Finished generation of ASY schematic symbol.
+</msg>
+
+<msg type="info" file="sim" num="948" delta="new" >Finished FLIST file generation.
+</msg>
+
+</messages>
+
diff --git a/ipcore_dir/_xmsgs/pn_parser.xmsgs b/ipcore_dir/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..a60b11e
--- /dev/null
+++ b/ipcore_dir/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo.vhd" into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/ipcore_dir/coregen.cgc b/ipcore_dir/coregen.cgc
new file mode 100644
index 0000000..6322068
--- /dev/null
+++ b/ipcore_dir/coregen.cgc
@@ -0,0 +1,167 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>project</spirit:library>
+ <spirit:name>coregen</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>fifo</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="6.2" />
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">fifo</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DEPTH">32768</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_FULL_TYPE">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_RESET_VALUE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_FLAGS_RESET_VALUE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROGRAMMABLE_EMPTY_TYPE">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_DEPTH">8192</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_DBIT_ERROR">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT_WIDTH">13</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VALID_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_DATA_WIDTH">8</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_ASSERT_VALUE">4096</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT_WIDTH">13</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERFLOW_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_INT_CLK">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_TIMING_VIOLATIONS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PIN">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_IMPLEMENTATION">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_ASSERT_VALUE">2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_COUNT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INJECT_SBIT_ERROR">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EXTRA_LOGIC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_CLOCK_FREQUENCY">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FULL_THRESHOLD_NEGATE_VALUE">4095</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_EMPTY_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.UNDERFLOW_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">Asynchronous_Reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT_WIDTH">15</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DOUT_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_DATA_COUNT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DATA_COUNT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALMOST_FULL_FLAG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_ACKNOWLEDGE_SENSE">Active_High</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EMPTY_THRESHOLD_NEGATE_VALUE">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_EMBEDDED_REGISTERS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PERFORMANCE_OPTIONS">Standard_FIFO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RESET_SYNCHRONIZATION">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_ECC">false</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:instanceProperties>
+ <xilinx:projectOptions>
+ <xilinx:projectName>coregen</xilinx:projectName>
+ <xilinx:outputDirectory>./</xilinx:outputDirectory>
+ <xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
+ <xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
+ </xilinx:projectOptions>
+ <xilinx:part>
+ <xilinx:device>xc3s500e</xilinx:device>
+ <xilinx:deviceFamily>spartan3e</xilinx:deviceFamily>
+ <xilinx:package>fg320</xilinx:package>
+ <xilinx:speedGrade>-4</xilinx:speedGrade>
+ </xilinx:part>
+ <xilinx:flowOptions>
+ <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
+ <xilinx:designEntry>VHDL</xilinx:designEntry>
+ <xilinx:asySymbol>true</xilinx:asySymbol>
+ <xilinx:flowVendor>Foundation_ISE</xilinx:flowVendor>
+ <xilinx:addPads>false</xilinx:addPads>
+ <xilinx:removeRPMs>false</xilinx:removeRPMs>
+ <xilinx:createNDF>false</xilinx:createNDF>
+ <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
+ <xilinx:formalVerification>false</xilinx:formalVerification>
+ </xilinx:flowOptions>
+ <xilinx:simulationOptions>
+ <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
+ <xilinx:simulationLanguage>VHDL_and_Verilog</xilinx:simulationLanguage>
+ <xilinx:foundationSym>false</xilinx:foundationSym>
+ </xilinx:simulationOptions>
+ <xilinx:packageInfo>
+ <xilinx:sourceCoreCreationDate>2012-10-13+03:35</xilinx:sourceCoreCreationDate>
+ </xilinx:packageInfo>
+ </xilinx:instanceProperties>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ <spirit:componentInstance>
+ <spirit:instanceName>DCM_33</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="dcm_sp" spirit:version="13.1" />
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">DCM_33</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XAWFILENAME">/home/horacio/work/lago/lago_fpga_sync_one_fifo/ipcore_dir/DCM_33.xaw</spirit:configurableElementValue>
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+ <xilinx:package>fg320</xilinx:package>
+ <xilinx:speedGrade>-4</xilinx:speedGrade>
+ </xilinx:part>
+ <xilinx:flowOptions>
+ <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
+ <xilinx:designEntry>VHDL</xilinx:designEntry>
+ <xilinx:asySymbol>true</xilinx:asySymbol>
+ <xilinx:flowVendor>Foundation_ISE</xilinx:flowVendor>
+ <xilinx:addPads>false</xilinx:addPads>
+ <xilinx:removeRPMs>false</xilinx:removeRPMs>
+ <xilinx:createNDF>false</xilinx:createNDF>
+ <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
+ <xilinx:formalVerification>false</xilinx:formalVerification>
+ </xilinx:flowOptions>
+ <xilinx:simulationOptions>
+ <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
+ <xilinx:simulationLanguage>VHDL_and_Verilog</xilinx:simulationLanguage>
+ <xilinx:foundationSym>false</xilinx:foundationSym>
+ </xilinx:simulationOptions>
+ </xilinx:instanceProperties>
+ </spirit:vendorExtensions>
+</spirit:design>
+
diff --git a/ipcore_dir/coregen.cgp b/ipcore_dir/coregen.cgp
new file mode 100644
index 0000000..7f8f48f
--- /dev/null
+++ b/ipcore_dir/coregen.cgp
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = VHDL
+SET device = xc3s500e
+SET devicefamily = spartan3e
+SET flowvendor = Foundation_ISE
+SET package = fg320
+SET speedgrade = -4
+SET verilogsim = true
+SET vhdlsim = true
diff --git a/ipcore_dir/coregen.log b/ipcore_dir/coregen.log
new file mode 100644
index 0000000..12fe67a
--- /dev/null
+++ b/ipcore_dir/coregen.log
@@ -0,0 +1,63 @@
+INFO:sim:172 - Generating IP...
+Applying current project options...
+Finished applying current project options.
+Customizing IP...
+Release 14.3 - Xilinx CORE Generator IP GUI Launcher P.40xd (lin64)
+Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
+Finished Customizing.
+Generating IP...
+WARNING:sim:89 - A core named <fifo> already exists in the output directory.
+ Output products for this core may be overwritten.
+XST: HDL Compilation
+XST: Design Hierarchy Analysis
+XST: HDL Analysis
+XST: HDL Synthesis
+XST: Advanced HDL Synthesis
+XST: Low Level Synthesis
+XST: Partition Report
+XST: Final Report
+Generating Implementation files.
+Generating NGC file.
+Finished Generation.
+Generating IP instantiation template...
+Generating ASY schematic symbol...
+INFO:sim:949 - Finished generation of ASY schematic symbol.
+Generating SYM schematic symbol for 'fifo'...
+Generating metadata file...
+Generating ISE project...
+XCO file found: fifo.xco
+XMDF file found: fifo_xmdf.tcl
+Adding /home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo.asy
+-view all -origin_type imported
+Adding /home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo.ngc
+-view all -origin_type created
+Checking file
+"/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo.ngc" for
+project device match ...
+File "/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo.ngc"
+device information matches project device.
+Adding /home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo.sym
+-view all -origin_type imported
+Adding /home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo.vhd
+-view all -origin_type created
+INFO:HDLCompiler:1061 - Parsing VHDL file
+ "/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo.vhd"
+ into library work
+INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
+Adding /home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo.vho
+-view all -origin_type imported
+Adding
+/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo_generator_re
+adme.txt -view all -origin_type imported
+INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
+ Please set the new top explicitly by running the "project set top" command.
+ To re-calculate the new top automatically, set the "Auto Implementation Top"
+ property to true.
+Top level has been set to "/fifo"
+Generating README file...
+Generating FLIST file...
+INFO:sim:948 - Finished FLIST file generation.
+Launching README viewer...
+Moving files to output directory...
+Finished moving files to output directory
+Wrote CGP file for project 'fifo'.
diff --git a/ipcore_dir/coregen.rsp b/ipcore_dir/coregen.rsp
new file mode 100755
index 0000000..ee0058e
--- /dev/null
+++ b/ipcore_dir/coregen.rsp
@@ -0,0 +1,2 @@
+SETPROJECT "/home/horacio/work/lago/lago_fpga_sync_one_fifo/ipcore_dir/coregen.cgp"
+LAUNCHXCO "/home/horacio/work/lago/lago_fpga_sync_one_fifo/ipcore_dir/fifo.xco"
diff --git a/ipcore_dir/edit_fifo.tcl b/ipcore_dir/edit_fifo.tcl
new file mode 100644
index 0000000..a514e49
--- /dev/null
+++ b/ipcore_dir/edit_fifo.tcl
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+ set xilenv ""
+ if { [info exists ::env(XILINX) ] } {
+ if { [info exists ::env(MYXILINX)] } {
+ set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+ } else {
+ set xilenv $::env(XILINX)
+ }
+ }
+ foreach path [ split $xilenv $::xilinx::path_sep ] {
+ set fullPath [ file join $path $relativePath ]
+ if { [ file exists $fullPath ] } {
+ return $fullPath
+ }
+ }
+ return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "fifo" xc3s500e-4fg320 VHDL ]
+
+if { $result == 0 } {
+ puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+ puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+ # convert 'version check' result to real return range, bypassing any messages.
+ set result [ expr $result - 3 ]
+} else {
+ puts "Core Generator edit cancelled."
+}
+exit $result
diff --git a/ipcore_dir/fifo.asy b/ipcore_dir/fifo.asy
new file mode 100644
index 0000000..ee71229
--- /dev/null
+++ b/ipcore_dir/fifo.asy
@@ -0,0 +1,45 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 fifo
+RECTANGLE Normal 32 32 544 768
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName din[31:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Normal 144 800 144 768
+PIN 144 800 BOTTOM 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName dout[7:0]
+PINATTR Polarity OUT
+LINE Normal 576 208 544 208
+PIN 576 208 RIGHT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Normal 576 272 544 272
+PIN 576 272 RIGHT 36
+PINATTR PinName prog_full
+PINATTR Polarity OUT
+LINE Normal 576 432 544 432
+PIN 576 432 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+
diff --git a/ipcore_dir/fifo.gise b/ipcore_dir/fifo.gise
new file mode 100644
index 0000000..4fb80a9
--- /dev/null
+++ b/ipcore_dir/fifo.gise
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="fifo.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:fileType="FILE_ASY" xil_pn:name="fifo.asy" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="fifo.sym" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_VHO" xil_pn:name="fifo.vho" xil_pn:origination="imported"/>
+ <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
diff --git a/ipcore_dir/fifo.ncf b/ipcore_dir/fifo.ncf
new file mode 100644
index 0000000..e69de29
diff --git a/ipcore_dir/fifo.ngc b/ipcore_dir/fifo.ngc
new file mode 100644
index 0000000..fc7ab74
--- /dev/null
+++ b/ipcore_dir/fifo.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.6e
+$46e44<,[o}e~g`n;"2*73>(-;0<9>40123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?2:216>6?<2:M<??41292*5733881EC^ZT;CG@WD;980;2<h4128JJUSS2yxdkRhzlm]wlwct`5;96=0=6:30>LHW]]0{~biPftno[qnumzbTm~}jru>26?69:?1:?7GAPTV9twi`Wog`Rzgrdqk[kc`i}o7=?4?>0c856<H]]Z^X7jnt`]`kphs4881<3?k;019KPRW]]0|~Rjnt`]`kphs4881<3?;;069MKVR\3KOH_O31283:76<9<0BB][[:qplcZcjx}sTxe|jsi>20?69:>1:97GAPTV9twi`Wlg{xtQ{hsgplZgt{lx0<:50?04?43=AGZ^X7~}of]fiur~W}byi~fPndebp`:6<3:5=i5>5;MVPUSS2{nThlzn_bmvjq:6<3:5==5>:HLSQQ<CAH6;6=0>1:39KPRW]]0OCL2?:1<2?7753:81EC^ZT;fjj956294o7>}:01gec647%=;;794FNQWW>AOE4:0;2<?44;MVPUSS2MEI0>4?>59600663?80:4:468;50>>3:8;9754@UURVP?bh}}6<6=0;;9C;<4=><23;<4<49768=30>02KOH_O30?;8EABUI5;;245NDEPB847912KOH_O313<a?DBCZH6:?7>19:CG@WG;9:437LJKR@>2:==FLMXJ0?07;@FGVD:4611JHI\N<5<;?DBCZH6>255NDEPB838?3HNO^L28>99B@ATF41437LJKR@>::==FLMXI0=06;@FGVG:687h0MIJ]B=32>58>3HNO^O2>1?:8EABUJ5;546OKDS@?6;><IMNYN1=18:CG@WD;<720MIJ]B=7=<>GCL[H7:364AEFQF91902KOH_L38?:8EABUJ535?6OCL89BW\HDW[OL=6L<;CW1<>DR[VCEJB?4C39@A44<KAOHGRBFCDLPAZR^XL80OD:4CMIB0>EKCK90OA\6;BMNILRSMM;?7NA]E^EFJ@TF\@EESD@IO69@V@GSMM;0H?5KI99GMD:7294=7IGN<1<5?AOE494=7IGM<0<5?AOE4;437IGM<283:3=CAK68255KO@>3>5813MEJ0=09;EMA85813MEI0<09;EMA878?3MEI0>4?>79GKG:46;1N8>5JN@18AKD53O>97K6=;GF0?CBD<2LOOH=4FEG0?CBW<2LO\H?4G29DJA4<A980E<<4I308M6?<AGC__YO[E69JJLRX89=0ECG[_134?LHN\V:9;6GAIU]372=NF@^T<994IOKW[5303@DBXR>97:KMMQY7?>1BBDZP0958MKOSW93<7D@FT^2B3>OIA]U;N:5FNHV\4F1<AGC_S=J8;HLJPZ6B?2CEEYQ?F69JJLRX99=0ECG[_034?LHN\V;9;6GAIU]272=NF@^T=994IOKW[4303@DBXR?97:KMMQY6?>1BBDZP1958MKOSW83<7D@FT^3B3>OIA]U:N:5FNHV\5F1<AGC_S<J8;HLJPZ7B?2CEEYQ>F69JJLRX:9=0ECG[_334?LHN\V89;6GAIU]172=NF@^T>994IOKW[7303@DBXR<97:KMMQY5?>1BBDZP2958MKOSW;3<7D@FT^0B3>OIA]U9N:5FNHV\6F1<AGC_S?J8;HLJPZ4B?2CEEYQ=F69JJLRX;9=0ECG[_234?LHN\V99;6GAIU]072=NF@^T?994IOKW[6303@DBXR=97:KMMQY4?>1BBDZP3958MKOSW:3<7D@FT^1B3>OIA]U8N:5FNHV\7F1<AGC_S>J8;HLJPZ5B?2CEEYQ<F79JJLRXI?1BBDZPB39OM7=KG?1GCLJJD69OKBODIE>0@XZ>4:NVP70<D\^9SI84LTV1[I2<D\^8:6BZT2]O0>JR\=<0@XZ;_E78IVAHF<1FYUMVc:ObnjtQm{ybccm4MhllvScu{`ee>6@>3:L251=I98;87C?=3:L271=I9:8?7C?<359M56233G;8995A1247?K74?=1E=>6;;O30=6=I9=>0B<:?4:L2015<F8?87C?93:L236=I91>0B<663:L2=6=I:990B??<;O017>H5;:1E>9=4N370?K41;2D9;>5A2918J7?53G987C=?3:L056=I;;90B>=<;O177>H4=:1E?;=4N250?K5?;2D85>5A4118J1743G>9?6@;329M014<F<80B:<4N8d8JGYE]ZZBBR^]OQQ4?KCS_FX@=6A=;NI2?U2<XHX_m6^FN^@VWLB_j2ZBBRLZSOCNA6=WZL;0]n5]AL@22ZU6WZ>j7_KND^DJVVR63Z;87^GB_BMOHLUNGGUHDHMD6:QLQWEB?2YYZLBPA69PVSGKWK>0_^\N4:QPVG2<\PZN??5Z0.eqb+ta'nis"nbdx.O{kwYulVzexQhc^zlv5678VXnxb{1208Q5)`zo$yj"ilx/aoo})JpfxT~iQnup\cfYg{:;<<Q]erwop4553\:$kh!rg-dg}(ddbr$Aua}_sf\tkruWniTtb|?010\V`urd};8>6[?/fpe*w`(ojr%oaew/LzlvZtcWyd~Ril_ymq4564W[oxyaz>339V4*aun'xm#jmw.bnh|*Kg{UyhR~ats]dgZ~hz9:;8R\jstnw564<]9%l~k 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1262o:0q~:77;296~X3>>16894;669'017=n81v8:k:181[33l27?87;;d:&704<a:2wx9>:50;0xZ05334>?68=;;%675?`43ty?n54?:3y]0d`<5=>18lh4$562>f?<uz>i:7>52z\7e`=:<=0?mh5+4539gd=z{=h>6=4={_6b`>;3<3>jh6*;408`f>{t<k>1<7<t^5c`?8232=kh7):;1;a`?xu3j:0;6?uQ4``8912=<hh0(9:>:bf8yv2e:3:1>vP;a`9>01<3ih1/89?5cd9~w1d62909wS:n9:?70?2f12.?8<4lf:p0g6=838pR9o7;<67>1g?3->?=7j?;|q7g5<72;qU8n>4=5690f6<,=>:6i<4}r6ae?6=:rT?nl524587fd=#<=;1h>5rs5d4>5<5sW>m;63;4;6e3>"3<80o46srnd:0>5<5sA>?>6sae9694?4|@=>97p`j8483>7}O<=80qck76;296~N3<;1vbh68:181M23:2wei5650;0xL1253tdn444?:3yK014<ugo3m7>52zJ707=zfl2i6=4={I676>{im1i1<7<tH561?xhb0m0;6?uG4508ykc?m3:1>vF;439~j`>a2909wE:;2:ma<6=838pD9:=;|lf=4<72;qC89<4}og:6?6=:rB?8?5rnd;0>5<5sA>?>6sae8694?4|@=>97p`j9483>7}O<=80qck66;296~N3<;1vbh78:181M23:2wei4650;0xL1253tdn544?:3yK014<ugo2m7>52zJ707=zfl3i6=4={I676>{im0i1<7<tH561?xhb1m0;6?uG4508ykc>m3:1>vF;439~j`?a2909wE:;2:mad6=838pD9:=;|lfe4<72;qC89<4}ogb6?6=:rB?8?5rndc0>5<5sA>?>6sae`694?4|@=>97p`ja483>7}O<=80qckn6;296~N3<;1vbho8:181M23:2weil650;0xL1253tdnm44?:3yK014<ugojm7>52zJ707=zflki6=4={I676>{imhi1<7<tH561?xhbim0;6?uG4508ykcfm3:1>vF;439~j`ga2909wE:;2:mag6=838pD9:=;|lff4<72;qC89<4}oga6?6=:rB?8?5rnb:5>5<6sA>?>6sacc494?7|@=>97p`lb683>4}O<=80qcmm8;295~N3<;1vbnl6:182M23:2weooo50;3xL1253tdhno4?:0yK014<ugiio7>51zJ707=zfjho6=4>{I676>{ikko1<7?tH561?xhdjo0;6<uG4508yked83:1=vF;439~jfe6290:wE:;2:mgf4=83;pD9:=;|l`g6<728qC89<4}oa`0?6=9rB?8?5rnba6>5<6sA>?>6sacb494?7|@=>97p`lc683>4}O<=80qcml8;295~N3<;1vbnm6:182M23:2weono50;3xL1253tdhoo4?:0yK014<ugiho7>51zJ707=zfjio6=4>{I676>{ikjo1<7?tH561?xhdko0;6<uG4508ykec83:1=vF;439~jfb6290:wE:;2:mga4=83;pD9:=;|l``6<728qC89<4}oag0?6=9rB?8?5rnbf6>5<6sA>?>6sace494?7|@=>97p`ld683>4}O<=80qcmk8;295~N3<;1vbnj6:182M23:2weoio50;3xL1253tdhho4?:0yK014<ugioo7>51zJ707=zfjno6=4>{I676>{ikmo1<7?tH561?xhdlo0;6<uG4508ykeb83:1=vF;439~jfc6290:wE:;2:mg`4=83;pD9:=;|l`a6<728qC89<4}oaf0?6=9rB?8?5rnbg6>5<6sA>?>6sacd494?7|@=>97p`le683>4}O<=80qcmj8;295~N3<;1vbnk6:182M23:2weoho50;3xL1253tdhio4?:0yK014<ugino7>51zJ707=zfjoo6=4>{I676>{iklo1<7?tH561?xhdmo0;6<uG4508ykea83:1=vF;439~jf`6290:wE:;2:mgc4=83;pD9:=;|l`b6<728qC89<4}oae0?6=9rB?8?5rnbd6>5<6sA>?>6sacg494?7|@=>97p`lf683>4}O<=80qcmi8;295~N3<;1vbnh6:182M23:2weoko50;3xL1253tdhjo4?:0yK014<ugimo7>51zJ707=zfjlo6=4>{I676>{ikoo1<7?tH561?xhdno0;6<uG4508ykb783:1=vF;439~ja66290:wE:;2:m`54=83;pD9:=;|lg46<728qC89<4}of30?6=9rB?8?5rne26>5<6sA>?>6sad1494?7|@=>97p`k0683>4}O<=80qcj?8;295~N3<;1vbi>6:182M23:2weh=o50;3xL1253tdo<o4?:0yK014<ugn;o7>51zJ707=zfm:o6=4>{I676>{il9o1<7?tH561?xhc8o0;6<uG4508ykb683:1=vF;439~ja76290:wE:;2:m`44=83;pD9:=;|lg56<728qC89<4}of20?6=9rB?8?5rne36>5<6sA>?>6sad0494?7|@=>97p`k1683>4}O<=80qcj>8;295~N3<;1vbi?6:182M23:2weh<o50;3xL1253tdo=o4?:0yK014<ugn:o7>51zJ707=zfm;o6=4>{I676>{il8o1<7?tH561?xhc9o0;6<uG4508ykb583:1=vF;439~ja46290:wE:;2:m`74=83;pD9:=;|lg66<728qC89<4}of10?6=9rB?8?5rne06>5<6sA>?>6sad3494?7|@=>97p`k2683>4}O<=80qcj=8;295~N3<;1vbi<6:182M23:2weh?o50;3xL1253tdo>o4?:0yK014<ugn9o7>51zJ707=zfm8o6=4>{I676>{il;o1<7?tH561?xhc:o0;6<uG4508ykb483:1=vF;439~ja56290:wE:;2:m`64=83;pD9:=;|lg76<728qC89<4}of00?6=9rB?8?5rne16>5<6sA>?>6sad2494?7|@=>97p`k3683>4}O<=80qcj<8;295~N3<;1vbi=6:182M23:2weh>o50;3xL1253tdo?o4?:0yK014<ugn8o7>51zJ707=zfm9o6=4>{I676>{il:o1<7?tH561?xhc;o0;6<uG4508ykb383:1=vF;439~ja26290:wE:;2:m`14=83;pD9:=;|lg06<728qC89<4}of70?6=9rB?8?5rne66>5<6sA>?>6sad5494?7|@=>97p`k4683>4}O<=80qcj;8;295~N3<;1vbi:6:182M23:2weh9o50;3xL1253tdo8o4?:0yK014<ugn?o7>51zJ707=zfm>o6=4>{I676>{il=o1<7?tH561?xhc<o0;6<uG4508ykb283:1=vF;439~ja36290:wE:;2:m`04=83;pD9:=;|lg16<728qC89<4}of60?6=9rB?8?5rne76>5<6sA>?>6sad4494?7|@=>97p`k5683>4}O<=80qcj:8;295~N3<;1vbi;6:182M23:2weh8o50;3xL1253tdo9o4?:0yK014<ugn>o7>51zJ707=zfm?o6=4>{I676>{il<o1<7?tH561?xhc=o0;6<uG4508ykb183:1=vF;439~ja06290:wE:;2:m`34=83;pD9:=;|lg26<728qC89<4}of50?6=9rB?8?5rne46>5<6sA>?>6sad7494?7|@=>97p`k6683>4}O<=80qcj98;295~N3<;1vbi86:182M23:2weh;o50;3xL1253tdo:o4?:0yK014<ugn=o7>51zJ707=zfm<o6=4>{I676>{il?o1<7?tH561?xhc>o0;6<uG4508ykb083:1=vF;439~ja16290:wE:;2:m`24=83;pD9:=;|lg36<728qC89<4}of40?6=9rB?8?5rne56>5<6sA>?>6sad6494?7|@=>97p`k7683>4}O<=80qcj88;295~N3<;1vbi96:182M23:2weh:o50;3xL1253tdo;o4?:0yK014<ugn<o7>51zJ707=zfm=o6=4>{I676>{il>o1<7?tH561?xhc?o0;6<uG4508ykb?83:1=vF;439~ja>6290:wE:;2:m`=4=83;pD9:=;|lg<6<728qC89<4}of;0?6=9rB?8?5rne:6>5<6sA>?>6sad9494?7|@=>97p`k8683>4}O<=80qcj78;295~N3<;1vbi66:182M23:2weh5o50;3xL1253tdo4o4?:0yK014<ugn3o7>51zJ707=zfm2o6=4>{I676>{il1o1<7?tH561?xhc0o0;6<uG4508ykb>83:1=vF;439~ja?6290:wE:;2:m`<4=83;pD9:=;|lg=6<728qC89<4}of:0?6=9rB?8?5rne;6>5<6sA>?>6sad8494?7|@=>97p`k9683>4}O<=80qcj68;295~N3<;1vbi76:182M23:2weh4o50;3xL1253tdo5o4?:0yK014<ugn2o7>51zJ707=zfm3o6=4>{I676>{il0o1<7?tH561?xhc1o0;6<uG4508ykbf83:1=vF;439~jag6290:wE:;2:m`d4=83;pD9:=;|lge6<728qC89<4}ofb0?6=9rB?8?5rnec6>5<6sA>?>6sad`494?7|@=>97p`ka683>4}O<=80qcjn8;295~N3<;1vbio6:182M23:2wehlo50;3xL1253tdomo4?:0yK014<ugnjo7>51zJ707=zfmko6=4>{I676>{ilho1<7?tH561?xhcio0;6<uG4508ykbe83:1=vF;439~jad6290:wE:;2:m`g4=83;pD9:=;|lgf6<728qC89<4}ofa0?6=9rB?8?5rne`6>5<6sA>?>6sadc494?7|@=>97p`kb683>4}O<=80qcjm8;295~N3<;1vbil6:182M23:2wehoo50;3xL1253tdono4?:0yK014<ugnio7>51zJ707=zfmho6=4>{I676>{ilko1<7?tH561?xhcjo0;6<uG4508ykbd83:1=vF;439~jae6290:wE:;2:m`f4=83;pD9:=;|lgg6<728qC89<4}of`0?6=9rB?8?5rnea6>5<6sA>?>6sadb494?7|@=>97p`kc683>4}O<=80qcjl8;295~N3<;1vbim6:182M23:2wehno50;3xL1253tdooo4?:0yK014<ugnho7>51zJ707=zfmio6=4>{I676>{iljo1<7?tH561?xhcko0;6<uG4508ykbc83:1=vF;439~jab6290:wE:;2:m`a4=83;pD9:=;|lg`6<728qC89<4}ofg0?6=9rB?8?5rnef6>5<6sA>?>6sade494?7|@=>97p`kd683>4}O<=80qcjk8;295~N3<;1vbij6:182M23:2wehio50;3xL1253tdoho4?:0yK014<ugnoo7>51zJ707=zfmno6=4>{I676>{ilmo1<7?tH561?xhclo0;6<uG4508ykbb83:1=vF;439~jac6290:wE:;2:m``4=83;pD9:=;|lga6<728qC89<4}off0?6=9rB?8?5rneg6>5<6sA>?>6sadd494?7|@=>97p`ke683>4}O<=80qcjj8;295~N3<;1vbik6:182M23:2wehho50;3xL1253tdoio4?:0yK014<ugnno7>51zJ707=zfmoo6=4>{I676>{illo1<7?tH561?xhcmo0;6<uG4508ykba83:1=vF;439~ja`6290:wE:;2:m`c4=83;pD9:=;|lgb6<728qC89<4}ofe0?6=9rB?8?5rned6>5<6sA>?>6sadg494?7|@=>97p`kf683>4}O<=80qcji8;295~N3<;1vbih6:182M23:2wehko50;3xL1253tdojo4?:0yK014<ugnmo7>51zJ707=zfmlo6=4>{I676>{iloo1<7?tH561?xhcno0;6<uG4508ykc783:1=vF;439~j`66290:wE:;2:ma54=83;pD9:=;|lf46<728qC89<4}og30?6=9rB?8?5rnd26>5<6sA>?>6sae1494?7|@=>97p`j0683>4}O<=80qck?8;295~N3<;1vbh>6:182M23:2wei=o50;3xL1253tdn<o4?:0yK014<ugo;o7>51zJ707=zfl:o6=4>{I676>{im9o1<7?tH561?xhb8o0;6<uG4508ykc683:1=vF;439~j`76290:wE:;2:ma44=83;pD9:=;|lf56<728qC89<4}og20?6=9rB?8?5rnd36>5<6sA>?>6sae0494?7|@=>97p`j1683>4}O<=80qck>8;295~N3<;1vbh?6:182M23:2wei<o50;3xL1253tdn=o4?:0yK014<ugo:o7>51zJ707=zfl;o6=4>{I676>{im8o1<7?tH561?xhb9o0;6<uG4508ykc583:1=vF;439~j`46290:wE:;2:ma74=83;pD9:=;|lf66<728qC89<4}og10?6=9rB?8?5rnd06>5<6sA>?>6sae3494?7|@=>97p`j2683>4}O<=80qck=8;295~N3<;1vbh<6:182M23:2wei?o50;3xL1253tdn>o4?:0yK014<ugo9o7>51zJ707=zfl8o6=4>{I676>{im;o1<7?tH561?xhb:o0;6<uG4508ykc483:1=vF;439~j`56290:wE:;2:ma64=83;pD9:=;|lf76<728qC89<4}og00?6=9rB?8?5rnd16>5<6sA>?>6sae2494?7|@=>97p`j3683>4}O<=80qck<8;295~N3<;1vbh=6:182M23:2wei>o50;3xL1253tdn?o4?:0yK014<ugo8o7>51zJ707=zfl9o6=4>{I676>{im:o1<7?tH561?xhb;o0;6<uG4508ykc383:1=vF;439~j`26290:wE:;2:ma14=83;pD9:=;|lf06<728qC89<4}og70?6=9rB?8?5rnd66>5<6sA>?>6sae5494?7|@=>97p`j4683>4}O<=80qck;8;295~N3<;1vbh:6:182M23:2wei9o50;3xL1253tdn8o4?:0yK014<ugo?o7>51zJ707=zfl>o6=4>{I676>{im=o1<7?tH561?xhb<o0;6<uG4508ykc283:1=vF;439~j`36290:wE:;2:ma04=83;pD9:=;|lf16<728qC89<4}og60?6=9rB?8?5rnd76>5<6sA>?>6sae4494?7|@=>97p`j5683>4}O<=80qck:8;295~N3<;1vbh;6:182M23:2wei8o50;3xL1253tdn9o4?:0yK014<ugo>o7>51zJ707=zfl?o6=4>{I676>{im<o1<7?tH561?xhb=o0;6<uG4508ykc183:1=vF;439~j`06290:wE:;2:ma34=83;pD9:=;|lf26<728qC89<4}og50?6=9rB?8?5rnd46>5<6sA>?>6sae7494?7|@=>97p`j6683>4}O<=80qck98;295~N3<;1vbh86:182M23:2wei;o50;3xL1253tdn:o4?:0yK014<ugo=o7>51zJ707=zfl<o6=4>{I676>{im?o1<7?tH561?xhb>o0;6<uG4508ykc083:1=vF;439~j`16290:wE:;2:ma24=83;pD9:=;|lf36<728qC89<4}og40?6=9rB?8?5rnd56>5<6sA>?>6sae6494?7|@=>97p`j7683>4}O<=80qck88;295~N3<;1vbh96:182M23:2wei:o50;3xL1253tdn;o4?:0yK014<ugo<o7>51zJ707=zfl=o6=4>{I676>{im>o1<7?tH561?xhb?o0;6<uG4508ykc?83:1=vF;439~j`>6290:wE:;2:ma=4=83;pD9:=;|~yEFDs8:i=7k<10;e7g{GHKq;qMN_{|BC
\ No newline at end of file
diff --git a/ipcore_dir/fifo.sym b/ipcore_dir/fifo.sym
new file mode 100644
index 0000000..410396c
--- /dev/null
+++ b/ipcore_dir/fifo.sym
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="fifo">
+ <symboltype>BLOCK</symboltype>
+ <timestamp>2013-11-14T16:1:28</timestamp>
+ <pin polarity="Input" x="0" y="80" name="din[31:0]" />
+ <pin polarity="Input" x="0" y="144" name="wr_en" />
+ <pin polarity="Input" x="0" y="176" name="wr_clk" />
+ <pin polarity="Input" x="0" y="240" name="rd_en" />
+ <pin polarity="Input" x="0" y="272" name="rd_clk" />
+ <pin polarity="Input" x="144" y="800" name="rst" />
+ <pin polarity="Output" x="576" y="80" name="dout[7:0]" />
+ <pin polarity="Output" x="576" y="208" name="full" />
+ <pin polarity="Output" x="576" y="272" name="prog_full" />
+ <pin polarity="Output" x="576" y="432" name="empty" />
+ <graph>
+ <text style="fontsize:40;fontname:Arial" x="32" y="32">fifo</text>
+ <rect width="512" x="32" y="32" height="736" />
+ <line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin din[31:0]" />
+ <line x2="32" y1="144" y2="144" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin wr_en" />
+ <line x2="32" y1="176" y2="176" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="176" type="pin wr_clk" />
+ <line x2="32" y1="240" y2="240" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="240" type="pin rd_en" />
+ <line x2="32" y1="272" y2="272" x1="0" />
+ <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin rd_clk" />
+ <line x2="144" y1="800" y2="768" x1="144" />
+ <attrtext style="alignment:BCENTER;fontsize:24;fontname:Arial" attrname="PinName" x="144" y="764" type="pin rst" />
+ <line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin dout[7:0]" />
+ <line x2="544" y1="208" y2="208" x1="576" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="208" type="pin full" />
+ <line x2="544" y1="272" y2="272" x1="576" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="272" type="pin prog_full" />
+ <line x2="544" y1="432" y2="432" x1="576" />
+ <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="432" type="pin empty" />
+ </graph>
+</symbol>
diff --git a/ipcore_dir/fifo.v b/ipcore_dir/fifo.v
new file mode 100644
index 0000000..61e7146
--- /dev/null
+++ b/ipcore_dir/fifo.v
@@ -0,0 +1,175 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2009 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo.v when simulating
+// the core, fifo. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo(
+ rst,
+ wr_clk,
+ rd_clk,
+ din,
+ wr_en,
+ rd_en,
+ dout,
+ full,
+ empty,
+ prog_full);
+
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [31 : 0] din;
+input wr_en;
+input rd_en;
+output [7 : 0] dout;
+output full;
+output empty;
+output prog_full;
+
+// synthesis translate_off
+
+ FIFO_GENERATOR_V6_2 #(
+ .C_COMMON_CLOCK(0),
+ .C_COUNT_TYPE(0),
+ .C_DATA_COUNT_WIDTH(13),
+ .C_DEFAULT_VALUE("BlankString"),
+ .C_DIN_WIDTH(32),
+ .C_DOUT_RST_VAL("0"),
+ .C_DOUT_WIDTH(8),
+ .C_ENABLE_RLOCS(0),
+ .C_ENABLE_RST_SYNC(1),
+ .C_ERROR_INJECTION_TYPE(0),
+ .C_FAMILY("spartan3"),
+ .C_FULL_FLAGS_RST_VAL(1),
+ .C_HAS_ALMOST_EMPTY(0),
+ .C_HAS_ALMOST_FULL(0),
+ .C_HAS_BACKUP(0),
+ .C_HAS_DATA_COUNT(0),
+ .C_HAS_INT_CLK(0),
+ .C_HAS_MEMINIT_FILE(0),
+ .C_HAS_OVERFLOW(0),
+ .C_HAS_RD_DATA_COUNT(0),
+ .C_HAS_RD_RST(0),
+ .C_HAS_RST(1),
+ .C_HAS_SRST(0),
+ .C_HAS_UNDERFLOW(0),
+ .C_HAS_VALID(0),
+ .C_HAS_WR_ACK(0),
+ .C_HAS_WR_DATA_COUNT(0),
+ .C_HAS_WR_RST(0),
+ .C_IMPLEMENTATION_TYPE(2),
+ .C_INIT_WR_PNTR_VAL(0),
+ .C_MEMORY_TYPE(1),
+ .C_MIF_FILE_NAME("BlankString"),
+ .C_MSGON_VAL(1),
+ .C_OPTIMIZATION_MODE(0),
+ .C_OVERFLOW_LOW(0),
+ .C_PRELOAD_LATENCY(1),
+ .C_PRELOAD_REGS(0),
+ .C_PRIM_FIFO_TYPE("8kx4"),
+ .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
+ .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
+ .C_PROG_EMPTY_TYPE(0),
+ .C_PROG_FULL_THRESH_ASSERT_VAL(4096),
+ .C_PROG_FULL_THRESH_NEGATE_VAL(4095),
+ .C_PROG_FULL_TYPE(1),
+ .C_RD_DATA_COUNT_WIDTH(15),
+ .C_RD_DEPTH(32768),
+ .C_RD_FREQ(1),
+ .C_RD_PNTR_WIDTH(15),
+ .C_UNDERFLOW_LOW(0),
+ .C_USE_DOUT_RST(1),
+ .C_USE_ECC(0),
+ .C_USE_EMBEDDED_REG(0),
+ .C_USE_FIFO16_FLAGS(0),
+ .C_USE_FWFT_DATA_COUNT(0),
+ .C_VALID_LOW(0),
+ .C_WR_ACK_LOW(0),
+ .C_WR_DATA_COUNT_WIDTH(13),
+ .C_WR_DEPTH(8192),
+ .C_WR_FREQ(1),
+ .C_WR_PNTR_WIDTH(13),
+ .C_WR_RESPONSE_LATENCY(1))
+ inst (
+ .RST(rst),
+ .WR_CLK(wr_clk),
+ .RD_CLK(rd_clk),
+ .DIN(din),
+ .WR_EN(wr_en),
+ .RD_EN(rd_en),
+ .DOUT(dout),
+ .FULL(full),
+ .EMPTY(empty),
+ .PROG_FULL(prog_full),
+ .BACKUP(),
+ .BACKUP_MARKER(),
+ .CLK(),
+ .SRST(),
+ .WR_RST(),
+ .RD_RST(),
+ .PROG_EMPTY_THRESH(),
+ .PROG_EMPTY_THRESH_ASSERT(),
+ .PROG_EMPTY_THRESH_NEGATE(),
+ .PROG_FULL_THRESH(),
+ .PROG_FULL_THRESH_ASSERT(),
+ .PROG_FULL_THRESH_NEGATE(),
+ .INT_CLK(),
+ .INJECTDBITERR(),
+ .INJECTSBITERR(),
+ .ALMOST_FULL(),
+ .WR_ACK(),
+ .OVERFLOW(),
+ .ALMOST_EMPTY(),
+ .VALID(),
+ .UNDERFLOW(),
+ .DATA_COUNT(),
+ .RD_DATA_COUNT(),
+ .WR_DATA_COUNT(),
+ .PROG_EMPTY(),
+ .SBITERR(),
+ .DBITERR());
+
+
+// synthesis translate_on
+
+// XST black box declaration
+// box_type "black_box"
+// synthesis attribute box_type of fifo is "black_box"
+
+endmodule
+
diff --git a/ipcore_dir/fifo.veo b/ipcore_dir/fifo.veo
new file mode 100644
index 0000000..11483c5
--- /dev/null
+++ b/ipcore_dir/fifo.veo
@@ -0,0 +1,52 @@
+/*******************************************************************************
+* This file is owned and controlled by Xilinx and must be used *
+* solely for design, simulation, implementation and creation of *
+* design files limited to Xilinx devices or technologies. Use *
+* with non-Xilinx devices or technologies is expressly prohibited *
+* and immediately terminates your license. *
+* *
+* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
+* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
+* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
+* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
+* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
+* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
+* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
+* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
+* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
+* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
+* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
+* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
+* FOR A PARTICULAR PURPOSE. *
+* *
+* Xilinx products are not intended for use in life support *
+* appliances, devices, or systems. Use in such applications are *
+* expressly prohibited. *
+* *
+* (c) Copyright 1995-2009 Xilinx, Inc. *
+* All rights reserved. *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo YourInstanceName (
+ .rst(rst),
+ .wr_clk(wr_clk),
+ .rd_clk(rd_clk),
+ .din(din), // Bus [31 : 0]
+ .wr_en(wr_en),
+ .rd_en(rd_en),
+ .dout(dout), // Bus [7 : 0]
+ .full(full),
+ .empty(empty),
+ .prog_full(prog_full));
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo.v when simulating
+// the core, fifo. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/ipcore_dir/fifo.vhd b/ipcore_dir/fifo.vhd
new file mode 100644
index 0000000..5826686
--- /dev/null
+++ b/ipcore_dir/fifo.vhd
@@ -0,0 +1,178 @@
+--------------------------------------------------------------------------------
+-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
+-- --
+-- This file contains confidential and proprietary information --
+-- of Xilinx, Inc. and is protected under U.S. and --
+-- international copyright and other intellectual property --
+-- laws. --
+-- --
+-- DISCLAIMER --
+-- This disclaimer is not a license and does not grant any --
+-- rights to the materials distributed herewith. Except as --
+-- otherwise provided in a valid license issued to you by --
+-- Xilinx, and to the maximum extent permitted by applicable --
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
+-- (2) Xilinx shall not be liable (whether in contract or tort, --
+-- including negligence, or under any other theory of --
+-- liability) for any loss or damage of any kind or nature --
+-- related to, arising under or in connection with these --
+-- materials, including for any direct, or any indirect, --
+-- special, incidental, or consequential loss or damage --
+-- (including loss of data, profits, goodwill, or any type of --
+-- loss or damage suffered as a result of any action brought --
+-- by a third party) even if such damage or loss was --
+-- reasonably foreseeable or Xilinx had been advised of the --
+-- possibility of the same. --
+-- --
+-- CRITICAL APPLICATIONS --
+-- Xilinx products are not designed or intended to be fail- --
+-- safe, or for use in any application requiring fail-safe --
+-- performance, such as life-support or safety devices or --
+-- systems, Class III medical devices, nuclear facilities, --
+-- applications related to the deployment of airbags, or any --
+-- other applications that could lead to death, personal --
+-- injury, or severe property or environmental damage --
+-- (individually and collectively, "Critical --
+-- Applications"). Customer assumes the sole risk and --
+-- liability of any use of Xilinx products in Critical --
+-- Applications, subject only to applicable laws and --
+-- regulations governing limitations on product liability. --
+-- --
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
+-- PART OF THIS FILE AT ALL TIMES. --
+--------------------------------------------------------------------------------
+
+-- Generated from component ID: xilinx.com:ip:fifo_generator:6.2
+
+
+-- You must compile the wrapper file fifo.vhd when simulating
+-- the core, fifo. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY fifo IS
+ port (
+ rst: in std_logic;
+ wr_clk: in std_logic;
+ rd_clk: in std_logic;
+ din: in std_logic_vector(31 downto 0);
+ wr_en: in std_logic;
+ rd_en: in std_logic;
+ dout: out std_logic_vector(7 downto 0);
+ full: out std_logic;
+ empty: out std_logic;
+ prog_full: out std_logic);
+END fifo;
+
+ARCHITECTURE fifo_a OF fifo IS
+-- synthesis translate_off
+component wrapped_fifo
+ port (
+ rst: in std_logic;
+ wr_clk: in std_logic;
+ rd_clk: in std_logic;
+ din: in std_logic_vector(31 downto 0);
+ wr_en: in std_logic;
+ rd_en: in std_logic;
+ dout: out std_logic_vector(7 downto 0);
+ full: out std_logic;
+ empty: out std_logic;
+ prog_full: out std_logic);
+end component;
+
+-- Configuration specification
+ for all : wrapped_fifo use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
+ generic map(
+ c_has_int_clk => 0,
+ c_wr_response_latency => 1,
+ c_rd_freq => 1,
+ c_has_srst => 0,
+ c_enable_rst_sync => 1,
+ c_has_rd_data_count => 0,
+ c_din_width => 32,
+ c_has_wr_data_count => 0,
+ c_full_flags_rst_val => 1,
+ c_implementation_type => 2,
+ c_family => "spartan3",
+ c_use_embedded_reg => 0,
+ c_has_wr_rst => 0,
+ c_wr_freq => 1,
+ c_use_dout_rst => 1,
+ c_underflow_low => 0,
+ c_has_meminit_file => 0,
+ c_has_overflow => 0,
+ c_preload_latency => 1,
+ c_dout_width => 8,
+ c_msgon_val => 1,
+ c_rd_depth => 32768,
+ c_default_value => "BlankString",
+ c_mif_file_name => "BlankString",
+ c_error_injection_type => 0,
+ c_has_underflow => 0,
+ c_has_rd_rst => 0,
+ c_has_almost_full => 0,
+ c_has_rst => 1,
+ c_data_count_width => 13,
+ c_has_wr_ack => 0,
+ c_use_ecc => 0,
+ c_wr_ack_low => 0,
+ c_common_clock => 0,
+ c_rd_pntr_width => 15,
+ c_use_fwft_data_count => 0,
+ c_has_almost_empty => 0,
+ c_rd_data_count_width => 15,
+ c_enable_rlocs => 0,
+ c_wr_pntr_width => 13,
+ c_overflow_low => 0,
+ c_prog_empty_type => 0,
+ c_optimization_mode => 0,
+ c_wr_data_count_width => 13,
+ c_preload_regs => 0,
+ c_dout_rst_val => "0",
+ c_has_data_count => 0,
+ c_prog_full_thresh_negate_val => 4095,
+ c_wr_depth => 8192,
+ c_prog_empty_thresh_negate_val => 3,
+ c_prog_empty_thresh_assert_val => 2,
+ c_has_valid => 0,
+ c_init_wr_pntr_val => 0,
+ c_prog_full_thresh_assert_val => 4096,
+ c_use_fifo16_flags => 0,
+ c_has_backup => 0,
+ c_valid_low => 0,
+ c_prim_fifo_type => "8kx4",
+ c_count_type => 0,
+ c_prog_full_type => 1,
+ c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_fifo
+ port map (
+ rst => rst,
+ wr_clk => wr_clk,
+ rd_clk => rd_clk,
+ din => din,
+ wr_en => wr_en,
+ rd_en => rd_en,
+ dout => dout,
+ full => full,
+ empty => empty,
+ prog_full => prog_full);
+-- synthesis translate_on
+
+END fifo_a;
+
diff --git a/ipcore_dir/fifo.vho b/ipcore_dir/fifo.vho
new file mode 100644
index 0000000..218266f
--- /dev/null
+++ b/ipcore_dir/fifo.vho
@@ -0,0 +1,97 @@
+--------------------------------------------------------------------------------
+-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
+-- --
+-- This file contains confidential and proprietary information --
+-- of Xilinx, Inc. and is protected under U.S. and --
+-- international copyright and other intellectual property --
+-- laws. --
+-- --
+-- DISCLAIMER --
+-- This disclaimer is not a license and does not grant any --
+-- rights to the materials distributed herewith. Except as --
+-- otherwise provided in a valid license issued to you by --
+-- Xilinx, and to the maximum extent permitted by applicable --
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
+-- (2) Xilinx shall not be liable (whether in contract or tort, --
+-- including negligence, or under any other theory of --
+-- liability) for any loss or damage of any kind or nature --
+-- related to, arising under or in connection with these --
+-- materials, including for any direct, or any indirect, --
+-- special, incidental, or consequential loss or damage --
+-- (including loss of data, profits, goodwill, or any type of --
+-- loss or damage suffered as a result of any action brought --
+-- by a third party) even if such damage or loss was --
+-- reasonably foreseeable or Xilinx had been advised of the --
+-- possibility of the same. --
+-- --
+-- CRITICAL APPLICATIONS --
+-- Xilinx products are not designed or intended to be fail- --
+-- safe, or for use in any application requiring fail-safe --
+-- performance, such as life-support or safety devices or --
+-- systems, Class III medical devices, nuclear facilities, --
+-- applications related to the deployment of airbags, or any --
+-- other applications that could lead to death, personal --
+-- injury, or severe property or environmental damage --
+-- (individually and collectively, "Critical --
+-- Applications"). Customer assumes the sole risk and --
+-- liability of any use of Xilinx products in Critical --
+-- Applications, subject only to applicable laws and --
+-- regulations governing limitations on product liability. --
+-- --
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
+-- PART OF THIS FILE AT ALL TIMES. --
+--------------------------------------------------------------------------------
+
+-- Generated from component ID: xilinx.com:ip:fifo_generator:6.2
+
+
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component fifo
+ port (
+ rst: in std_logic;
+ wr_clk: in std_logic;
+ rd_clk: in std_logic;
+ din: in std_logic_vector(31 downto 0);
+ wr_en: in std_logic;
+ rd_en: in std_logic;
+ dout: out std_logic_vector(7 downto 0);
+ full: out std_logic;
+ empty: out std_logic;
+ prog_full: out std_logic);
+end component;
+
+-- Synplicity black box declaration
+attribute syn_black_box : boolean;
+attribute syn_black_box of fifo: component is true;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : fifo
+ port map (
+ rst => rst,
+ wr_clk => wr_clk,
+ rd_clk => rd_clk,
+ din => din,
+ wr_en => wr_en,
+ rd_en => rd_en,
+ dout => dout,
+ full => full,
+ empty => empty,
+ prog_full => prog_full);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file fifo.vhd when simulating
+-- the core, fifo. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
diff --git a/ipcore_dir/fifo.xco b/ipcore_dir/fifo.xco
new file mode 100644
index 0000000..fde520f
--- /dev/null
+++ b/ipcore_dir/fifo.xco
@@ -0,0 +1,91 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.3
+# Date: Thu Nov 14 16:00:10 2013
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:fifo_generator:6.2
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc3s500e
+SET devicefamily = spartan3e
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg320
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -4
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo
+CSET data_count=false
+CSET data_count_width=13
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=4096
+CSET full_threshold_negate_value=4095
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=32
+CSET input_depth=8192
+CSET output_data_width=8
+CSET output_depth=32768
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET read_clock_frequency=1
+CSET read_data_count=false
+CSET read_data_count_width=15
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=false
+CSET write_data_count_width=13
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-10-13T03:35:42Z
+# END Extra information
+GENERATE
+# CRC: 90d0bfa6
diff --git a/ipcore_dir/fifo.xco.bak b/ipcore_dir/fifo.xco.bak
new file mode 100644
index 0000000..9c23d2f
--- /dev/null
+++ b/ipcore_dir/fifo.xco.bak
@@ -0,0 +1,84 @@
+##############################################################
+#
+# Xilinx Core Generator version 12.2
+# Date: Mon May 28 18:27:00 2012
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc3s500e
+SET devicefamily = spartan3e
+SET flowvendor = Foundation_ISE
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = fg320
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -4
+SET verilogsim = true
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 6.2
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=true
+CSET component_name=fifo
+CSET data_count=false
+CSET data_count_width=12
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=2
+CSET empty_threshold_negate_value=3
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET enable_reset_synchronization=true
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=2048
+CSET full_threshold_negate_value=2047
+CSET inject_dbit_error=false
+CSET inject_sbit_error=false
+CSET input_data_width=32
+CSET input_depth=4096
+CSET output_data_width=8
+CSET output_depth=16384
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=Standard_FIFO
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=14
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=false
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=12
+# END Parameters
+GENERATE
+# CRC: 9f6cdb39
diff --git a/ipcore_dir/fifo.xise b/ipcore_dir/fifo.xise
new file mode 100644
index 0000000..6b3fea5
--- /dev/null
+++ b/ipcore_dir/fifo.xise
@@ -0,0 +1,386 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="fifo.ngc" xil_pn:type="FILE_NGC">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+ <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
+ <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
+ <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+ <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
+ <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+ <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+ <property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|fifo|fifo_a" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="fifo.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/fifo" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output File Name" xil_pn:value="fifo" xil_pn:valueState="default"/>
+ <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="fifo_map.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="fifo_timesim.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="fifo_synthesis.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="fifo_translate.v" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
+ <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
+ <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
+ <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+ <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+ <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
+ <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+ <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="fifo" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-11-14T13:01:32" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="53468C5E4BE340C8CFB2C65918BD7686" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/ipcore_dir/fifo_flist.txt b/ipcore_dir/fifo_flist.txt
new file mode 100644
index 0000000..9434e50
--- /dev/null
+++ b/ipcore_dir/fifo_flist.txt
@@ -0,0 +1,14 @@
+# Output products list for <fifo>
+_xmsgs/pn_parser.xmsgs
+fifo.asy
+fifo.gise
+fifo.ngc
+fifo.sym
+fifo.vhd
+fifo.vho
+fifo.xco
+fifo.xise
+fifo_flist.txt
+fifo_generator_readme.txt
+fifo_generator_ug175.pdf
+fifo_xmdf.tcl
diff --git a/ipcore_dir/fifo_generator_readme.txt b/ipcore_dir/fifo_generator_readme.txt
new file mode 100644
index 0000000..2673d68
--- /dev/null
+++ b/ipcore_dir/fifo_generator_readme.txt
@@ -0,0 +1,165 @@
+ Core Name: Xilinx LogiCORE FIFO Generator
+ Version: 6.2
+ Release Date: July 23, 2010
+
+
+================================================================================
+
+This document contains the following sections:
+
+1. Introduction
+2. New Features
+3. Supported Devices
+4. Resolved Issues
+5. Known Issues
+6. Technical Support
+7. Core Release History
+8. Legal Disclaimer
+
+================================================================================
+
+1. INTRODUCTION
+
+For the most recent updates to the IP installation instructions for this core,
+please go to:
+
+ http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+
+For system requirements:
+
+ http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v6.2
+solution. For the latest core updates, see the product page at:
+
+ http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+
+2. NEW FEATURES
+
+ - ISE 12.2 software support
+
+3. SUPPORTED DEVICES
+
+ - SPARTAN-3, SPARTAN-3 XA, SPARTAN-3E SPARTAN-3E XA, SPARTAN-3A, SPARTAN-3A XA, SPARTAN-3ADSP, SPARTAN-3ADSP XA
+ - SPARTAN-6, SPARTAN-6 XA, SPARTAN-6L and QSPARTAN-6
+ - VIRTEX-4
+ - VIRTEX-5 and QVIRTEX-5
+ - VIRTEX-6, VIRTEX-6L and QVIRTEX-6
+
+4. RESOLVED ISSUES
+
+ - In the FIFO Generator core, PROG_FULL does not assert when set to maximum threshold value.
+ - Version fixed: v6.2
+ - CR 553279
+
+ - In the FIFO Generator verilog behavioral model, PROG_EMPTY does not assert/de-assert when the threshold
+ value is passed through parameter.
+ - Version fixed: v6.2
+ - CR 549673
+
+ - In the FIFO Generator GUI, read width is reset to write width when the component name is change.
+ - Version fixed: v6.2
+ - CR 563827
+
+5. KNOWN ISSUES
+
+ The following are known issues for v6.2 of this core at time of release:
+
+ - In the FIFO generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+ into a Virtex-4 coregen project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
+ page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+ - CR 467240
+ - AR 31379
+
+ The most recent information, including known issues, workarounds, and
+ resolutions for this version is provided in the IP Release Notes User Guide
+ located at
+
+ www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+
+
+6. TECHNICAL SUPPORT
+
+ To obtain technical support, create a WebCase at www.xilinx.com/support.
+ Questions are routed to a team with expertise using this product.
+
+ Xilinx provides technical support for use of this product when used
+ according to the guidelines described in the core documentation, and
+ cannot guarantee timing, functionality, or support of this product for
+ designs that do not follow specified guidelines.
+
+7. CORE RELEASE HISTORY
+
+Date By Version Description
+================================================================================
+07/23/2010 Xilinx, Inc. 6.2 ISE 12.2 support
+04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
+12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
+08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
+05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
+04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
+================================================================================
+
+8. Legal Disclaimer
+
+ (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
+
+ This file contains confidential and proprietary information
+ of Xilinx, Inc. and is protected under U.S. and
+ international copyright and other intellectual property
+ laws.
+
+ DISCLAIMER
+ This disclaimer is not a license and does not grant any
+ rights to the materials distributed herewith. Except as
+ otherwise provided in a valid license issued to you by
+ Xilinx, and to the maximum extent permitted by applicable
+ law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+ WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ (2) Xilinx shall not be liable (whether in contract or tort,
+ including negligence, or under any other theory of
+ liability) for any loss or damage of any kind or nature
+ related to, arising under or in connection with these
+ materials, including for any direct, or any indirect,
+ special, incidental, or consequential loss or damage
+ (including loss of data, profits, goodwill, or any type of
+ loss or damage suffered as a result of any action brought
+ by a third party) even if such damage or loss was
+ reasonably foreseeable or Xilinx had been advised of the
+ possibility of the same.
+
+ CRITICAL APPLICATIONS
+ Xilinx products are not designed or intended to be fail-
+ safe, or for use in any application requiring fail-safe
+ performance, such as life-support or safety devices or
+ systems, Class III medical devices, nuclear facilities,
+ applications related to the deployment of airbags, or any
+ other applications that could lead to death, personal
+ injury, or severe property or environmental damage
+ (individually and collectively, "Critical
+ Applications"). Customer assumes the sole risk and
+ liability of any use of Xilinx products in Critical
+ Applications, subject only to applicable laws and
+ regulations governing limitations on product liability.
+
+ THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ PART OF THIS FILE AT ALL TIMES.
diff --git a/ipcore_dir/fifo_generator_ug175.pdf b/ipcore_dir/fifo_generator_ug175.pdf
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HcmV?d00001
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diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main
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index 0000000000000000000000000000000000000000..336370f8091a49f5e89f82fedc83a9ed04bd24ac
GIT binary patch
literal 25
VcmZQzU}9nb;{Q;<00ev>0sw562oC@N
literal 0
HcmV?d00001
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__OBJSTORE__/ProjectNavigator/dpm_project_main/dpm_project_main_StrTbl
new file mode 100755
index 0000000000000000000000000000000000000000..359501c5e254de720bb0edd97879dcdaa4c50d01
GIT binary patch
literal 10
NcmZQz00RyN1^@se00{s9
literal 0
HcmV?d00001
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/Autonym/regkeys
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index 0000000..e69de29
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
new file mode 100755
index 0000000..0da60f5
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/HierarchicalDesign/HDProject/regkeys
@@ -0,0 +1,24 @@
+CommandLine-Map
+
+s
+CommandLine-Ngdbuild
+
+s
+CommandLine-Par
+
+s
+CommandLine-Xst
+
+s
+Previous-NGD
+
+s
+Previous-NGM
+
+s
+Previous-Packed-NCD
+
+s
+Previous-Routed-NCD
+
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys
new file mode 100755
index 0000000..4bd7af1
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ProjectNavigator/regkeys
@@ -0,0 +1,3 @@
+ISE_VERSION_LAST_SAVED_WITH
+11.1
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys
new file mode 100755
index 0000000..e601c65
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ProjectNavigator11/regkeys
@@ -0,0 +1,6 @@
+ISE_VERSION_LAST_SAVED_WITH
+11.1
+s
+XISE_FILE
+fifo_usb_if.xise
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys
new file mode 100755
index 0000000..87cda85
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/XSLTProcess/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/XSLTProcess.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
new file mode 100755
index 0000000..cc20273
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/_ProjRepoInternal_/regkeys
@@ -0,0 +1,21 @@
+ISE_VERSION_CREATED_WITH
+11.1
+s
+ISE_VERSION_LAST_SAVED_WITH
+11.1
+s
+LastRepoDir
+/home/user/Desktop/Exercises/ex3/cores/
+s
+OBJSTORE_VERSION
+1.3
+s
+PROJECT_CREATION_TIMESTAMP
+2010-01-08T17:34:04
+s
+REGISTRY_VERSION
+1.1
+s
+REPOSITORY_VERSION
+1.1
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys
new file mode 100755
index 0000000..949818c
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/bitgen/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/bitgen.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys
new file mode 100755
index 0000000..dae1ec7
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/bitinit/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/bitinit.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/common/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/common/regkeys
new file mode 100755
index 0000000..74ed1c7
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/common/regkeys
@@ -0,0 +1,15 @@
+IncrementalMessagingEnabled
+false
+s
+MessageCaptureEnabled
+true
+s
+MessageFilterFile
+filter.filter
+s
+MessageFilteringEnabled
+false
+s
+RunOnce
+#/PnAutoRun/Scripts/RunOnce_tcl
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys
new file mode 100755
index 0000000..f3969b3
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/cpldfit/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/cpldfit.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys
new file mode 100755
index 0000000..7e5b4bb
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/dumpngdio/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/dumpngdio.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/fuse/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/fuse/regkeys
new file mode 100755
index 0000000..77fa32d
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/fuse/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/fuse.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys
new file mode 100755
index 0000000..e654ecd
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/hprep6/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/hprep6.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/idem/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/idem/regkeys
new file mode 100755
index 0000000..7b9c321
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/idem/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/idem.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/libgen/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/libgen/regkeys
new file mode 100755
index 0000000..a2612da
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/libgen/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/libgen.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/map/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/map/regkeys
new file mode 100755
index 0000000..447e64c
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/map/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/map.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/netgen/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/netgen/regkeys
new file mode 100755
index 0000000..b15e57f
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/netgen/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/netgen.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys
new file mode 100755
index 0000000..2cb66e4
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngc2edif/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/ngc2edif.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys
new file mode 100755
index 0000000..af67ad1
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngcbuild/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/ngcbuild.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys
new file mode 100755
index 0000000..47ac460
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/ngdbuild/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/ngdbuild.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/par/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/par/regkeys
new file mode 100755
index 0000000..17ae8fb
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/par/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/par.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/platgen/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/platgen/regkeys
new file mode 100755
index 0000000..d4497d2
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/platgen/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/platgen.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/runner/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/runner/regkeys
new file mode 100755
index 0000000..d5e13d0
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/runner/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/runner.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/simgen/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/simgen/regkeys
new file mode 100755
index 0000000..e12ea38
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/simgen/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/simgen.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/taengine/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/taengine/regkeys
new file mode 100755
index 0000000..fc0b038
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/taengine/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/taengine.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/trce/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/trce/regkeys
new file mode 100755
index 0000000..cffe0cf
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/trce/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/trce.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/tsim/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/tsim/regkeys
new file mode 100755
index 0000000..52a3e8b
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/tsim/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/tsim.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys
new file mode 100755
index 0000000..2d5cd6a
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/vhpcomp/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/vhpcomp.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys
new file mode 100755
index 0000000..9a5c2fa
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/vlogcomp/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/vlogcomp.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys
new file mode 100755
index 0000000..c3f895c
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/xpwr/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/xpwr.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/xst/regkeys b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/xst/regkeys
new file mode 100755
index 0000000..5b1ae90
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/__REGISTRY__/xst/regkeys
@@ -0,0 +1,3 @@
+ClientMessageOutputFile
+_xmsgs/xst.xmsgs
+s
diff --git a/ipcore_dir/fifo_usb_if_xdb/tmp/ise/version b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/version
new file mode 100755
index 0000000..eec4d22
--- /dev/null
+++ b/ipcore_dir/fifo_usb_if_xdb/tmp/ise/version
@@ -0,0 +1,10 @@
+REPOSITORY_VERSION
+1.1
+REGISTRY_VERSION
+1.1
+OBJSTORE_VERSION
+1.3
+ISE_VERSION_CREATED_WITH
+11.1
+ISE_VERSION_LAST_SAVED_WITH
+11.1
diff --git a/ipcore_dir/fifo_xmdf.tcl b/ipcore_dir/fifo_xmdf.tcl
new file mode 100644
index 0000000..2667b57
--- /dev/null
+++ b/ipcore_dir/fifo_xmdf.tcl
@@ -0,0 +1,79 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo
+}
+# ::fifo_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/ipcore_dir/iseconfig/fifo_usb_if.projectmgr b/ipcore_dir/iseconfig/fifo_usb_if.projectmgr
new file mode 100755
index 0000000..158f41f
--- /dev/null
+++ b/ipcore_dir/iseconfig/fifo_usb_if.projectmgr
@@ -0,0 +1,103 @@
+<?xml version='1.0' encoding='utf-8'?>
+<!--This is an ISE project configuration file.-->
+<!--It holds project specific layout data for the projectmgr plugin.-->
+<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
+<Project version="1" owner="projectmgr" name="fifo_usb_if" >
+ <!--This is an ISE project configuration file.-->
+ <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
+ <ClosedNodes/>
+ <SelectedItems>
+ <SelectedItem>fifo_usb_if - fifo_usb_if_a (E:/Ejemplos_VHDL/Exercises/ex3/cores/fifo_usb_if.vhd)</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001fd000000020000000000000000000000000000000064ffffffff000000810000000000000002000001fd0000000100000000000000000000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>fifo_usb_if - fifo_usb_if_a (E:/Ejemplos_VHDL/Exercises/ex3/cores/fifo_usb_if.vhd)</CurrentItem>
+ </ItemView>
+ <ItemView engineview="SynthesisOnly" sourcetype="DESUT_NGC" guiview="Process" >
+ <ClosedNodes/>
+ <SelectedItems>
+ <SelectedItem>Add Existing Source</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>Add Existing Source</CurrentItem>
+ </ItemView>
+ <ItemView guiview="File" >
+ <ClosedNodes/>
+ <SelectedItems/>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000028e000000040101000100000000000000000000000064ffffffff000000810000000000000004000001240000000100000000000000440000000100000000000000660000000100000000000000c00000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>E:\Ejemplos_VHDL\Exercises\ex3\cores\fifo_usb_if.ngc</CurrentItem>
+ </ItemView>
+ <ItemView guiview="Library" >
+ <ClosedNodes>
+ <ClosedNode>work</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems/>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>work</CurrentItem>
+ </ItemView>
+ <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNode>Configure Target Device</ClosedNode>
+ <ClosedNode>Design Utilities</ClosedNode>
+ <ClosedNode>Implement Design</ClosedNode>
+ <ClosedNode>Synthesize - XST</ClosedNode>
+ <ClosedNode>User Constraints</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
+ <SelectedItem>Add Existing Source</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000064000000010000000100000000000000000000000064ffffffff000000810000000000000001000000640000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>Add Existing Source</CurrentItem>
+ </ItemView>
+ <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
+ <CurrentView>Behavioral Simulation</CurrentView>
+ <ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
+ <ClosedNodes/>
+ <SelectedItems>
+ <SelectedItem>fifo_usb_if - fifo_usb_if_a (E:/Ejemplos_VHDL/Exercises/ex3/cores/fifo_usb_if.vhd)</SelectedItem>
+ </SelectedItems>
+ <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+ <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+ <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000023c000000020000000000000000000000000000000064ffffffff0000008100000000000000020000023c0000000100000000000000000000000100000000</ViewHeaderState>
+ <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+ <CurrentItem>fifo_usb_if - fifo_usb_if_a (E:/Ejemplos_VHDL/Exercises/ex3/cores/fifo_usb_if.vhd)</CurrentItem>
+ </ItemView>
+ <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
+ <ClosedNodes>
+ <ClosedNode>Design Utilities</ClosedNode>
+ </ClosedNodes>
+ <SelectedItems>
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diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg
new file mode 100755
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diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/fifo_usb_if_isim_beh.exe b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/fifo_usb_if_isim_beh.exe
new file mode 100755
index 0000000000000000000000000000000000000000..7d74ba36a38b096e2ac566830b20751306a04a49
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diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/isimcrash.log b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/isimcrash.log
new file mode 100755
index 0000000..e69de29
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/isimkernel.log b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/isimkernel.log
new file mode 100755
index 0000000..8f7b352
--- /dev/null
+++ b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/isimkernel.log
@@ -0,0 +1,29 @@
+Command line:
+ fifo_usb_if_isim_beh.exe
+ -simmode gui
+ -simrunnum 0
+ -socket 49568
+
+Tue Sep 14 09:07:55 2010
+
+
+ Elaboration Time: 0.0624 sec
+
+ Current Memory Usage: 497.521 Meg
+
+ Total Signals : 194
+ Total Nets : 346
+ Total Signal Drivers : 79
+ Total Blocks : 25
+ Total Primitive Blocks : 19
+ Total Processes : 60
+ Total Traceable Variables : 126
+ Total Scalar Nets and Variables : 870
+Total Line Count : 254
+
+ Total Simulation Time: 0.0624 sec
+
+ Current Memory Usage: 497.521 Meg
+
+Tue Sep 14 09:08:08 2010
+
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/libPortability.dll b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/libPortability.dll
new file mode 100755
index 0000000000000000000000000000000000000000..680995e573d8e7ea2780bf0ba61288d0fa53add2
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HcmV?d00001
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/netId.dat b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/netId.dat
new file mode 100755
index 0000000000000000000000000000000000000000..b9952409a17ad62a5e6783fcab07f3381f624c02
GIT binary patch
literal 92
zcmWm0I|_g>6hzTyX>I2x+NsNsAVEaL{cpyTfy<dTA`aDcO+>Hk4?H=taN@<pn=>EQ
ME&i(4-}rIo53M}|`~Uy|
literal 0
HcmV?d00001
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/tmp_save/_1 b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/tmp_save/_1
new file mode 100755
index 0000000000000000000000000000000000000000..932f76685284229953b81ea70f5646d75f8ec021
GIT binary patch
literal 18697
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literal 0
HcmV?d00001
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.c b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.c
new file mode 100755
index 0000000..95ddd43
--- /dev/null
+++ b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.c
@@ -0,0 +1,31 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/***********************************************************************/
+
+/* This file is designed for use with ISim build 0x7dea747 */
+
+#define XSI_HIDE_SYMBOL_SPEC true
+#include "xsi.h"
+#include <memory.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+
+
+
+
+extern void work_a_1176593161_2718564866_init()
+{
+ xsi_register_didat("work_a_1176593161_2718564866", "isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.didat");
+}
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.didat b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.didat
new file mode 100755
index 0000000000000000000000000000000000000000..17e2e66d402eefc0d998206b5ad997fb61cd72d4
GIT binary patch
literal 9520
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QDCX5-anQ6)-DQ9O1hZ3^+yDRo
literal 0
HcmV?d00001
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.nt64.obj b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/a_1176593161_2718564866.nt64.obj
new file mode 100755
index 0000000000000000000000000000000000000000..d0b5b8f8252cadbee9cc2bfed17efdcb2219c998
GIT binary patch
literal 679
zcmaJ;!AiqG5S=suL98b|Dn0hJC2G@ptDul$?;gg)Z0e%5B^xnEq2R5MkMRQv`U!r9
z-(a2D6-labVP<FEdpkSKB+nl3i5-Bpi98UwEOHZD*P-i$?3^@wT(S;~uS62%kwKc>
z2*xWBYu&7{%oFRfdciqS?;8)P-Y8srbi?I7GvTs*LD$+Qi?{A;S(ZwxX)jgj3?Foi
zDn$k`mN!BcQZV^A%WiuS`u-s3pC0>xk4FQ4*bh#IK_C)EZ2(KKL9)@)7UkPy9_;=^
zdlc;$Or+{gQpD$T4KOiNv{SdJ^@rbyL$hreO_hb(R+x631NJphbt5gKsnI5>Zi8RD
yfBjY21b6B>@$W)}oK?^kTvFCBF>wv}-$YT}s~iy3bdFePg_)cvoy!dEHogD@5?%ZN
literal 0
HcmV?d00001
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/fifo_usb_if_isim_beh.exe_main.c b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/fifo_usb_if_isim_beh.exe_main.c
new file mode 100755
index 0000000..a9c7620
--- /dev/null
+++ b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/fifo_usb_if_isim_beh.exe_main.c
@@ -0,0 +1,48 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/***********************************************************************/
+
+#include "xsi.h"
+
+struct XSI_INFO xsi_info;
+
+char *IEEE_P_2592010699;
+char *STD_STANDARD;
+char *IEEE_P_3499444699;
+char *IEEE_P_3620187407;
+
+
+int main(int argc, char **argv)
+{
+ xsi_init_design(argc, argv);
+ xsi_register_info(&xsi_info);
+
+ xsi_register_min_prec_unit(-12);
+ ieee_p_2592010699_init();
+ ieee_p_3499444699_init();
+ ieee_p_3620187407_init();
+ xilinxcorelib_a_4048593843_3212880686_init();
+ xilinxcorelib_a_3173924170_3212880686_init();
+ xilinxcorelib_a_1848741551_3212880686_init();
+ work_a_1176593161_2718564866_init();
+
+
+ xsi_register_tops("work_a_1176593161_2718564866");
+
+ IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
+ xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
+ STD_STANDARD = xsi_get_engine_memory("std_standard");
+ IEEE_P_3499444699 = xsi_get_engine_memory("ieee_p_3499444699");
+ IEEE_P_3620187407 = xsi_get_engine_memory("ieee_p_3620187407");
+
+ return xsi_run_simulation(argc, argv);
+
+}
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/fifo_usb_if_isim_beh.exe_main.nt64.obj b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/work/fifo_usb_if_isim_beh.exe_main.nt64.obj
new file mode 100755
index 0000000000000000000000000000000000000000..affe88d4e6be01b1ab0701e446505cb451be4926
GIT binary patch
literal 2092
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diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_1848741551_3212880686.c b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_1848741551_3212880686.c
new file mode 100755
index 0000000..71180df
--- /dev/null
+++ b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_1848741551_3212880686.c
@@ -0,0 +1,1090 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/***********************************************************************/
+
+/* This file is designed for use with ISim build 0x7dea747 */
+
+#define XSI_HIDE_SYMBOL_SPEC true
+#include "xsi.h"
+#include <memory.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+extern char *IEEE_P_2592010699;
+extern char *STD_STANDARD;
+static const char *ng2 = "Function int_2_std_logic_vector ended without a return statement";
+
+unsigned char ieee_p_2592010699_sub_1605435078_2592010699(char *, unsigned char , unsigned char );
+unsigned char ieee_p_2592010699_sub_1690584930_2592010699(char *, unsigned char );
+
+
+char *xilinxcorelib_a_1848741551_3212880686_sub_445809469_3212880686(char *t1, char *t2, char *t3, char *t4)
+{
+ char t5[248];
+ char t6[24];
+ char t16[16];
+ char t37[8];
+ char *t0;
+ int t7;
+ char *t8;
+ int t9;
+ char *t10;
+ int t11;
+ char *t12;
+ int t13;
+ int t14;
+ unsigned int t15;
+ int t17;
+ char *t18;
+ int t19;
+ char *t20;
+ int t21;
+ char *t22;
+ int t23;
+ char *t24;
+ char *t25;
+ int t26;
+ unsigned int t27;
+ char *t28;
+ char *t29;
+ char *t30;
+ char *t31;
+ char *t32;
+ char *t33;
+ char *t34;
+ char *t35;
+ char *t36;
+ char *t38;
+ char *t39;
+ char *t40;
+ unsigned char t41;
+ char *t42;
+ int t43;
+ char *t44;
+ int t45;
+ char *t46;
+ int t47;
+ char *t48;
+ int t49;
+ int t50;
+ int t51;
+ char *t52;
+ char *t53;
+ int t54;
+ unsigned char t55;
+ int t56;
+ char *t57;
+ int t58;
+ int t59;
+ char *t60;
+ int t61;
+ unsigned int t62;
+ unsigned int t63;
+ char *t64;
+ unsigned char t65;
+ unsigned char t66;
+ char *t67;
+ char *t68;
+ int t69;
+ char *t70;
+ int t71;
+ int t72;
+ unsigned int t73;
+ char *t74;
+ int t75;
+ unsigned int t76;
+ unsigned int t77;
+ char *t78;
+
+LAB0: t8 = (t4 + 0U);
+ t9 = *((int *)t8);
+ t10 = (t4 + 4U);
+ t11 = *((int *)t10);
+ t12 = (t4 + 8U);
+ t13 = *((int *)t12);
+ if (t9 > t11)
+ goto LAB2;
+
+LAB3: if (t13 == -1)
+ goto LAB7;
+
+LAB8: t7 = t11;
+
+LAB4: t14 = (0 - t7);
+ t15 = (t14 * -1);
+ t15 = (t15 + 1);
+ t15 = (t15 * 1U);
+ t18 = (t4 + 0U);
+ t19 = *((int *)t18);
+ t20 = (t4 + 4U);
+ t21 = *((int *)t20);
+ t22 = (t4 + 8U);
+ t23 = *((int *)t22);
+ if (t19 > t21)
+ goto LAB9;
+
+LAB10: if (t23 == -1)
+ goto LAB14;
+
+LAB15: t17 = t21;
+
+LAB11: t24 = (t16 + 0U);
+ t25 = (t24 + 0U);
+ *((int *)t25) = t17;
+ t25 = (t24 + 4U);
+ *((int *)t25) = 0;
+ t25 = (t24 + 8U);
+ *((int *)t25) = -1;
+ t26 = (0 - t17);
+ t27 = (t26 * -1);
+ t27 = (t27 + 1);
+ t25 = (t24 + 12U);
+ *((unsigned int *)t25) = t27;
+ t25 = (t5 + 4U);
+ t28 = ((IEEE_P_2592010699) + 4024);
+ t29 = (t25 + 88U);
+ *((char **)t29) = t28;
+ t30 = (char *)alloca(t15);
+ t31 = (t25 + 56U);
+ *((char **)t31) = t30;
+ xsi_type_set_default_value(t28, t30, t16);
+ t32 = (t25 + 64U);
+ *((char **)t32) = t16;
+ t33 = (t25 + 80U);
+ *((unsigned int *)t33) = t15;
+ t34 = (t5 + 124U);
+ t35 = ((STD_STANDARD) + 384);
+ t36 = (t34 + 88U);
+ *((char **)t36) = t35;
+ t38 = (t34 + 56U);
+ *((char **)t38) = t37;
+ *((int *)t37) = 0;
+ t39 = (t34 + 80U);
+ *((unsigned int *)t39) = 4U;
+ t40 = (t6 + 4U);
+ t41 = (t3 != 0);
+ if (t41 == 1)
+ goto LAB17;
+
+LAB16: t42 = (t6 + 12U);
+ *((char **)t42) = t4;
+ t44 = (t4 + 0U);
+ t45 = *((int *)t44);
+ t46 = (t4 + 4U);
+ t47 = *((int *)t46);
+ t48 = (t4 + 8U);
+ t49 = *((int *)t48);
+ if (t45 > t47)
+ goto LAB22;
+
+LAB23: if (t49 == -1)
+ goto LAB27;
+
+LAB28: t43 = t47;
+
+LAB24: t50 = 0;
+ t51 = t43;
+
+LAB18: if (t50 <= t51)
+ goto LAB19;
+
+LAB21: t8 = (t25 + 56U);
+ t10 = *((char **)t8);
+ t8 = (t16 + 12U);
+ t15 = *((unsigned int *)t8);
+ t15 = (t15 * 1U);
+ t0 = xsi_get_transient_memory(t15);
+ memcpy(t0, t10, t15);
+ t12 = (t16 + 0U);
+ t7 = *((int *)t12);
+ t18 = (t16 + 4U);
+ t9 = *((int *)t18);
+ t20 = (t16 + 8U);
+ t11 = *((int *)t20);
+ t22 = (t2 + 0U);
+ t24 = (t22 + 0U);
+ *((int *)t24) = t7;
+ t24 = (t22 + 4U);
+ *((int *)t24) = t9;
+ t24 = (t22 + 8U);
+ *((int *)t24) = t11;
+ t13 = (t9 - t7);
+ t27 = (t13 * t11);
+ t27 = (t27 + 1);
+ t24 = (t22 + 12U);
+ *((unsigned int *)t24) = t27;
+
+LAB1: return t0;
+LAB2: if (t13 == 1)
+ goto LAB5;
+
+LAB6: t7 = t9;
+ goto LAB4;
+
+LAB5: t7 = t11;
+ goto LAB4;
+
+LAB7: t7 = t9;
+ goto LAB4;
+
+LAB9: if (t23 == 1)
+ goto LAB12;
+
+LAB13: t17 = t19;
+ goto LAB11;
+
+LAB12: t17 = t21;
+ goto LAB11;
+
+LAB14: t17 = t19;
+ goto LAB11;
+
+LAB17: *((char **)t40) = *((char **)t3);
+ goto LAB16;
+
+LAB19: t52 = (t34 + 56U);
+ t53 = *((char **)t52);
+ t54 = *((int *)t53);
+ t55 = (t54 == 1);
+ if (t55 != 0)
+ goto LAB29;
+
+LAB31: t8 = (t4 + 0U);
+ t7 = *((int *)t8);
+ t10 = (t4 + 8U);
+ t9 = *((int *)t10);
+ t11 = (t50 - t7);
+ t15 = (t11 * t9);
+ t12 = (t4 + 4U);
+ t13 = *((int *)t12);
+ xsi_vhdl_check_range_of_index(t7, t13, t9, t50);
+ t27 = (1U * t15);
+ t62 = (0 + t27);
+ t18 = (t3 + t62);
+ t41 = *((unsigned char *)t18);
+ t20 = (t25 + 56U);
+ t22 = *((char **)t20);
+ t20 = (t16 + 0U);
+ t14 = *((int *)t20);
+ t24 = (t16 + 8U);
+ t17 = *((int *)t24);
+ t19 = (t50 - t14);
+ t63 = (t19 * t17);
+ t28 = (t16 + 4U);
+ t21 = *((int *)t28);
+ xsi_vhdl_check_range_of_index(t14, t21, t17, t50);
+ t73 = (1U * t63);
+ t76 = (0 + t73);
+ t29 = (t22 + t76);
+ *((unsigned char *)t29) = t41;
+ t8 = (t4 + 0U);
+ t7 = *((int *)t8);
+ t10 = (t4 + 8U);
+ t9 = *((int *)t10);
+ t11 = (t50 - t7);
+ t15 = (t11 * t9);
+ t12 = (t4 + 4U);
+ t13 = *((int *)t12);
+ xsi_vhdl_check_range_of_index(t7, t13, t9, t50);
+ t27 = (1U * t15);
+ t62 = (0 + t27);
+ t18 = (t3 + t62);
+ t41 = *((unsigned char *)t18);
+ t55 = (t41 == (unsigned char)3);
+ if (t55 != 0)
+ goto LAB35;
+
+LAB37:
+LAB36:
+LAB30:
+LAB20: if (t50 == t51)
+ goto LAB21;
+
+LAB38: t7 = (t50 + 1);
+ t50 = t7;
+ goto LAB18;
+
+LAB22: if (t49 == 1)
+ goto LAB25;
+
+LAB26: t43 = t45;
+ goto LAB24;
+
+LAB25: t43 = t47;
+ goto LAB24;
+
+LAB27: t43 = t45;
+ goto LAB24;
+
+LAB29: t52 = (t4 + 0U);
+ t56 = *((int *)t52);
+ t57 = (t4 + 8U);
+ t58 = *((int *)t57);
+ t59 = (t50 - t56);
+ t27 = (t59 * t58);
+ t60 = (t4 + 4U);
+ t61 = *((int *)t60);
+ xsi_vhdl_check_range_of_index(t56, t61, t58, t50);
+ t62 = (1U * t27);
+ t63 = (0 + t62);
+ t64 = (t3 + t63);
+ t65 = *((unsigned char *)t64);
+ t66 = (t65 == (unsigned char)2);
+ if (t66 != 0)
+ goto LAB32;
+
+LAB34: t8 = (t25 + 56U);
+ t10 = *((char **)t8);
+ t8 = (t16 + 0U);
+ t7 = *((int *)t8);
+ t12 = (t16 + 8U);
+ t9 = *((int *)t12);
+ t11 = (t50 - t7);
+ t15 = (t11 * t9);
+ t18 = (t16 + 4U);
+ t13 = *((int *)t18);
+ xsi_vhdl_check_range_of_index(t7, t13, t9, t50);
+ t27 = (1U * t15);
+ t62 = (0 + t27);
+ t20 = (t10 + t62);
+ *((unsigned char *)t20) = (unsigned char)2;
+
+LAB33: goto LAB30;
+
+LAB32: t67 = (t25 + 56U);
+ t68 = *((char **)t67);
+ t67 = (t16 + 0U);
+ t69 = *((int *)t67);
+ t70 = (t16 + 8U);
+ t71 = *((int *)t70);
+ t72 = (t50 - t69);
+ t73 = (t72 * t71);
+ t74 = (t16 + 4U);
+ t75 = *((int *)t74);
+ xsi_vhdl_check_range_of_index(t69, t75, t71, t50);
+ t76 = (1U * t73);
+ t77 = (0 + t76);
+ t78 = (t68 + t77);
+ *((unsigned char *)t78) = (unsigned char)3;
+ goto LAB33;
+
+LAB35: t20 = (t34 + 56U);
+ t22 = *((char **)t20);
+ t20 = (t22 + 0);
+ *((int *)t20) = 1;
+ goto LAB36;
+
+LAB39:;
+}
+
+char *xilinxcorelib_a_1848741551_3212880686_sub_1670819029_3212880686(char *t1, char *t2, int t3, int t4)
+{
+ char t5[248];
+ char t6[16];
+ char t10[8];
+ char t16[16];
+ char t39[16];
+ char *t0;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t11;
+ char *t12;
+ int t13;
+ int t14;
+ unsigned int t15;
+ int t17;
+ char *t18;
+ char *t19;
+ int t20;
+ unsigned int t21;
+ char *t22;
+ char *t23;
+ char *t24;
+ char *t25;
+ char *t26;
+ char *t27;
+ char *t28;
+ char *t29;
+ unsigned char t30;
+ int t31;
+ int t32;
+ char *t33;
+ char *t34;
+ int t35;
+ int t36;
+ int t37;
+ unsigned int t38;
+
+LAB0: t7 = (t5 + 4U);
+ t8 = ((STD_STANDARD) + 384);
+ t9 = (t7 + 88U);
+ *((char **)t9) = t8;
+ t11 = (t7 + 56U);
+ *((char **)t11) = t10;
+ *((int *)t10) = t3;
+ t12 = (t7 + 80U);
+ *((unsigned int *)t12) = 4U;
+ t13 = (t4 - 1);
+ t14 = (0 - t13);
+ t15 = (t14 * -1);
+ t15 = (t15 + 1);
+ t15 = (t15 * 1U);
+ t17 = (t4 - 1);
+ t18 = (t16 + 0U);
+ t19 = (t18 + 0U);
+ *((int *)t19) = t17;
+ t19 = (t18 + 4U);
+ *((int *)t19) = 0;
+ t19 = (t18 + 8U);
+ *((int *)t19) = -1;
+ t20 = (0 - t17);
+ t21 = (t20 * -1);
+ t21 = (t21 + 1);
+ t19 = (t18 + 12U);
+ *((unsigned int *)t19) = t21;
+ t19 = (t5 + 124U);
+ t22 = ((IEEE_P_2592010699) + 4024);
+ t23 = (t19 + 88U);
+ *((char **)t23) = t22;
+ t24 = (char *)alloca(t15);
+ t25 = (t19 + 56U);
+ *((char **)t25) = t24;
+ xsi_type_set_default_value(t22, t24, t16);
+ t26 = (t19 + 64U);
+ *((char **)t26) = t16;
+ t27 = (t19 + 80U);
+ *((unsigned int *)t27) = t15;
+ t28 = (t6 + 4U);
+ *((int *)t28) = t3;
+ t29 = (t6 + 8U);
+ *((int *)t29) = t4;
+ t30 = (t3 < 0);
+ if (t30 != 0)
+ goto LAB2;
+
+LAB4:
+LAB3: t13 = (t4 - 1);
+ t14 = 0;
+ t17 = t13;
+
+LAB5: if (t14 <= t17)
+ goto LAB6;
+
+LAB8: t30 = (t3 < 0);
+ if (t30 != 0)
+ goto LAB13;
+
+LAB15: t8 = (t19 + 56U);
+ t9 = *((char **)t8);
+ t8 = (t16 + 12U);
+ t15 = *((unsigned int *)t8);
+ t15 = (t15 * 1U);
+ t0 = xsi_get_transient_memory(t15);
+ memcpy(t0, t9, t15);
+ t11 = (t16 + 0U);
+ t13 = *((int *)t11);
+ t12 = (t16 + 4U);
+ t14 = *((int *)t12);
+ t18 = (t16 + 8U);
+ t17 = *((int *)t18);
+ t22 = (t2 + 0U);
+ t23 = (t22 + 0U);
+ *((int *)t23) = t13;
+ t23 = (t22 + 4U);
+ *((int *)t23) = t14;
+ t23 = (t22 + 8U);
+ *((int *)t23) = t17;
+ t20 = (t14 - t13);
+ t21 = (t20 * t17);
+ t21 = (t21 + 1);
+ t23 = (t22 + 12U);
+ *((unsigned int *)t23) = t21;
+
+LAB1: return t0;
+LAB2: t31 = (1 * t3);
+ t32 = (-(t31));
+ t33 = (t7 + 56U);
+ t34 = *((char **)t33);
+ t33 = (t34 + 0);
+ *((int *)t33) = t32;
+ goto LAB3;
+
+LAB6: t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ t20 = *((int *)t9);
+ t31 = xsi_vhdl_mod(t20, 2);
+ t30 = (t31 == 0);
+ if (t30 != 0)
+ goto LAB9;
+
+LAB11: t8 = (t19 + 56U);
+ t9 = *((char **)t8);
+ t8 = (t16 + 0U);
+ t13 = *((int *)t8);
+ t11 = (t16 + 8U);
+ t20 = *((int *)t11);
+ t31 = (t14 - t13);
+ t15 = (t31 * t20);
+ t12 = (t16 + 4U);
+ t32 = *((int *)t12);
+ xsi_vhdl_check_range_of_index(t13, t32, t20, t14);
+ t21 = (1U * t15);
+ t38 = (0 + t21);
+ t18 = (t9 + t38);
+ *((unsigned char *)t18) = (unsigned char)3;
+
+LAB10: t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ t13 = *((int *)t9);
+ t20 = (t13 / 2);
+ t8 = (t7 + 56U);
+ t11 = *((char **)t8);
+ t8 = (t11 + 0);
+ *((int *)t8) = t20;
+
+LAB7: if (t14 == t17)
+ goto LAB8;
+
+LAB12: t13 = (t14 + 1);
+ t14 = t13;
+ goto LAB5;
+
+LAB9: t8 = (t19 + 56U);
+ t11 = *((char **)t8);
+ t8 = (t16 + 0U);
+ t32 = *((int *)t8);
+ t12 = (t16 + 8U);
+ t35 = *((int *)t12);
+ t36 = (t14 - t32);
+ t15 = (t36 * t35);
+ t18 = (t16 + 4U);
+ t37 = *((int *)t18);
+ xsi_vhdl_check_range_of_index(t32, t37, t35, t14);
+ t21 = (1U * t15);
+ t38 = (0 + t21);
+ t22 = (t11 + t38);
+ *((unsigned char *)t22) = (unsigned char)2;
+ goto LAB10;
+
+LAB13: t8 = (t19 + 56U);
+ t9 = *((char **)t8);
+ t8 = xilinxcorelib_a_1848741551_3212880686_sub_445809469_3212880686(t1, t39, t9, t16);
+ t11 = (t39 + 12U);
+ t15 = *((unsigned int *)t11);
+ t15 = (t15 * 1U);
+ t0 = xsi_get_transient_memory(t15);
+ memcpy(t0, t8, t15);
+ t12 = (t39 + 0U);
+ t13 = *((int *)t12);
+ t18 = (t39 + 4U);
+ t14 = *((int *)t18);
+ t22 = (t39 + 8U);
+ t17 = *((int *)t22);
+ t23 = (t2 + 0U);
+ t25 = (t23 + 0U);
+ *((int *)t25) = t13;
+ t25 = (t23 + 4U);
+ *((int *)t25) = t14;
+ t25 = (t23 + 8U);
+ *((int *)t25) = t17;
+ t20 = (t14 - t13);
+ t21 = (t20 * t17);
+ t21 = (t21 + 1);
+ t25 = (t23 + 12U);
+ *((unsigned int *)t25) = t21;
+ goto LAB1;
+
+LAB14: xsi_error(ng2);
+ t0 = 0;
+ goto LAB1;
+
+LAB16: goto LAB14;
+
+LAB17: goto LAB14;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_0(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+
+LAB0:
+LAB3: t1 = (t0 + 25040);
+ t2 = (t1 + 56U);
+ t3 = *((char **)t2);
+ t4 = (t3 + 56U);
+ t5 = *((char **)t4);
+ *((unsigned char *)t5) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2:
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_1(char *t0)
+{
+ unsigned char t1;
+ char *t2;
+
+LAB0: t1 = (1 != 4);
+ if (t1 == 0)
+ goto LAB2;
+
+LAB3:
+LAB1: return;
+LAB2: t2 = (t0 + 39421);
+ xsi_report(t2, 370U, (unsigned char)3);
+ goto LAB3;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_2(char *t0)
+{
+ unsigned char t1;
+ char *t2;
+
+LAB0: t1 = (2 != 2);
+ if (t1 == 0)
+ goto LAB2;
+
+LAB3:
+LAB1: return;
+LAB2: t2 = (t0 + 39791);
+ xsi_report(t2, 428U, (unsigned char)0);
+ goto LAB3;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_3(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 3952U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 25104);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t8 = (t0 + 24784);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_4(char *t0)
+{
+ unsigned char t1;
+ char *t2;
+ char *t3;
+ unsigned char t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ unsigned char t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+ char *t16;
+
+LAB0: t1 = (1 == 0);
+ if (t1 != 0)
+ goto LAB3;
+
+LAB4:
+LAB5: t9 = (t0 + 4432U);
+ t10 = *((char **)t9);
+ t11 = *((unsigned char *)t10);
+ t9 = (t0 + 25168);
+ t12 = (t9 + 56U);
+ t13 = *((char **)t12);
+ t14 = (t13 + 56U);
+ t15 = *((char **)t14);
+ *((unsigned char *)t15) = t11;
+ xsi_driver_first_trans_fast(t9);
+
+LAB2: t16 = (t0 + 24800);
+ *((int *)t16) = 1;
+
+LAB1: return;
+LAB3: t2 = (t0 + 4272U);
+ t3 = *((char **)t2);
+ t4 = *((unsigned char *)t3);
+ t2 = (t0 + 25168);
+ t5 = (t2 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = t4;
+ xsi_driver_first_trans_fast(t2);
+ goto LAB2;
+
+LAB6: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_5(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+
+LAB0:
+LAB3: t1 = (t0 + 9552U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 25232);
+ t3 = (t1 + 56U);
+ t4 = *((char **)t3);
+ t5 = (t4 + 56U);
+ t6 = *((char **)t5);
+ memcpy(t6, t2, 13U);
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t7 = (t0 + 24816);
+ *((int *)t7) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_6(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+
+LAB0:
+LAB3: t1 = (t0 + 9712U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 25296);
+ t3 = (t1 + 56U);
+ t4 = *((char **)t3);
+ t5 = (t4 + 56U);
+ t6 = *((char **)t5);
+ memcpy(t6, t2, 13U);
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t7 = (t0 + 24832);
+ *((int *)t7) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_7(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ unsigned char t5;
+ unsigned char t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+
+LAB0:
+LAB3: t1 = (t0 + 4112U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 10832U);
+ t4 = *((char **)t1);
+ t5 = *((unsigned char *)t4);
+ t6 = ieee_p_2592010699_sub_1605435078_2592010699(IEEE_P_2592010699, t3, t5);
+ t1 = (t0 + 25360);
+ t7 = (t1 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((unsigned char *)t10) = t6;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t11 = (t0 + 24848);
+ *((int *)t11) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_8(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ unsigned char t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+ char *t12;
+
+LAB0:
+LAB3: t1 = (t0 + 4912U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 10512U);
+ t4 = *((char **)t1);
+ t5 = *((unsigned char *)t4);
+ t6 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t5);
+ t7 = ieee_p_2592010699_sub_1605435078_2592010699(IEEE_P_2592010699, t3, t6);
+ t1 = (t0 + 25424);
+ t8 = (t1 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ *((unsigned char *)t11) = t7;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t12 = (t0 + 24864);
+ *((int *)t12) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_9(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+
+LAB0:
+LAB3: t1 = (t0 + 10672U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 25488);
+ t3 = (t1 + 56U);
+ t4 = *((char **)t3);
+ t5 = (t4 + 56U);
+ t6 = *((char **)t5);
+ memcpy(t6, t2, 8U);
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t7 = (t0 + 24880);
+ *((int *)t7) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_10(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 10832U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 25552);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 24896);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_11(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 10992U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 25616);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 24912);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_12(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 11312U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 25680);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 24928);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_13(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 11152U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 25744);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 24944);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_1848741551_3212880686_p_14(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 10512U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 25808);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 24960);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+
+extern void xilinxcorelib_a_1848741551_3212880686_init()
+{
+ static char *pe[] = {(void *)xilinxcorelib_a_1848741551_3212880686_p_0,(void *)xilinxcorelib_a_1848741551_3212880686_p_1,(void *)xilinxcorelib_a_1848741551_3212880686_p_2,(void *)xilinxcorelib_a_1848741551_3212880686_p_3,(void *)xilinxcorelib_a_1848741551_3212880686_p_4,(void *)xilinxcorelib_a_1848741551_3212880686_p_5,(void *)xilinxcorelib_a_1848741551_3212880686_p_6,(void *)xilinxcorelib_a_1848741551_3212880686_p_7,(void *)xilinxcorelib_a_1848741551_3212880686_p_8,(void *)xilinxcorelib_a_1848741551_3212880686_p_9,(void *)xilinxcorelib_a_1848741551_3212880686_p_10,(void *)xilinxcorelib_a_1848741551_3212880686_p_11,(void *)xilinxcorelib_a_1848741551_3212880686_p_12,(void *)xilinxcorelib_a_1848741551_3212880686_p_13,(void *)xilinxcorelib_a_1848741551_3212880686_p_14};
+ static char *se[] = {(void *)xilinxcorelib_a_1848741551_3212880686_sub_445809469_3212880686,(void *)xilinxcorelib_a_1848741551_3212880686_sub_1670819029_3212880686};
+ xsi_register_didat("xilinxcorelib_a_1848741551_3212880686", "isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_1848741551_3212880686.didat");
+ xsi_register_executes(pe);
+ xsi_register_subprogram_executes(se);
+}
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_1848741551_3212880686.didat b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_1848741551_3212880686.didat
new file mode 100755
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HcmV?d00001
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.c b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.c
new file mode 100755
index 0000000..aa33fb3
--- /dev/null
+++ b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.c
@@ -0,0 +1,2229 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/***********************************************************************/
+
+/* This file is designed for use with ISim build 0x7dea747 */
+
+#define XSI_HIDE_SYMBOL_SPEC true
+#include "xsi.h"
+#include <memory.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+extern char *IEEE_P_2592010699;
+extern char *STD_STANDARD;
+
+unsigned char ieee_p_2592010699_sub_1605435078_2592010699(char *, unsigned char , unsigned char );
+unsigned char ieee_p_2592010699_sub_1690584930_2592010699(char *, unsigned char );
+unsigned char ieee_p_2592010699_sub_2545490612_2592010699(char *, unsigned char , unsigned char );
+
+
+char *xilinxcorelib_a_3173924170_3212880686_sub_3703097363_3212880686(char *t1, char *t2, char *t3, char *t4, int t5)
+{
+ char t6[368];
+ char t7[24];
+ char t16[16];
+ char t28[16];
+ char t34[8];
+ char t41[8];
+ char *t0;
+ int t8;
+ int t9;
+ unsigned int t10;
+ char *t11;
+ char *t12;
+ int t13;
+ int t14;
+ unsigned int t15;
+ int t17;
+ char *t18;
+ char *t19;
+ int t20;
+ unsigned int t21;
+ char *t22;
+ char *t23;
+ char *t24;
+ char *t25;
+ char *t26;
+ char *t27;
+ char *t29;
+ char *t30;
+ int t31;
+ char *t32;
+ char *t33;
+ char *t35;
+ char *t36;
+ char *t37;
+ char *t38;
+ char *t39;
+ char *t40;
+ char *t42;
+ char *t43;
+ char *t44;
+ unsigned char t45;
+ char *t46;
+ char *t47;
+ char *t48;
+ int t49;
+ int t50;
+ char *t51;
+ int t52;
+ char *t53;
+ int t54;
+ int t55;
+ int t56;
+ int t57;
+ int t58;
+ char *t59;
+ int t60;
+ char *t61;
+ int t62;
+ int t63;
+ unsigned int t64;
+ unsigned int t65;
+ char *t66;
+ unsigned char t67;
+ char *t68;
+ char *t69;
+ unsigned int t70;
+ char *t71;
+ char *t72;
+ char *t73;
+ char *t74;
+ char *t75;
+ unsigned int t76;
+ int t77;
+ static char *nl0[] = {&&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB9, &&LAB10, &&LAB11, &&LAB12, &&LAB13, &&LAB14, &&LAB15, &&LAB16, &&LAB17, &&LAB18, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB19, &&LAB21, &&LAB23, &&LAB25, &&LAB27, &&LAB29, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB20, &&LAB22, &&LAB24, &&LAB26, &&LAB28, &&LAB30, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31};
+
+LAB0: t8 = (t5 - 1);
+ t9 = (0 - t8);
+ t10 = (t9 * -1);
+ t10 = (t10 + 1);
+ t10 = (t10 * 1U);
+ t11 = xsi_get_transient_memory(t10);
+ memset(t11, 0, t10);
+ t12 = t11;
+ memset(t12, (unsigned char)2, t10);
+ t13 = (t5 - 1);
+ t14 = (0 - t13);
+ t15 = (t14 * -1);
+ t15 = (t15 + 1);
+ t15 = (t15 * 1U);
+ t17 = (t5 - 1);
+ t18 = (t16 + 0U);
+ t19 = (t18 + 0U);
+ *((int *)t19) = t17;
+ t19 = (t18 + 4U);
+ *((int *)t19) = 0;
+ t19 = (t18 + 8U);
+ *((int *)t19) = -1;
+ t20 = (0 - t17);
+ t21 = (t20 * -1);
+ t21 = (t21 + 1);
+ t19 = (t18 + 12U);
+ *((unsigned int *)t19) = t21;
+ t19 = (t6 + 4U);
+ t22 = ((IEEE_P_2592010699) + 4024);
+ t23 = (t19 + 88U);
+ *((char **)t23) = t22;
+ t24 = (char *)alloca(t15);
+ t25 = (t19 + 56U);
+ *((char **)t25) = t24;
+ memcpy(t24, t11, t15);
+ t26 = (t19 + 64U);
+ *((char **)t26) = t16;
+ t27 = (t19 + 80U);
+ *((unsigned int *)t27) = t15;
+ t29 = (t28 + 0U);
+ t30 = (t29 + 0U);
+ *((int *)t30) = 3;
+ t30 = (t29 + 4U);
+ *((int *)t30) = 0;
+ t30 = (t29 + 8U);
+ *((int *)t30) = -1;
+ t31 = (0 - 3);
+ t21 = (t31 * -1);
+ t21 = (t21 + 1);
+ t30 = (t29 + 12U);
+ *((unsigned int *)t30) = t21;
+ t30 = (t6 + 124U);
+ t32 = ((IEEE_P_2592010699) + 4024);
+ t33 = (t30 + 88U);
+ *((char **)t33) = t32;
+ t35 = (t30 + 56U);
+ *((char **)t35) = t34;
+ xsi_type_set_default_value(t32, t34, t28);
+ t36 = (t30 + 64U);
+ *((char **)t36) = t28;
+ t37 = (t30 + 80U);
+ *((unsigned int *)t37) = 4U;
+ t38 = (t6 + 244U);
+ t39 = ((STD_STANDARD) + 384);
+ t40 = (t38 + 88U);
+ *((char **)t40) = t39;
+ t42 = (t38 + 56U);
+ *((char **)t42) = t41;
+ *((int *)t41) = 0;
+ t43 = (t38 + 80U);
+ *((unsigned int *)t43) = 4U;
+ t44 = (t7 + 4U);
+ t45 = (t3 != 0);
+ if (t45 == 1)
+ goto LAB3;
+
+LAB2: t46 = (t7 + 12U);
+ *((char **)t46) = t4;
+ t47 = (t7 + 20U);
+ *((int *)t47) = t5;
+ t48 = (t4 + 8U);
+ t49 = *((int *)t48);
+ t50 = (t49 * -1);
+ t51 = (t4 + 0U);
+ t52 = *((int *)t51);
+ t53 = (t4 + 4U);
+ t54 = *((int *)t53);
+ t55 = t54;
+ t56 = t52;
+
+LAB4: t57 = (t56 * t50);
+ t58 = (t55 * t50);
+ if (t58 <= t57)
+ goto LAB5;
+
+LAB7: t11 = (t19 + 56U);
+ t12 = *((char **)t11);
+ t11 = (t16 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t0 = xsi_get_transient_memory(t10);
+ memcpy(t0, t12, t10);
+ t18 = (t16 + 0U);
+ t8 = *((int *)t18);
+ t22 = (t16 + 4U);
+ t9 = *((int *)t22);
+ t23 = (t16 + 8U);
+ t13 = *((int *)t23);
+ t25 = (t2 + 0U);
+ t26 = (t25 + 0U);
+ *((int *)t26) = t8;
+ t26 = (t25 + 4U);
+ *((int *)t26) = t9;
+ t26 = (t25 + 8U);
+ *((int *)t26) = t13;
+ t14 = (t9 - t8);
+ t15 = (t14 * t13);
+ t15 = (t15 + 1);
+ t26 = (t25 + 12U);
+ *((unsigned int *)t26) = t15;
+
+LAB1: return t0;
+LAB3: *((char **)t44) = *((char **)t3);
+ goto LAB2;
+
+LAB5: t59 = (t4 + 0U);
+ t60 = *((int *)t59);
+ t61 = (t4 + 8U);
+ t62 = *((int *)t61);
+ t63 = (t55 - t60);
+ t21 = (t63 * t62);
+ t64 = (1U * t21);
+ t65 = (0 + t64);
+ t66 = (t3 + t65);
+ t67 = *((unsigned char *)t66);
+ t68 = (char *)((nl0) + t67);
+ goto **((char **)t68);
+
+LAB6: if (t55 == t56)
+ goto LAB7;
+
+LAB45: t8 = (t55 + t50);
+ t55 = t8;
+ goto LAB4;
+
+LAB8: t8 = 0;
+ t9 = 3;
+
+LAB37: if (t8 <= t9)
+ goto LAB38;
+
+LAB40: t11 = (t38 + 56U);
+ t12 = *((char **)t11);
+ t8 = *((int *)t12);
+ t9 = (t8 + 1);
+ t11 = (t38 + 56U);
+ t18 = *((char **)t11);
+ t11 = (t18 + 0);
+ *((int *)t11) = t9;
+ goto LAB6;
+
+LAB9: t69 = (t28 + 12U);
+ t70 = *((unsigned int *)t69);
+ t70 = (t70 * 1U);
+ t71 = xsi_get_transient_memory(t70);
+ memset(t71, 0, t70);
+ t72 = t71;
+ memset(t72, (unsigned char)2, t70);
+ t73 = (t30 + 56U);
+ t74 = *((char **)t73);
+ t73 = (t74 + 0);
+ t75 = (t28 + 12U);
+ t76 = *((unsigned int *)t75);
+ t76 = (t76 * 1U);
+ memcpy(t73, t71, t76);
+ goto LAB8;
+
+LAB10: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB11: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (1 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB12: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t14 = (1 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)3;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB13: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (2 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB14: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t14 = (2 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)3;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB15: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (1 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t14 = (2 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)3;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB16: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (3 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB17: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (3 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB18: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t14 = (3 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)3;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB19: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t14 = (2 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)2;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB20: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t14 = (2 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)2;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB21: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (2 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB22: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (2 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB23: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t14 = (1 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)2;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB24: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t14 = (1 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)2;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB25: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (1 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB26: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (1 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB27: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB28: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB29: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t30 + 56U);
+ t23 = *((char **)t22);
+ t22 = (t23 + 0);
+ t25 = (t28 + 12U);
+ t15 = *((unsigned int *)t25);
+ t15 = (t15 * 1U);
+ memcpy(t22, t12, t15);
+ goto LAB8;
+
+LAB30: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t30 + 56U);
+ t23 = *((char **)t22);
+ t22 = (t23 + 0);
+ t25 = (t28 + 12U);
+ t15 = *((unsigned int *)t25);
+ t15 = (t15 * 1U);
+ memcpy(t22, t12, t15);
+ goto LAB8;
+
+LAB31: t8 = 0;
+ t9 = 3;
+
+LAB32: if (t8 <= t9)
+ goto LAB33;
+
+LAB35: goto LAB8;
+
+LAB33: t11 = (t30 + 56U);
+ t12 = *((char **)t11);
+ t11 = (t28 + 0U);
+ t13 = *((int *)t11);
+ t18 = (t28 + 8U);
+ t14 = *((int *)t18);
+ t17 = (t8 - t13);
+ t10 = (t17 * t14);
+ t22 = (t28 + 4U);
+ t20 = *((int *)t22);
+ xsi_vhdl_check_range_of_index(t13, t20, t14, t8);
+ t15 = (1U * t10);
+ t21 = (0 + t15);
+ t23 = (t12 + t21);
+ *((unsigned char *)t23) = (unsigned char)1;
+
+LAB34: if (t8 == t9)
+ goto LAB35;
+
+LAB36: t13 = (t8 + 1);
+ t8 = t13;
+ goto LAB32;
+
+LAB38: t11 = (t38 + 56U);
+ t12 = *((char **)t11);
+ t13 = *((int *)t12);
+ t14 = (t13 * 4);
+ t17 = (t14 + t8);
+ t45 = (t17 < t5);
+ if (t45 != 0)
+ goto LAB41;
+
+LAB43:
+LAB42:
+LAB39: if (t8 == t9)
+ goto LAB40;
+
+LAB44: t13 = (t8 + 1);
+ t8 = t13;
+ goto LAB37;
+
+LAB41: t11 = (t30 + 56U);
+ t18 = *((char **)t11);
+ t11 = (t28 + 0U);
+ t20 = *((int *)t11);
+ t22 = (t28 + 8U);
+ t31 = *((int *)t22);
+ t49 = (t8 - t20);
+ t10 = (t49 * t31);
+ t23 = (t28 + 4U);
+ t52 = *((int *)t23);
+ xsi_vhdl_check_range_of_index(t20, t52, t31, t8);
+ t15 = (1U * t10);
+ t21 = (0 + t15);
+ t25 = (t18 + t21);
+ t67 = *((unsigned char *)t25);
+ t26 = (t19 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t38 + 56U);
+ t29 = *((char **)t26);
+ t54 = *((int *)t29);
+ t57 = (t54 * 4);
+ t58 = (t57 + t8);
+ t26 = (t16 + 0U);
+ t60 = *((int *)t26);
+ t32 = (t16 + 8U);
+ t62 = *((int *)t32);
+ t63 = (t58 - t60);
+ t64 = (t63 * t62);
+ t33 = (t16 + 4U);
+ t77 = *((int *)t33);
+ xsi_vhdl_check_range_of_index(t60, t77, t62, t58);
+ t65 = (1U * t64);
+ t70 = (0 + t65);
+ t35 = (t27 + t70);
+ *((unsigned char *)t35) = t67;
+ goto LAB42;
+
+LAB46:;
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_0(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+
+LAB0:
+LAB3: t1 = (t0 + 14656);
+ t2 = (t1 + 56U);
+ t3 = *((char **)t2);
+ t4 = (t3 + 56U);
+ t5 = *((char **)t4);
+ *((unsigned char *)t5) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2:
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_1(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+
+LAB0:
+LAB3: t1 = (t0 + 14720);
+ t2 = (t1 + 56U);
+ t3 = *((char **)t2);
+ t4 = (t3 + 56U);
+ t5 = *((char **)t4);
+ *((unsigned char *)t5) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2:
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_2(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ unsigned char t5;
+ unsigned char t6;
+ char *t7;
+ unsigned char t8;
+ unsigned char t9;
+ unsigned char t10;
+ char *t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+
+LAB0:
+LAB3: t1 = (t0 + 5288U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 5448U);
+ t4 = *((char **)t1);
+ t5 = *((unsigned char *)t4);
+ t6 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t5);
+ t1 = (t0 + 2568U);
+ t7 = *((char **)t1);
+ t8 = *((unsigned char *)t7);
+ t9 = ieee_p_2592010699_sub_2545490612_2592010699(IEEE_P_2592010699, t6, t8);
+ t10 = ieee_p_2592010699_sub_1605435078_2592010699(IEEE_P_2592010699, t3, t9);
+ t1 = (t0 + 14784);
+ t11 = (t1 + 56U);
+ t12 = *((char **)t11);
+ t13 = (t12 + 56U);
+ t14 = *((char **)t13);
+ *((unsigned char *)t14) = t10;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t15 = (t0 + 14304);
+ *((int *)t15) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_3(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ unsigned char t4;
+ char *t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ unsigned char t9;
+ unsigned char t10;
+ unsigned char t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+ char *t16;
+
+LAB0:
+LAB3: t1 = (t0 + 5288U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t3);
+ t1 = (t0 + 5128U);
+ t5 = *((char **)t1);
+ t6 = *((unsigned char *)t5);
+ t7 = ieee_p_2592010699_sub_2545490612_2592010699(IEEE_P_2592010699, t4, t6);
+ t1 = (t0 + 2728U);
+ t8 = *((char **)t1);
+ t9 = *((unsigned char *)t8);
+ t10 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t9);
+ t11 = ieee_p_2592010699_sub_1605435078_2592010699(IEEE_P_2592010699, t7, t10);
+ t1 = (t0 + 14848);
+ t12 = (t1 + 56U);
+ t13 = *((char **)t12);
+ t14 = (t13 + 56U);
+ t15 = *((char **)t14);
+ *((unsigned char *)t15) = t11;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t16 = (t0 + 14320);
+ *((int *)t16) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_4(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 5128U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 14912);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t8 = (t0 + 14336);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_5(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ unsigned char t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ unsigned char t9;
+ unsigned char t10;
+ char *t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+
+LAB0:
+LAB3: t1 = (t0 + 2568U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 2728U);
+ t4 = *((char **)t1);
+ t5 = *((unsigned char *)t4);
+ t6 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t5);
+ t7 = ieee_p_2592010699_sub_1605435078_2592010699(IEEE_P_2592010699, t3, t6);
+ t1 = (t0 + 4968U);
+ t8 = *((char **)t1);
+ t9 = *((unsigned char *)t8);
+ t10 = ieee_p_2592010699_sub_2545490612_2592010699(IEEE_P_2592010699, t7, t9);
+ t1 = (t0 + 14976);
+ t11 = (t1 + 56U);
+ t12 = *((char **)t11);
+ t13 = (t12 + 56U);
+ t14 = *((char **)t13);
+ *((unsigned char *)t14) = t10;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t15 = (t0 + 14352);
+ *((int *)t15) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_6(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ unsigned char t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ unsigned char t10;
+ unsigned char t11;
+ unsigned char t12;
+ unsigned char t13;
+ char *t14;
+ char *t15;
+
+LAB0: t1 = (t0 + 6728U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)3);
+ if (t4 != 0)
+ goto LAB2;
+
+LAB4: t1 = (t0 + 2048U);
+ t4 = xsi_signal_has_event(t1);
+ if (t4 == 1)
+ goto LAB7;
+
+LAB8: t3 = (unsigned char)0;
+
+LAB9: if (t3 != 0)
+ goto LAB5;
+
+LAB6:
+LAB3: t1 = (t0 + 14368);
+ *((int *)t1) = 1;
+
+LAB1: return;
+LAB2: t1 = (t0 + 15040);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15040);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+ goto LAB3;
+
+LAB5: t2 = (t0 + 6888U);
+ t6 = *((char **)t2);
+ t12 = *((unsigned char *)t6);
+ t13 = (t12 == (unsigned char)3);
+ if (t13 != 0)
+ goto LAB10;
+
+LAB12: t1 = (t0 + 5768U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)3);
+ if (t4 != 0)
+ goto LAB13;
+
+LAB15: t1 = (t0 + 5608U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)3);
+ if (t4 != 0)
+ goto LAB16;
+
+LAB18: t1 = (t0 + 5288U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 15040);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = t3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15040);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+
+LAB17:
+LAB14:
+LAB11: goto LAB3;
+
+LAB7: t2 = (t0 + 2088U);
+ t5 = *((char **)t2);
+ t10 = *((unsigned char *)t5);
+ t11 = (t10 == (unsigned char)3);
+ t3 = t11;
+ goto LAB9;
+
+LAB10: t2 = (t0 + 15040);
+ t7 = (t2 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t14 = *((char **)t9);
+ *((unsigned char *)t14) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t2, 0U, 1, 100LL);
+ t15 = (t0 + 15040);
+ xsi_driver_intertial_reject(t15, 100LL, 100LL);
+ goto LAB11;
+
+LAB13: t1 = (t0 + 15040);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15040);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+ goto LAB14;
+
+LAB16: t1 = (t0 + 15040);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15040);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+ goto LAB17;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_7(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ unsigned char t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ unsigned char t10;
+ unsigned char t11;
+ unsigned char t12;
+ unsigned char t13;
+ char *t14;
+ char *t15;
+
+LAB0: t1 = (t0 + 6728U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)3);
+ if (t4 != 0)
+ goto LAB2;
+
+LAB4: t1 = (t0 + 2048U);
+ t4 = xsi_signal_has_event(t1);
+ if (t4 == 1)
+ goto LAB7;
+
+LAB8: t3 = (unsigned char)0;
+
+LAB9: if (t3 != 0)
+ goto LAB5;
+
+LAB6:
+LAB3: t1 = (t0 + 14384);
+ *((int *)t1) = 1;
+
+LAB1: return;
+LAB2: t1 = (t0 + 15104);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15104);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+ goto LAB3;
+
+LAB5: t2 = (t0 + 6888U);
+ t6 = *((char **)t2);
+ t12 = *((unsigned char *)t6);
+ t13 = (t12 == (unsigned char)3);
+ if (t13 != 0)
+ goto LAB10;
+
+LAB12: t1 = (t0 + 5288U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 5448U);
+ t5 = *((char **)t1);
+ t4 = *((unsigned char *)t5);
+ t1 = (t0 + 2568U);
+ t6 = *((char **)t1);
+ t10 = *((unsigned char *)t6);
+ t11 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t10);
+ t12 = ieee_p_2592010699_sub_1605435078_2592010699(IEEE_P_2592010699, t4, t11);
+ t13 = ieee_p_2592010699_sub_2545490612_2592010699(IEEE_P_2592010699, t3, t12);
+ t1 = (t0 + 15104);
+ t7 = (t1 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t14 = *((char **)t9);
+ *((unsigned char *)t14) = t13;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t15 = (t0 + 15104);
+ xsi_driver_intertial_reject(t15, 100LL, 100LL);
+
+LAB11: goto LAB3;
+
+LAB7: t2 = (t0 + 2088U);
+ t5 = *((char **)t2);
+ t10 = *((unsigned char *)t5);
+ t11 = (t10 == (unsigned char)3);
+ t3 = t11;
+ goto LAB9;
+
+LAB10: t2 = (t0 + 15104);
+ t7 = (t2 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t14 = *((char **)t9);
+ *((unsigned char *)t14) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t2, 0U, 1, 100LL);
+ t15 = (t0 + 15104);
+ xsi_driver_intertial_reject(t15, 100LL, 100LL);
+ goto LAB11;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_8(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ unsigned char t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ unsigned char t10;
+ unsigned char t11;
+ unsigned char t12;
+ unsigned char t13;
+ char *t14;
+ char *t15;
+ unsigned char t16;
+ unsigned char t17;
+ unsigned char t18;
+ unsigned char t19;
+ char *t20;
+
+LAB0: t1 = (t0 + 6728U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)3);
+ if (t4 != 0)
+ goto LAB2;
+
+LAB4: t1 = (t0 + 2048U);
+ t4 = xsi_signal_has_event(t1);
+ if (t4 == 1)
+ goto LAB7;
+
+LAB8: t3 = (unsigned char)0;
+
+LAB9: if (t3 != 0)
+ goto LAB5;
+
+LAB6:
+LAB3: t1 = (t0 + 14400);
+ *((int *)t1) = 1;
+
+LAB1: return;
+LAB2: t1 = (t0 + 15168);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15168);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+ goto LAB3;
+
+LAB5: t2 = (t0 + 6888U);
+ t6 = *((char **)t2);
+ t12 = *((unsigned char *)t6);
+ t13 = (t12 == (unsigned char)3);
+ if (t13 != 0)
+ goto LAB10;
+
+LAB12: t1 = (t0 + 5288U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t3);
+ t1 = (t0 + 5448U);
+ t5 = *((char **)t1);
+ t10 = *((unsigned char *)t5);
+ t11 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t10);
+ t12 = ieee_p_2592010699_sub_1605435078_2592010699(IEEE_P_2592010699, t4, t11);
+ t1 = (t0 + 5288U);
+ t6 = *((char **)t1);
+ t13 = *((unsigned char *)t6);
+ t16 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t13);
+ t1 = (t0 + 2568U);
+ t7 = *((char **)t1);
+ t17 = *((unsigned char *)t7);
+ t18 = ieee_p_2592010699_sub_1605435078_2592010699(IEEE_P_2592010699, t16, t17);
+ t19 = ieee_p_2592010699_sub_2545490612_2592010699(IEEE_P_2592010699, t12, t18);
+ t1 = (t0 + 15168);
+ t8 = (t1 + 56U);
+ t9 = *((char **)t8);
+ t14 = (t9 + 56U);
+ t15 = *((char **)t14);
+ *((unsigned char *)t15) = t19;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t20 = (t0 + 15168);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+
+LAB11: goto LAB3;
+
+LAB7: t2 = (t0 + 2088U);
+ t5 = *((char **)t2);
+ t10 = *((unsigned char *)t5);
+ t11 = (t10 == (unsigned char)3);
+ t3 = t11;
+ goto LAB9;
+
+LAB10: t2 = (t0 + 15168);
+ t7 = (t2 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t14 = *((char **)t9);
+ *((unsigned char *)t14) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t2, 0U, 1, 100LL);
+ t15 = (t0 + 15168);
+ xsi_driver_intertial_reject(t15, 100LL, 100LL);
+ goto LAB11;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_9(char *t0)
+{
+ unsigned char t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ unsigned char t9;
+ unsigned char t10;
+ char *t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+
+LAB0: t2 = (t0 + 2048U);
+ t3 = xsi_signal_has_event(t2);
+ if (t3 == 1)
+ goto LAB5;
+
+LAB6: t1 = (unsigned char)0;
+
+LAB7: if (t1 != 0)
+ goto LAB2;
+
+LAB4:
+LAB3: t2 = (t0 + 14416);
+ *((int *)t2) = 1;
+
+LAB1: return;
+LAB2: t4 = (t0 + 6888U);
+ t8 = *((char **)t4);
+ t9 = *((unsigned char *)t8);
+ t10 = (t9 == (unsigned char)3);
+ if (t10 != 0)
+ goto LAB8;
+
+LAB10: t2 = (t0 + 5928U);
+ t4 = *((char **)t2);
+ t1 = *((unsigned char *)t4);
+ t2 = (t0 + 15232);
+ t5 = (t2 + 56U);
+ t8 = *((char **)t5);
+ t11 = (t8 + 56U);
+ t12 = *((char **)t11);
+ *((unsigned char *)t12) = t1;
+ xsi_driver_first_trans_delta(t2, 0U, 1, 100LL);
+ t13 = (t0 + 15232);
+ xsi_driver_intertial_reject(t13, 100LL, 100LL);
+
+LAB9: goto LAB3;
+
+LAB5: t4 = (t0 + 2088U);
+ t5 = *((char **)t4);
+ t6 = *((unsigned char *)t5);
+ t7 = (t6 == (unsigned char)3);
+ t1 = t7;
+ goto LAB7;
+
+LAB8: t4 = (t0 + 15232);
+ t11 = (t4 + 56U);
+ t12 = *((char **)t11);
+ t13 = (t12 + 56U);
+ t14 = *((char **)t13);
+ *((unsigned char *)t14) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t4, 0U, 1, 100LL);
+ t15 = (t0 + 15232);
+ xsi_driver_intertial_reject(t15, 100LL, 100LL);
+ goto LAB9;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_10(char *t0)
+{
+ unsigned char t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ unsigned char t9;
+ unsigned char t10;
+ char *t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+
+LAB0: t2 = (t0 + 2048U);
+ t3 = xsi_signal_has_event(t2);
+ if (t3 == 1)
+ goto LAB5;
+
+LAB6: t1 = (unsigned char)0;
+
+LAB7: if (t1 != 0)
+ goto LAB2;
+
+LAB4:
+LAB3: t2 = (t0 + 14432);
+ *((int *)t2) = 1;
+
+LAB1: return;
+LAB2: t4 = (t0 + 6888U);
+ t8 = *((char **)t4);
+ t9 = *((unsigned char *)t8);
+ t10 = (t9 == (unsigned char)3);
+ if (t10 != 0)
+ goto LAB8;
+
+LAB10: t2 = (t0 + 2568U);
+ t4 = *((char **)t2);
+ t1 = *((unsigned char *)t4);
+ t2 = (t0 + 15296);
+ t5 = (t2 + 56U);
+ t8 = *((char **)t5);
+ t11 = (t8 + 56U);
+ t12 = *((char **)t11);
+ *((unsigned char *)t12) = t1;
+ xsi_driver_first_trans_delta(t2, 0U, 1, 100LL);
+ t13 = (t0 + 15296);
+ xsi_driver_intertial_reject(t13, 100LL, 100LL);
+
+LAB9: goto LAB3;
+
+LAB5: t4 = (t0 + 2088U);
+ t5 = *((char **)t4);
+ t6 = *((unsigned char *)t5);
+ t7 = (t6 == (unsigned char)3);
+ t1 = t7;
+ goto LAB7;
+
+LAB8: t4 = (t0 + 15296);
+ t11 = (t4 + 56U);
+ t12 = *((char **)t11);
+ t13 = (t12 + 56U);
+ t14 = *((char **)t13);
+ *((unsigned char *)t14) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t4, 0U, 1, 100LL);
+ t15 = (t0 + 15296);
+ xsi_driver_intertial_reject(t15, 100LL, 100LL);
+ goto LAB9;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_11(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ unsigned char t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ unsigned char t10;
+ unsigned char t11;
+ unsigned char t12;
+ unsigned char t13;
+ char *t14;
+ char *t15;
+ unsigned char t16;
+ unsigned char t17;
+ unsigned char t18;
+ unsigned char t19;
+ unsigned char t20;
+ unsigned char t21;
+ char *t22;
+ char *t23;
+
+LAB0: t1 = (t0 + 6728U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)3);
+ if (t4 != 0)
+ goto LAB2;
+
+LAB4: t1 = (t0 + 2048U);
+ t4 = xsi_signal_has_event(t1);
+ if (t4 == 1)
+ goto LAB7;
+
+LAB8: t3 = (unsigned char)0;
+
+LAB9: if (t3 != 0)
+ goto LAB5;
+
+LAB6:
+LAB3: t1 = (t0 + 14448);
+ *((int *)t1) = 1;
+
+LAB1: return;
+LAB2: t1 = (t0 + 15360);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15360);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+ t1 = (t0 + 15424);
+ t2 = (t1 + 56U);
+ t5 = *((char **)t2);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t8 = (t0 + 15424);
+ xsi_driver_intertial_reject(t8, 100LL, 100LL);
+ goto LAB3;
+
+LAB5: t2 = (t0 + 6888U);
+ t6 = *((char **)t2);
+ t12 = *((unsigned char *)t6);
+ t13 = (t12 == (unsigned char)3);
+ if (t13 != 0)
+ goto LAB10;
+
+LAB12: t1 = (t0 + 5608U);
+ t2 = *((char **)t1);
+ t4 = *((unsigned char *)t2);
+ t10 = (t4 == (unsigned char)3);
+ if (t10 == 1)
+ goto LAB16;
+
+LAB17: t1 = (t0 + 2728U);
+ t5 = *((char **)t1);
+ t13 = *((unsigned char *)t5);
+ t16 = (t13 == (unsigned char)2);
+ if (t16 == 1)
+ goto LAB22;
+
+LAB23: t12 = (unsigned char)0;
+
+LAB24: if (t12 == 1)
+ goto LAB19;
+
+LAB20: t11 = (unsigned char)0;
+
+LAB21: t3 = t11;
+
+LAB18: if (t3 != 0)
+ goto LAB13;
+
+LAB15:
+LAB14: t1 = (t0 + 6408U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 15424);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = t3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15424);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+
+LAB11: goto LAB3;
+
+LAB7: t2 = (t0 + 2088U);
+ t5 = *((char **)t2);
+ t10 = *((unsigned char *)t5);
+ t11 = (t10 == (unsigned char)3);
+ t3 = t11;
+ goto LAB9;
+
+LAB10: t2 = (t0 + 15360);
+ t7 = (t2 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t14 = *((char **)t9);
+ *((unsigned char *)t14) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t2, 0U, 1, 100LL);
+ t15 = (t0 + 15360);
+ xsi_driver_intertial_reject(t15, 100LL, 100LL);
+ t1 = (t0 + 15424);
+ t2 = (t1 + 56U);
+ t5 = *((char **)t2);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t8 = (t0 + 15424);
+ xsi_driver_intertial_reject(t8, 100LL, 100LL);
+ goto LAB11;
+
+LAB13: t1 = (t0 + 2728U);
+ t8 = *((char **)t1);
+ t21 = *((unsigned char *)t8);
+ t1 = (t0 + 15360);
+ t9 = (t1 + 56U);
+ t14 = *((char **)t9);
+ t15 = (t14 + 56U);
+ t22 = *((char **)t15);
+ *((unsigned char *)t22) = t21;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t23 = (t0 + 15360);
+ xsi_driver_intertial_reject(t23, 100LL, 100LL);
+ goto LAB14;
+
+LAB16: t3 = (unsigned char)1;
+ goto LAB18;
+
+LAB19: t1 = (t0 + 2568U);
+ t7 = *((char **)t1);
+ t19 = *((unsigned char *)t7);
+ t20 = (t19 == (unsigned char)2);
+ t11 = t20;
+ goto LAB21;
+
+LAB22: t1 = (t0 + 5448U);
+ t6 = *((char **)t1);
+ t17 = *((unsigned char *)t6);
+ t18 = (t17 == (unsigned char)3);
+ t12 = t18;
+ goto LAB24;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_12(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 5928U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 15488);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 14464);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_13(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 6408U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 15552);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 14480);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_14(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 5768U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 15616);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 14496);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_15(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 5288U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 15680);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 14512);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_16(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 5448U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 15744);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 14528);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_17(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ unsigned char t5;
+ unsigned char t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+
+LAB0:
+LAB3: t1 = (t0 + 6088U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 6248U);
+ t4 = *((char **)t1);
+ t5 = *((unsigned char *)t4);
+ t6 = ieee_p_2592010699_sub_1605435078_2592010699(IEEE_P_2592010699, t3, t5);
+ t1 = (t0 + 15808);
+ t7 = (t1 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((unsigned char *)t10) = t6;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t11 = (t0 + 14544);
+ *((int *)t11) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_18(char *t0)
+{
+ char t10[16];
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ unsigned char t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t11;
+ char *t12;
+ char *t13;
+ unsigned char t14;
+ unsigned char t15;
+ unsigned char t16;
+ unsigned char t17;
+
+LAB0: t1 = (t0 + 6728U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)3);
+ if (t4 != 0)
+ goto LAB2;
+
+LAB4: t1 = (t0 + 2048U);
+ t4 = xsi_signal_has_event(t1);
+ if (t4 == 1)
+ goto LAB10;
+
+LAB11: t3 = (unsigned char)0;
+
+LAB12: if (t3 != 0)
+ goto LAB8;
+
+LAB9:
+LAB3: t1 = (t0 + 14560);
+ *((int *)t1) = 1;
+
+LAB1: return;
+LAB2: t1 = (t0 + 15872);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15872);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+ t1 = (t0 + 15936);
+ t2 = (t1 + 56U);
+ t5 = *((char **)t2);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t8 = (t0 + 15936);
+ xsi_driver_intertial_reject(t8, 100LL, 100LL);
+ t3 = (0 == 1);
+ if (t3 != 0)
+ goto LAB5;
+
+LAB7:
+LAB6: goto LAB3;
+
+LAB5: t1 = (t0 + 22492);
+ t5 = (t0 + 22340U);
+ t6 = xilinxcorelib_a_3173924170_3212880686_sub_3703097363_3212880686(t0, t10, t1, t5, 8);
+ t7 = (t0 + 16000);
+ t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ t11 = (t9 + 56U);
+ t12 = *((char **)t11);
+ memcpy(t12, t6, 8U);
+ xsi_driver_first_trans_delta(t7, 0U, 8U, 100LL);
+ t13 = (t0 + 16000);
+ xsi_driver_intertial_reject(t13, 100LL, 100LL);
+ goto LAB6;
+
+LAB8: t2 = (t0 + 6888U);
+ t6 = *((char **)t2);
+ t16 = *((unsigned char *)t6);
+ t17 = (t16 == (unsigned char)3);
+ if (t17 != 0)
+ goto LAB13;
+
+LAB15: t1 = (t0 + 5608U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t4 = (t3 == (unsigned char)3);
+ if (t4 != 0)
+ goto LAB19;
+
+LAB21:
+LAB20:
+LAB14: goto LAB3;
+
+LAB10: t2 = (t0 + 2088U);
+ t5 = *((char **)t2);
+ t14 = *((unsigned char *)t5);
+ t15 = (t14 == (unsigned char)3);
+ t3 = t15;
+ goto LAB12;
+
+LAB13: t2 = (t0 + 15872);
+ t7 = (t2 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t11 = *((char **)t9);
+ *((unsigned char *)t11) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t2, 0U, 1, 100LL);
+ t12 = (t0 + 15872);
+ xsi_driver_intertial_reject(t12, 100LL, 100LL);
+ t1 = (t0 + 15936);
+ t2 = (t1 + 56U);
+ t5 = *((char **)t2);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t8 = (t0 + 15936);
+ xsi_driver_intertial_reject(t8, 100LL, 100LL);
+ t3 = (0 == 1);
+ if (t3 != 0)
+ goto LAB16;
+
+LAB18:
+LAB17: goto LAB14;
+
+LAB16: t1 = (t0 + 22493);
+ t5 = (t0 + 22340U);
+ t6 = xilinxcorelib_a_3173924170_3212880686_sub_3703097363_3212880686(t0, t10, t1, t5, 8);
+ t7 = (t0 + 16000);
+ t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ t11 = (t9 + 56U);
+ t12 = *((char **)t11);
+ memcpy(t12, t6, 8U);
+ xsi_driver_first_trans_delta(t7, 0U, 8U, 100LL);
+ t13 = (t0 + 16000);
+ xsi_driver_intertial_reject(t13, 100LL, 100LL);
+ goto LAB17;
+
+LAB19: t1 = (t0 + 2888U);
+ t5 = *((char **)t1);
+ t1 = (t0 + 16000);
+ t6 = (t1 + 56U);
+ t7 = *((char **)t6);
+ t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ memcpy(t9, t5, 8U);
+ xsi_driver_first_trans_delta(t1, 0U, 8U, 100LL);
+ t11 = (t0 + 16000);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+ t1 = (t0 + 3048U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 15872);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = t3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15872);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+ t1 = (t0 + 3208U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 15936);
+ t5 = (t1 + 56U);
+ t6 = *((char **)t5);
+ t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ *((unsigned char *)t8) = t3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t9 = (t0 + 15936);
+ xsi_driver_intertial_reject(t9, 100LL, 100LL);
+ goto LAB20;
+
+}
+
+static void xilinxcorelib_a_3173924170_3212880686_p_19(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+
+LAB0:
+LAB3: t1 = (t0 + 4808U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 16064);
+ t3 = (t1 + 56U);
+ t4 = *((char **)t3);
+ t5 = (t4 + 56U);
+ t6 = *((char **)t5);
+ memcpy(t6, t2, 8U);
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t7 = (t0 + 14576);
+ *((int *)t7) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+
+extern void xilinxcorelib_a_3173924170_3212880686_init()
+{
+ static char *pe[] = {(void *)xilinxcorelib_a_3173924170_3212880686_p_0,(void *)xilinxcorelib_a_3173924170_3212880686_p_1,(void *)xilinxcorelib_a_3173924170_3212880686_p_2,(void *)xilinxcorelib_a_3173924170_3212880686_p_3,(void *)xilinxcorelib_a_3173924170_3212880686_p_4,(void *)xilinxcorelib_a_3173924170_3212880686_p_5,(void *)xilinxcorelib_a_3173924170_3212880686_p_6,(void *)xilinxcorelib_a_3173924170_3212880686_p_7,(void *)xilinxcorelib_a_3173924170_3212880686_p_8,(void *)xilinxcorelib_a_3173924170_3212880686_p_9,(void *)xilinxcorelib_a_3173924170_3212880686_p_10,(void *)xilinxcorelib_a_3173924170_3212880686_p_11,(void *)xilinxcorelib_a_3173924170_3212880686_p_12,(void *)xilinxcorelib_a_3173924170_3212880686_p_13,(void *)xilinxcorelib_a_3173924170_3212880686_p_14,(void *)xilinxcorelib_a_3173924170_3212880686_p_15,(void *)xilinxcorelib_a_3173924170_3212880686_p_16,(void *)xilinxcorelib_a_3173924170_3212880686_p_17,(void *)xilinxcorelib_a_3173924170_3212880686_p_18,(void *)xilinxcorelib_a_3173924170_3212880686_p_19};
+ static char *se[] = {(void *)xilinxcorelib_a_3173924170_3212880686_sub_3703097363_3212880686};
+ xsi_register_didat("xilinxcorelib_a_3173924170_3212880686", "isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.didat");
+ xsi_register_executes(pe);
+ xsi_register_subprogram_executes(se);
+}
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.didat b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.didat
new file mode 100755
index 0000000000000000000000000000000000000000..82cfa7a4dbc3d2bbd80ca40e974b041db1abc7c6
GIT binary patch
literal 13772
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literal 0
HcmV?d00001
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.nt64.obj b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_3173924170_3212880686.nt64.obj
new file mode 100755
index 0000000000000000000000000000000000000000..2143c7a3de2c0ac330e0ac4405ed67e54c72c2ee
GIT binary patch
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diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.c b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.c
new file mode 100755
index 0000000..fb896d3
--- /dev/null
+++ b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.c
@@ -0,0 +1,5654 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/***********************************************************************/
+
+/* This file is designed for use with ISim build 0x7dea747 */
+
+#define XSI_HIDE_SYMBOL_SPEC true
+#include "xsi.h"
+#include <memory.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+extern char *STD_STANDARD;
+static const char *ng1 = "Function int_2_std_logic ended without a return statement";
+extern char *IEEE_P_2592010699;
+static const char *ng3 = "Function get_lesser ended without a return statement";
+static const char *ng4 = "";
+extern char *IEEE_P_3499444699;
+extern char *IEEE_P_3620187407;
+
+unsigned char ieee_p_2592010699_sub_1690584930_2592010699(char *, unsigned char );
+char *ieee_p_3499444699_sub_2213602152_3499444699(char *, char *, int , int );
+int ieee_p_3620187407_sub_514432868_3620187407(char *, char *, char *);
+
+
+int xilinxcorelib_a_4048593843_3212880686_sub_1842417276_3212880686(char *t1, int t2, int t3, int t4)
+{
+ char t6[16];
+ int t0;
+ char *t7;
+ char *t8;
+ char *t9;
+ int t10;
+
+LAB0: t7 = (t6 + 4U);
+ *((int *)t7) = t2;
+ t8 = (t6 + 8U);
+ *((int *)t8) = t3;
+ t9 = (t6 + 12U);
+ *((int *)t9) = t4;
+ t10 = (t2 - 1);
+ t0 = t10;
+
+LAB1: return t0;
+LAB2:;
+}
+
+int xilinxcorelib_a_4048593843_3212880686_sub_1315575287_3212880686(char *t1, int t2, int t3)
+{
+ char t4[128];
+ char t5[16];
+ char t9[8];
+ int t0;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t10;
+ char *t11;
+ char *t12;
+ char *t13;
+ int t14;
+ char *t15;
+ char *t16;
+ unsigned char t17;
+ int t18;
+ int t19;
+
+LAB0: t6 = (t4 + 4U);
+ t7 = ((STD_STANDARD) + 384);
+ t8 = (t6 + 88U);
+ *((char **)t8) = t7;
+ t10 = (t6 + 56U);
+ *((char **)t10) = t9;
+ xsi_type_set_default_value(t7, t9, 0);
+ t11 = (t6 + 80U);
+ *((unsigned int *)t11) = 4U;
+ t12 = (t5 + 4U);
+ *((int *)t12) = t2;
+ t13 = (t5 + 8U);
+ *((int *)t13) = t3;
+ t14 = (t2 / t3);
+ t15 = (t6 + 56U);
+ t16 = *((char **)t15);
+ t15 = (t16 + 0);
+ *((int *)t15) = t14;
+ t14 = xsi_vhdl_mod(t2, t3);
+ t17 = (t14 != 0);
+ if (t17 != 0)
+ goto LAB2;
+
+LAB4:
+LAB3: t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ t14 = *((int *)t8);
+ t0 = t14;
+
+LAB1: return t0;
+LAB2: t7 = (t6 + 56U);
+ t8 = *((char **)t7);
+ t18 = *((int *)t8);
+ t19 = (t18 + 1);
+ t7 = (t6 + 56U);
+ t10 = *((char **)t7);
+ t7 = (t10 + 0);
+ *((int *)t7) = t19;
+ goto LAB3;
+
+LAB5:;
+}
+
+unsigned char xilinxcorelib_a_4048593843_3212880686_sub_2978940197_3212880686(char *t1, int t2)
+{
+ char t4[8];
+ unsigned char t0;
+ char *t5;
+ unsigned char t6;
+
+LAB0: t5 = (t4 + 4U);
+ *((int *)t5) = t2;
+ t6 = (t2 == 1);
+ if (t6 != 0)
+ goto LAB2;
+
+LAB4: t0 = (unsigned char)2;
+
+LAB1: return t0;
+LAB2: t0 = (unsigned char)3;
+ goto LAB1;
+
+LAB3: xsi_error(ng1);
+ t0 = 0;
+ goto LAB1;
+
+LAB5: goto LAB3;
+
+LAB6: goto LAB3;
+
+}
+
+int xilinxcorelib_a_4048593843_3212880686_sub_3672023036_3212880686(char *t1, unsigned char t2, int t3, int t4)
+{
+ char t5[128];
+ char t6[16];
+ char t10[8];
+ int t0;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+ unsigned char t16;
+ char *t17;
+ char *t18;
+ int t19;
+
+LAB0: t7 = (t5 + 4U);
+ t8 = ((STD_STANDARD) + 384);
+ t9 = (t7 + 88U);
+ *((char **)t9) = t8;
+ t11 = (t7 + 56U);
+ *((char **)t11) = t10;
+ *((int *)t10) = 0;
+ t12 = (t7 + 80U);
+ *((unsigned int *)t12) = 4U;
+ t13 = (t6 + 4U);
+ *((unsigned char *)t13) = t2;
+ t14 = (t6 + 5U);
+ *((int *)t14) = t3;
+ t15 = (t6 + 9U);
+ *((int *)t15) = t4;
+ t16 = (!(t2));
+ if (t16 != 0)
+ goto LAB2;
+
+LAB4: t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ t8 = (t9 + 0);
+ *((int *)t8) = t3;
+
+LAB3: t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ t19 = *((int *)t9);
+ t0 = t19;
+
+LAB1: return t0;
+LAB2: t17 = (t7 + 56U);
+ t18 = *((char **)t17);
+ t17 = (t18 + 0);
+ *((int *)t17) = t4;
+ goto LAB3;
+
+LAB5:;
+}
+
+char *xilinxcorelib_a_4048593843_3212880686_sub_3703097363_3212880686(char *t1, char *t2, char *t3, char *t4, int t5)
+{
+ char t6[368];
+ char t7[24];
+ char t16[16];
+ char t28[16];
+ char t34[8];
+ char t41[8];
+ char *t0;
+ int t8;
+ int t9;
+ unsigned int t10;
+ char *t11;
+ char *t12;
+ int t13;
+ int t14;
+ unsigned int t15;
+ int t17;
+ char *t18;
+ char *t19;
+ int t20;
+ unsigned int t21;
+ char *t22;
+ char *t23;
+ char *t24;
+ char *t25;
+ char *t26;
+ char *t27;
+ char *t29;
+ char *t30;
+ int t31;
+ char *t32;
+ char *t33;
+ char *t35;
+ char *t36;
+ char *t37;
+ char *t38;
+ char *t39;
+ char *t40;
+ char *t42;
+ char *t43;
+ char *t44;
+ unsigned char t45;
+ char *t46;
+ char *t47;
+ char *t48;
+ int t49;
+ int t50;
+ char *t51;
+ int t52;
+ char *t53;
+ int t54;
+ int t55;
+ int t56;
+ int t57;
+ int t58;
+ char *t59;
+ int t60;
+ char *t61;
+ int t62;
+ int t63;
+ unsigned int t64;
+ unsigned int t65;
+ char *t66;
+ unsigned char t67;
+ char *t68;
+ char *t69;
+ unsigned int t70;
+ char *t71;
+ char *t72;
+ char *t73;
+ char *t74;
+ char *t75;
+ unsigned int t76;
+ int t77;
+ static char *nl0[] = {&&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB9, &&LAB10, &&LAB11, &&LAB12, &&LAB13, &&LAB14, &&LAB15, &&LAB16, &&LAB17, &&LAB18, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB19, &&LAB21, &&LAB23, &&LAB25, &&LAB27, &&LAB29, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB20, &&LAB22, &&LAB24, &&LAB26, &&LAB28, &&LAB30, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31, &&LAB31};
+
+LAB0: t8 = (t5 - 1);
+ t9 = (0 - t8);
+ t10 = (t9 * -1);
+ t10 = (t10 + 1);
+ t10 = (t10 * 1U);
+ t11 = xsi_get_transient_memory(t10);
+ memset(t11, 0, t10);
+ t12 = t11;
+ memset(t12, (unsigned char)2, t10);
+ t13 = (t5 - 1);
+ t14 = (0 - t13);
+ t15 = (t14 * -1);
+ t15 = (t15 + 1);
+ t15 = (t15 * 1U);
+ t17 = (t5 - 1);
+ t18 = (t16 + 0U);
+ t19 = (t18 + 0U);
+ *((int *)t19) = t17;
+ t19 = (t18 + 4U);
+ *((int *)t19) = 0;
+ t19 = (t18 + 8U);
+ *((int *)t19) = -1;
+ t20 = (0 - t17);
+ t21 = (t20 * -1);
+ t21 = (t21 + 1);
+ t19 = (t18 + 12U);
+ *((unsigned int *)t19) = t21;
+ t19 = (t6 + 4U);
+ t22 = ((IEEE_P_2592010699) + 4024);
+ t23 = (t19 + 88U);
+ *((char **)t23) = t22;
+ t24 = (char *)alloca(t15);
+ t25 = (t19 + 56U);
+ *((char **)t25) = t24;
+ memcpy(t24, t11, t15);
+ t26 = (t19 + 64U);
+ *((char **)t26) = t16;
+ t27 = (t19 + 80U);
+ *((unsigned int *)t27) = t15;
+ t29 = (t28 + 0U);
+ t30 = (t29 + 0U);
+ *((int *)t30) = 3;
+ t30 = (t29 + 4U);
+ *((int *)t30) = 0;
+ t30 = (t29 + 8U);
+ *((int *)t30) = -1;
+ t31 = (0 - 3);
+ t21 = (t31 * -1);
+ t21 = (t21 + 1);
+ t30 = (t29 + 12U);
+ *((unsigned int *)t30) = t21;
+ t30 = (t6 + 124U);
+ t32 = ((IEEE_P_2592010699) + 4024);
+ t33 = (t30 + 88U);
+ *((char **)t33) = t32;
+ t35 = (t30 + 56U);
+ *((char **)t35) = t34;
+ xsi_type_set_default_value(t32, t34, t28);
+ t36 = (t30 + 64U);
+ *((char **)t36) = t28;
+ t37 = (t30 + 80U);
+ *((unsigned int *)t37) = 4U;
+ t38 = (t6 + 244U);
+ t39 = ((STD_STANDARD) + 384);
+ t40 = (t38 + 88U);
+ *((char **)t40) = t39;
+ t42 = (t38 + 56U);
+ *((char **)t42) = t41;
+ *((int *)t41) = 0;
+ t43 = (t38 + 80U);
+ *((unsigned int *)t43) = 4U;
+ t44 = (t7 + 4U);
+ t45 = (t3 != 0);
+ if (t45 == 1)
+ goto LAB3;
+
+LAB2: t46 = (t7 + 12U);
+ *((char **)t46) = t4;
+ t47 = (t7 + 20U);
+ *((int *)t47) = t5;
+ t48 = (t4 + 8U);
+ t49 = *((int *)t48);
+ t50 = (t49 * -1);
+ t51 = (t4 + 0U);
+ t52 = *((int *)t51);
+ t53 = (t4 + 4U);
+ t54 = *((int *)t53);
+ t55 = t54;
+ t56 = t52;
+
+LAB4: t57 = (t56 * t50);
+ t58 = (t55 * t50);
+ if (t58 <= t57)
+ goto LAB5;
+
+LAB7: t11 = (t19 + 56U);
+ t12 = *((char **)t11);
+ t11 = (t16 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t0 = xsi_get_transient_memory(t10);
+ memcpy(t0, t12, t10);
+ t18 = (t16 + 0U);
+ t8 = *((int *)t18);
+ t22 = (t16 + 4U);
+ t9 = *((int *)t22);
+ t23 = (t16 + 8U);
+ t13 = *((int *)t23);
+ t25 = (t2 + 0U);
+ t26 = (t25 + 0U);
+ *((int *)t26) = t8;
+ t26 = (t25 + 4U);
+ *((int *)t26) = t9;
+ t26 = (t25 + 8U);
+ *((int *)t26) = t13;
+ t14 = (t9 - t8);
+ t15 = (t14 * t13);
+ t15 = (t15 + 1);
+ t26 = (t25 + 12U);
+ *((unsigned int *)t26) = t15;
+
+LAB1: return t0;
+LAB3: *((char **)t44) = *((char **)t3);
+ goto LAB2;
+
+LAB5: t59 = (t4 + 0U);
+ t60 = *((int *)t59);
+ t61 = (t4 + 8U);
+ t62 = *((int *)t61);
+ t63 = (t55 - t60);
+ t21 = (t63 * t62);
+ t64 = (1U * t21);
+ t65 = (0 + t64);
+ t66 = (t3 + t65);
+ t67 = *((unsigned char *)t66);
+ t68 = (char *)((nl0) + t67);
+ goto **((char **)t68);
+
+LAB6: if (t55 == t56)
+ goto LAB7;
+
+LAB45: t8 = (t55 + t50);
+ t55 = t8;
+ goto LAB4;
+
+LAB8: t8 = 0;
+ t9 = 3;
+
+LAB37: if (t8 <= t9)
+ goto LAB38;
+
+LAB40: t11 = (t38 + 56U);
+ t12 = *((char **)t11);
+ t8 = *((int *)t12);
+ t9 = (t8 + 1);
+ t11 = (t38 + 56U);
+ t18 = *((char **)t11);
+ t11 = (t18 + 0);
+ *((int *)t11) = t9;
+ goto LAB6;
+
+LAB9: t69 = (t28 + 12U);
+ t70 = *((unsigned int *)t69);
+ t70 = (t70 * 1U);
+ t71 = xsi_get_transient_memory(t70);
+ memset(t71, 0, t70);
+ t72 = t71;
+ memset(t72, (unsigned char)2, t70);
+ t73 = (t30 + 56U);
+ t74 = *((char **)t73);
+ t73 = (t74 + 0);
+ t75 = (t28 + 12U);
+ t76 = *((unsigned int *)t75);
+ t76 = (t76 * 1U);
+ memcpy(t73, t71, t76);
+ goto LAB8;
+
+LAB10: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB11: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (1 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB12: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t14 = (1 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)3;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB13: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (2 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB14: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t14 = (2 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)3;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB15: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (1 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t14 = (2 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)3;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB16: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (3 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB17: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (3 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB18: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)2, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)3;
+ t14 = (3 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)3;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB19: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t14 = (2 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)2;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB20: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t14 = (2 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)2;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB21: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (2 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB22: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (2 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB23: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t14 = (1 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)2;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB24: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t14 = (1 - t8);
+ t64 = (t14 * t9);
+ t65 = (1U * t64);
+ t26 = (t18 + t65);
+ *((unsigned char *)t26) = (unsigned char)2;
+ t27 = (t30 + 56U);
+ t29 = *((char **)t27);
+ t27 = (t29 + 0);
+ t32 = (t28 + 12U);
+ t70 = *((unsigned int *)t32);
+ t70 = (t70 * 1U);
+ memcpy(t27, t12, t70);
+ goto LAB8;
+
+LAB25: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (1 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB26: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (1 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB27: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB28: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t28 + 0U);
+ t8 = *((int *)t22);
+ t23 = (t28 + 8U);
+ t9 = *((int *)t23);
+ t13 = (0 - t8);
+ t15 = (t13 * t9);
+ t21 = (1U * t15);
+ t25 = (t18 + t21);
+ *((unsigned char *)t25) = (unsigned char)2;
+ t26 = (t30 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t27 + 0);
+ t29 = (t28 + 12U);
+ t64 = *((unsigned int *)t29);
+ t64 = (t64 * 1U);
+ memcpy(t26, t12, t64);
+ goto LAB8;
+
+LAB29: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t30 + 56U);
+ t23 = *((char **)t22);
+ t22 = (t23 + 0);
+ t25 = (t28 + 12U);
+ t15 = *((unsigned int *)t25);
+ t15 = (t15 * 1U);
+ memcpy(t22, t12, t15);
+ goto LAB8;
+
+LAB30: t11 = (t28 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t12 = xsi_get_transient_memory(t10);
+ memset(t12, 0, t10);
+ t18 = t12;
+ memset(t18, (unsigned char)3, t10);
+ t22 = (t30 + 56U);
+ t23 = *((char **)t22);
+ t22 = (t23 + 0);
+ t25 = (t28 + 12U);
+ t15 = *((unsigned int *)t25);
+ t15 = (t15 * 1U);
+ memcpy(t22, t12, t15);
+ goto LAB8;
+
+LAB31: t8 = 0;
+ t9 = 3;
+
+LAB32: if (t8 <= t9)
+ goto LAB33;
+
+LAB35: goto LAB8;
+
+LAB33: t11 = (t30 + 56U);
+ t12 = *((char **)t11);
+ t11 = (t28 + 0U);
+ t13 = *((int *)t11);
+ t18 = (t28 + 8U);
+ t14 = *((int *)t18);
+ t17 = (t8 - t13);
+ t10 = (t17 * t14);
+ t22 = (t28 + 4U);
+ t20 = *((int *)t22);
+ xsi_vhdl_check_range_of_index(t13, t20, t14, t8);
+ t15 = (1U * t10);
+ t21 = (0 + t15);
+ t23 = (t12 + t21);
+ *((unsigned char *)t23) = (unsigned char)1;
+
+LAB34: if (t8 == t9)
+ goto LAB35;
+
+LAB36: t13 = (t8 + 1);
+ t8 = t13;
+ goto LAB32;
+
+LAB38: t11 = (t38 + 56U);
+ t12 = *((char **)t11);
+ t13 = *((int *)t12);
+ t14 = (t13 * 4);
+ t17 = (t14 + t8);
+ t45 = (t17 < t5);
+ if (t45 != 0)
+ goto LAB41;
+
+LAB43:
+LAB42:
+LAB39: if (t8 == t9)
+ goto LAB40;
+
+LAB44: t13 = (t8 + 1);
+ t8 = t13;
+ goto LAB37;
+
+LAB41: t11 = (t30 + 56U);
+ t18 = *((char **)t11);
+ t11 = (t28 + 0U);
+ t20 = *((int *)t11);
+ t22 = (t28 + 8U);
+ t31 = *((int *)t22);
+ t49 = (t8 - t20);
+ t10 = (t49 * t31);
+ t23 = (t28 + 4U);
+ t52 = *((int *)t23);
+ xsi_vhdl_check_range_of_index(t20, t52, t31, t8);
+ t15 = (1U * t10);
+ t21 = (0 + t15);
+ t25 = (t18 + t21);
+ t67 = *((unsigned char *)t25);
+ t26 = (t19 + 56U);
+ t27 = *((char **)t26);
+ t26 = (t38 + 56U);
+ t29 = *((char **)t26);
+ t54 = *((int *)t29);
+ t57 = (t54 * 4);
+ t58 = (t57 + t8);
+ t26 = (t16 + 0U);
+ t60 = *((int *)t26);
+ t32 = (t16 + 8U);
+ t62 = *((int *)t32);
+ t63 = (t58 - t60);
+ t64 = (t63 * t62);
+ t33 = (t16 + 4U);
+ t77 = *((int *)t33);
+ xsi_vhdl_check_range_of_index(t60, t77, t62, t58);
+ t65 = (1U * t64);
+ t70 = (0 + t65);
+ t35 = (t27 + t70);
+ *((unsigned char *)t35) = t67;
+ goto LAB42;
+
+LAB46:;
+}
+
+int xilinxcorelib_a_4048593843_3212880686_sub_2234054365_3212880686(char *t1, int t2, int t3)
+{
+ char t5[16];
+ int t0;
+ char *t6;
+ char *t7;
+ unsigned char t8;
+
+LAB0: t6 = (t5 + 4U);
+ *((int *)t6) = t2;
+ t7 = (t5 + 8U);
+ *((int *)t7) = t3;
+ t8 = (t2 < t3);
+ if (t8 != 0)
+ goto LAB2;
+
+LAB4: t0 = t3;
+
+LAB1: return t0;
+LAB2: t0 = t2;
+ goto LAB1;
+
+LAB3: xsi_error(ng3);
+ t0 = 0;
+ goto LAB1;
+
+LAB5: goto LAB3;
+
+LAB6: goto LAB3;
+
+}
+
+void xilinxcorelib_a_4048593843_3212880686_sub_1807611230_3212880686(char *t0, char *t1, char *t2, char *t3, char *t4)
+{
+ char t6[32];
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+
+LAB0: t7 = (t6 + 4U);
+ *((char **)t7) = t2;
+ t8 = (t6 + 12U);
+ *((char **)t8) = t3;
+ t9 = (t6 + 20U);
+ *((char **)t9) = t4;
+ xsi_access_variable_set_value(t2, 0);
+ xsi_access_variable_set_value(t3, 0);
+ t10 = (t4 + 0);
+ *((int *)t10) = 0;
+
+LAB1: return;
+}
+
+void xilinxcorelib_a_4048593843_3212880686_sub_2129810750_3212880686(char *t0, char *t1, char *t2, char *t3, char *t4, char *t5, char *t6, char *t7)
+{
+ char t8[272];
+ char t9[64];
+ char t10[16];
+ char t26[16];
+ char t32[8];
+ char t64[16];
+ char t66[16];
+ char t73[16];
+ char t75[16];
+ char *t11;
+ char *t12;
+ int t13;
+ unsigned int t14;
+ char *t15;
+ char *t16;
+ char *t17;
+ char *t18;
+ char *t19;
+ char *t20;
+ char *t21;
+ char *t22;
+ char *t23;
+ char *t24;
+ char *t25;
+ char *t27;
+ char *t28;
+ int t29;
+ char *t30;
+ char *t31;
+ char *t33;
+ char *t34;
+ char *t35;
+ char *t36;
+ char *t37;
+ char *t38;
+ unsigned char t39;
+ char *t40;
+ char *t41;
+ char *t42;
+ unsigned char t43;
+ char *t44;
+ unsigned char t45;
+ int t46;
+ int t47;
+ int t48;
+ int t49;
+ int t50;
+ unsigned int t51;
+ unsigned int t52;
+ int t53;
+ int t54;
+ int t55;
+ int t56;
+ int t57;
+ int t58;
+ int t59;
+ unsigned int t60;
+ unsigned int t61;
+ unsigned int t62;
+ unsigned char t63;
+ unsigned int t65;
+ unsigned int t67;
+ unsigned int t68;
+ unsigned int t69;
+ int t70;
+ char *t71;
+ char *t72;
+ char *t74;
+ int t76;
+ char *t77;
+ int t78;
+ char *t79;
+ int t80;
+ char *t81;
+ int t82;
+ int t83;
+ int t84;
+ char *t85;
+ int t86;
+ char *t87;
+ int t88;
+ char *t89;
+ int t90;
+ char *t91;
+ char *t92;
+ int t93;
+ char *t94;
+ char *t95;
+ char *t96;
+ int t97;
+ char *t98;
+ int t99;
+ char *t100;
+ int t101;
+ char *t102;
+ int t103;
+ int t104;
+ int t105;
+ char *t106;
+ int t107;
+ char *t108;
+ int t109;
+ char *t110;
+ int t111;
+ int t112;
+ unsigned int t113;
+ unsigned int t114;
+ unsigned int t115;
+
+LAB0: t11 = (t10 + 0U);
+ t12 = (t11 + 0U);
+ *((int *)t12) = 2;
+ t12 = (t11 + 4U);
+ *((int *)t12) = 0;
+ t12 = (t11 + 8U);
+ *((int *)t12) = -1;
+ t13 = (0 - 2);
+ t14 = (t13 * -1);
+ t14 = (t14 + 1);
+ t12 = (t11 + 12U);
+ *((unsigned int *)t12) = t14;
+ t12 = (t8 + 4U);
+ t15 = (t0 + 33256);
+ t16 = (t12 + 56U);
+ *((char **)t16) = t15;
+ t17 = (t12 + 40U);
+ *((char **)t17) = 0;
+ t18 = (t12 + 64U);
+ *((int *)t18) = 1;
+ t19 = (t12 + 48U);
+ *((char **)t19) = 0;
+ t20 = (t8 + 76U);
+ t21 = (t0 + 33256);
+ t22 = (t20 + 56U);
+ *((char **)t22) = t21;
+ t23 = (t20 + 40U);
+ *((char **)t23) = 0;
+ t24 = (t20 + 64U);
+ *((int *)t24) = 1;
+ t25 = (t20 + 48U);
+ *((char **)t25) = 0;
+ t27 = (t26 + 0U);
+ t28 = (t27 + 0U);
+ *((int *)t28) = 1;
+ t28 = (t27 + 4U);
+ *((int *)t28) = 0;
+ t28 = (t27 + 8U);
+ *((int *)t28) = -1;
+ t29 = (0 - 1);
+ t14 = (t29 * -1);
+ t14 = (t14 + 1);
+ t28 = (t27 + 12U);
+ *((unsigned int *)t28) = t14;
+ t28 = (t8 + 148U);
+ t30 = ((IEEE_P_2592010699) + 4024);
+ t31 = (t28 + 88U);
+ *((char **)t31) = t30;
+ t33 = (t28 + 56U);
+ *((char **)t33) = t32;
+ xsi_type_set_default_value(t30, t32, t26);
+ t34 = (t28 + 64U);
+ *((char **)t34) = t26;
+ t35 = (t28 + 80U);
+ *((unsigned int *)t35) = 2U;
+ t36 = (t9 + 4U);
+ *((char **)t36) = t2;
+ t37 = (t9 + 12U);
+ *((char **)t37) = t3;
+ t38 = (t9 + 20U);
+ t39 = (t4 != 0);
+ if (t39 == 1)
+ goto LAB3;
+
+LAB2: t40 = (t9 + 28U);
+ *((char **)t40) = t5;
+ t41 = (t9 + 36U);
+ *((char **)t41) = t6;
+ t42 = (t9 + 44U);
+ t43 = (t7 != 0);
+ if (t43 == 1)
+ goto LAB5;
+
+LAB4: t44 = (t9 + 52U);
+ *((char **)t44) = t10;
+ t45 = xsi_access_variable_is_null(t2);
+ if ((!(t45)) != 0)
+ goto LAB6;
+
+LAB8:
+LAB7: t11 = (t0 + 32744);
+ t15 = xsi_variable_create(ng4, t11, 0, 0, 0, 0);
+ xsi_access_variable_set_value(t20, t15);
+ t11 = xsi_access_variable_all(t20);
+ t15 = (t11 + 56U);
+ t16 = *((char **)t15);
+ t15 = (t16 + 16U);
+ xsi_access_variable_assign(t15, t12);
+ t39 = xsi_access_variable_is_null(t2);
+ if ((!(t39)) != 0)
+ goto LAB9;
+
+LAB11:
+LAB10: t11 = (t5 + 0U);
+ t29 = *((int *)t11);
+ t15 = (t5 + 4U);
+ t46 = *((int *)t15);
+ t16 = (t5 + 8U);
+ t47 = *((int *)t16);
+ if (t29 > t46)
+ goto LAB12;
+
+LAB13: if (t47 == -1)
+ goto LAB17;
+
+LAB18: t13 = t46;
+
+LAB14: t17 = (t5 + 0U);
+ t48 = *((int *)t17);
+ t18 = (t5 + 8U);
+ t49 = *((int *)t18);
+ t50 = (t13 - t48);
+ t14 = (t50 * t49);
+ t51 = (1U * t14);
+ t52 = (0 + t51);
+ t19 = (t4 + t52);
+ t39 = *((unsigned char *)t19);
+ t43 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t39);
+ t21 = (t5 + 0U);
+ t54 = *((int *)t21);
+ t22 = (t5 + 4U);
+ t55 = *((int *)t22);
+ t23 = (t5 + 8U);
+ t56 = *((int *)t23);
+ if (t54 > t55)
+ goto LAB19;
+
+LAB20: if (t56 == -1)
+ goto LAB24;
+
+LAB25: t53 = t54;
+
+LAB21: t24 = (t5 + 0U);
+ t57 = *((int *)t24);
+ t25 = (t5 + 8U);
+ t58 = *((int *)t25);
+ t59 = (t53 - t57);
+ t60 = (t59 * t58);
+ t61 = (1U * t60);
+ t62 = (0 + t61);
+ t27 = (t4 + t62);
+ t45 = *((unsigned char *)t27);
+ t63 = ieee_p_2592010699_sub_1690584930_2592010699(IEEE_P_2592010699, t45);
+ t31 = ((IEEE_P_2592010699) + 4024);
+ t30 = xsi_base_array_concat(t30, t64, t31, (char)99, t43, (char)99, t63, (char)101);
+ t33 = (t28 + 56U);
+ t34 = *((char **)t33);
+ t33 = (t34 + 0);
+ t65 = (1U + 1U);
+ memcpy(t33, t30, t65);
+ t11 = (t10 + 0U);
+ t13 = *((int *)t11);
+ t15 = (t10 + 8U);
+ t29 = *((int *)t15);
+ t46 = (1 - t13);
+ t14 = (t46 * t29);
+ t51 = (1U * t14);
+ t52 = (0 + t51);
+ t16 = (t7 + t52);
+ t39 = *((unsigned char *)t16);
+ t43 = (t39 == (unsigned char)2);
+ if (t43 != 0)
+ goto LAB26;
+
+LAB28: t11 = (t10 + 0U);
+ t13 = *((int *)t11);
+ t15 = (t10 + 8U);
+ t29 = *((int *)t15);
+ t46 = (2 - t13);
+ t14 = (t46 * t29);
+ t51 = (1U * t14);
+ t52 = (0 + t51);
+ t16 = (t7 + t52);
+ t39 = *((unsigned char *)t16);
+ t43 = (t39 == (unsigned char)3);
+ if (t43 != 0)
+ goto LAB29;
+
+LAB31: t11 = (t10 + 0U);
+ t13 = *((int *)t11);
+ t15 = (t10 + 8U);
+ t29 = *((int *)t15);
+ t46 = (1 - t13);
+ t14 = (t46 * t29);
+ t51 = (1U * t14);
+ t52 = (0 + t51);
+ t16 = (t7 + t52);
+ t39 = *((unsigned char *)t16);
+ t18 = ((IEEE_P_2592010699) + 4024);
+ t17 = xsi_base_array_concat(t17, t64, t18, (char)99, t39, (char)99, (unsigned char)2, (char)101);
+ t19 = (t28 + 56U);
+ t21 = *((char **)t19);
+ t22 = ((IEEE_P_2592010699) + 4024);
+ t19 = xsi_base_array_concat(t19, t66, t22, (char)97, t17, t64, (char)97, t21, t26, (char)101);
+ t23 = (t5 + 0U);
+ t47 = *((int *)t23);
+ t24 = (t5 + 0U);
+ t49 = *((int *)t24);
+ t25 = (t5 + 4U);
+ t50 = *((int *)t25);
+ t27 = (t5 + 8U);
+ t53 = *((int *)t27);
+ if (t49 > t50)
+ goto LAB32;
+
+LAB33: if (t53 == -1)
+ goto LAB37;
+
+LAB38: t48 = t50;
+
+LAB34: t54 = (t48 - 2);
+ t60 = (t47 - t54);
+ t30 = (t5 + 0U);
+ t56 = *((int *)t30);
+ t31 = (t5 + 4U);
+ t57 = *((int *)t31);
+ t33 = (t5 + 8U);
+ t58 = *((int *)t33);
+ if (t56 > t57)
+ goto LAB39;
+
+LAB40: if (t58 == -1)
+ goto LAB44;
+
+LAB45: t55 = t56;
+
+LAB41: t34 = (t5 + 4U);
+ t59 = *((int *)t34);
+ t35 = (t5 + 8U);
+ t70 = *((int *)t35);
+ xsi_vhdl_check_range_of_slice(t47, t59, t70, t54, t55, -1);
+ t61 = (t60 * 1U);
+ t62 = (0 + t61);
+ t71 = (t4 + t62);
+ t74 = ((IEEE_P_2592010699) + 4024);
+ t77 = (t5 + 0U);
+ t78 = *((int *)t77);
+ t79 = (t5 + 4U);
+ t80 = *((int *)t79);
+ t81 = (t5 + 8U);
+ t82 = *((int *)t81);
+ if (t78 > t80)
+ goto LAB46;
+
+LAB47: if (t82 == -1)
+ goto LAB51;
+
+LAB52: t76 = t80;
+
+LAB48: t83 = (t76 - 2);
+ t85 = (t5 + 0U);
+ t86 = *((int *)t85);
+ t87 = (t5 + 4U);
+ t88 = *((int *)t87);
+ t89 = (t5 + 8U);
+ t90 = *((int *)t89);
+ if (t86 > t88)
+ goto LAB53;
+
+LAB54: if (t90 == -1)
+ goto LAB58;
+
+LAB59: t84 = t86;
+
+LAB55: t91 = (t75 + 0U);
+ t92 = (t91 + 0U);
+ *((int *)t92) = t83;
+ t92 = (t91 + 4U);
+ *((int *)t92) = t84;
+ t92 = (t91 + 8U);
+ *((int *)t92) = -1;
+ t93 = (t84 - t83);
+ t65 = (t93 * -1);
+ t65 = (t65 + 1);
+ t92 = (t91 + 12U);
+ *((unsigned int *)t92) = t65;
+ t72 = xsi_base_array_concat(t72, t73, t74, (char)97, t19, t66, (char)97, t71, t75, (char)101);
+ t92 = xsi_access_variable_all(t20);
+ t94 = (t92 + 56U);
+ t95 = *((char **)t94);
+ t65 = (0 + 0U);
+ t94 = (t95 + t65);
+ t67 = (1U + 1U);
+ t96 = (t26 + 12U);
+ t68 = *((unsigned int *)t96);
+ t68 = (t68 * 1U);
+ t69 = (t67 + t68);
+ t98 = (t5 + 0U);
+ t99 = *((int *)t98);
+ t100 = (t5 + 4U);
+ t101 = *((int *)t100);
+ t102 = (t5 + 8U);
+ t103 = *((int *)t102);
+ if (t99 > t101)
+ goto LAB60;
+
+LAB61: if (t103 == -1)
+ goto LAB65;
+
+LAB66: t97 = t101;
+
+LAB62: t104 = (t97 - 2);
+ t106 = (t5 + 0U);
+ t107 = *((int *)t106);
+ t108 = (t5 + 4U);
+ t109 = *((int *)t108);
+ t110 = (t5 + 8U);
+ t111 = *((int *)t110);
+ if (t107 > t109)
+ goto LAB67;
+
+LAB68: if (t111 == -1)
+ goto LAB72;
+
+LAB73: t105 = t107;
+
+LAB69: t112 = (t105 - t104);
+ t113 = (t112 * -1);
+ t113 = (t113 + 1);
+ t114 = (1U * t113);
+ t115 = (t69 + t114);
+ memcpy(t94, t72, t115);
+
+LAB30:
+LAB27: t13 = *((int *)t6);
+ t29 = (t13 + 1);
+ t11 = (t6 + 0);
+ *((int *)t11) = t29;
+ t11 = xsi_access_variable_all(t20);
+ t15 = (t11 + 56U);
+ t16 = *((char **)t15);
+ t15 = (t16 + 16U);
+ t39 = xsi_access_variable_is_null(t15);
+ if (t39 != 0)
+ goto LAB74;
+
+LAB76:
+LAB75: xsi_access_variable_assign(t2, t20);
+
+LAB1: xsi_access_variable_delete(t20);
+ xsi_access_variable_delete(t12);
+ return;
+LAB3: *((char **)t38) = *((char **)t4);
+ goto LAB2;
+
+LAB5: *((char **)t42) = *((char **)t7);
+ goto LAB4;
+
+LAB6: xsi_access_variable_assign(t12, t2);
+ goto LAB7;
+
+LAB9: t11 = xsi_access_variable_all(t12);
+ t15 = (t11 + 56U);
+ t16 = *((char **)t15);
+ t15 = (t16 + 88U);
+ xsi_access_variable_assign(t15, t20);
+ goto LAB10;
+
+LAB12: if (t47 == 1)
+ goto LAB15;
+
+LAB16: t13 = t29;
+ goto LAB14;
+
+LAB15: t13 = t46;
+ goto LAB14;
+
+LAB17: t13 = t29;
+ goto LAB14;
+
+LAB19: if (t56 == 1)
+ goto LAB22;
+
+LAB23: t53 = t55;
+ goto LAB21;
+
+LAB22: t53 = t54;
+ goto LAB21;
+
+LAB24: t53 = t55;
+ goto LAB21;
+
+LAB26: t17 = (t10 + 0U);
+ t47 = *((int *)t17);
+ t18 = (t10 + 8U);
+ t48 = *((int *)t18);
+ t49 = (0 - t47);
+ t60 = (t49 * t48);
+ t61 = (1U * t60);
+ t62 = (0 + t61);
+ t19 = (t7 + t62);
+ t45 = *((unsigned char *)t19);
+ t22 = ((IEEE_P_2592010699) + 4024);
+ t21 = xsi_base_array_concat(t21, t64, t22, (char)99, (unsigned char)2, (char)99, t45, (char)101);
+ t24 = ((IEEE_P_2592010699) + 4024);
+ t23 = xsi_base_array_concat(t23, t66, t24, (char)97, t21, t64, (char)97, t4, t5, (char)101);
+ t25 = xsi_access_variable_all(t20);
+ t27 = (t25 + 56U);
+ t30 = *((char **)t27);
+ t65 = (0 + 0U);
+ t27 = (t30 + t65);
+ t67 = (1U + 1U);
+ t31 = (t5 + 12U);
+ t68 = *((unsigned int *)t31);
+ t68 = (t68 * 1U);
+ t69 = (t67 + t68);
+ memcpy(t27, t23, t69);
+ goto LAB27;
+
+LAB29: t17 = (t10 + 0U);
+ t47 = *((int *)t17);
+ t18 = (t10 + 8U);
+ t48 = *((int *)t18);
+ t49 = (1 - t47);
+ t60 = (t49 * t48);
+ t61 = (1U * t60);
+ t62 = (0 + t61);
+ t19 = (t7 + t62);
+ t45 = *((unsigned char *)t19);
+ t22 = ((IEEE_P_2592010699) + 4024);
+ t21 = xsi_base_array_concat(t21, t64, t22, (char)99, t45, (char)99, (unsigned char)2, (char)101);
+ t23 = (t28 + 56U);
+ t24 = *((char **)t23);
+ t25 = ((IEEE_P_2592010699) + 4024);
+ t23 = xsi_base_array_concat(t23, t66, t25, (char)97, t21, t64, (char)97, t24, t26, (char)101);
+ t27 = xsi_access_variable_all(t20);
+ t30 = (t27 + 56U);
+ t31 = *((char **)t30);
+ t65 = (0 + 0U);
+ t30 = (t31 + t65);
+ t67 = (1U + 1U);
+ t33 = (t26 + 12U);
+ t68 = *((unsigned int *)t33);
+ t68 = (t68 * 1U);
+ t69 = (t67 + t68);
+ memcpy(t30, t23, t69);
+ goto LAB30;
+
+LAB32: if (t53 == 1)
+ goto LAB35;
+
+LAB36: t48 = t49;
+ goto LAB34;
+
+LAB35: t48 = t50;
+ goto LAB34;
+
+LAB37: t48 = t49;
+ goto LAB34;
+
+LAB39: if (t58 == 1)
+ goto LAB42;
+
+LAB43: t55 = t57;
+ goto LAB41;
+
+LAB42: t55 = t56;
+ goto LAB41;
+
+LAB44: t55 = t57;
+ goto LAB41;
+
+LAB46: if (t82 == 1)
+ goto LAB49;
+
+LAB50: t76 = t78;
+ goto LAB48;
+
+LAB49: t76 = t80;
+ goto LAB48;
+
+LAB51: t76 = t78;
+ goto LAB48;
+
+LAB53: if (t90 == 1)
+ goto LAB56;
+
+LAB57: t84 = t88;
+ goto LAB55;
+
+LAB56: t84 = t86;
+ goto LAB55;
+
+LAB58: t84 = t88;
+ goto LAB55;
+
+LAB60: if (t103 == 1)
+ goto LAB63;
+
+LAB64: t97 = t99;
+ goto LAB62;
+
+LAB63: t97 = t101;
+ goto LAB62;
+
+LAB65: t97 = t99;
+ goto LAB62;
+
+LAB67: if (t111 == 1)
+ goto LAB70;
+
+LAB71: t105 = t109;
+ goto LAB69;
+
+LAB70: t105 = t107;
+ goto LAB69;
+
+LAB72: t105 = t109;
+ goto LAB69;
+
+LAB74: xsi_access_variable_assign(t3, t20);
+ goto LAB75;
+
+}
+
+void xilinxcorelib_a_4048593843_3212880686_sub_2966016925_3212880686(char *t0, char *t1, char *t2, char *t3, char *t4, char *t5)
+{
+ char t6[128];
+ char t7[48];
+ char t8[16];
+ char t24[16];
+ char *t9;
+ char *t10;
+ int t11;
+ unsigned int t12;
+ char *t13;
+ int t14;
+ int t15;
+ int t16;
+ char *t17;
+ char *t18;
+ char *t19;
+ int t20;
+ int t21;
+ int t22;
+ unsigned int t23;
+ char *t25;
+ int t26;
+ int t27;
+ char *t28;
+ int t29;
+ unsigned int t30;
+ char *t31;
+ char *t32;
+ char *t33;
+ char *t34;
+ char *t35;
+ char *t36;
+ char *t37;
+ char *t38;
+ char *t39;
+ char *t40;
+ char *t41;
+ char *t42;
+ char *t43;
+ char *t44;
+ char *t45;
+ char *t46;
+ char *t47;
+ char *t48;
+ int t49;
+ int t50;
+ int t51;
+ unsigned int t52;
+ unsigned int t53;
+ int t54;
+
+LAB0: t9 = (t8 + 0U);
+ t10 = (t9 + 0U);
+ *((int *)t10) = 1;
+ t10 = (t9 + 4U);
+ *((int *)t10) = 0;
+ t10 = (t9 + 8U);
+ *((int *)t10) = -1;
+ t11 = (0 - 1);
+ t12 = (t11 * -1);
+ t12 = (t12 + 1);
+ t10 = (t9 + 12U);
+ *((unsigned int *)t10) = t12;
+ t10 = (t0 + 20224U);
+ t13 = *((char **)t10);
+ t14 = *((int *)t13);
+ t15 = (t14 + 1);
+ t16 = (0 - t15);
+ t12 = (t16 * -1);
+ t12 = (t12 + 1);
+ t12 = (t12 * 1U);
+ t10 = xsi_get_transient_memory(t12);
+ memset(t10, 0, t12);
+ t17 = t10;
+ memset(t17, (unsigned char)2, t12);
+ t18 = (t0 + 20224U);
+ t19 = *((char **)t18);
+ t20 = *((int *)t19);
+ t21 = (t20 + 1);
+ t22 = (0 - t21);
+ t23 = (t22 * -1);
+ t23 = (t23 + 1);
+ t23 = (t23 * 1U);
+ t18 = (t0 + 20224U);
+ t25 = *((char **)t18);
+ t26 = *((int *)t25);
+ t27 = (t26 + 1);
+ t18 = (t24 + 0U);
+ t28 = (t18 + 0U);
+ *((int *)t28) = t27;
+ t28 = (t18 + 4U);
+ *((int *)t28) = 0;
+ t28 = (t18 + 8U);
+ *((int *)t28) = -1;
+ t29 = (0 - t27);
+ t30 = (t29 * -1);
+ t30 = (t30 + 1);
+ t28 = (t18 + 12U);
+ *((unsigned int *)t28) = t30;
+ t28 = (t6 + 4U);
+ t31 = ((IEEE_P_2592010699) + 4024);
+ t32 = (t28 + 88U);
+ *((char **)t32) = t31;
+ t33 = (char *)alloca(t23);
+ t34 = (t28 + 56U);
+ *((char **)t34) = t33;
+ memcpy(t33, t10, t23);
+ t35 = (t28 + 64U);
+ *((char **)t35) = t24;
+ t36 = (t28 + 80U);
+ *((unsigned int *)t36) = t23;
+ t37 = (t7 + 4U);
+ *((char **)t37) = t2;
+ t38 = (t7 + 12U);
+ *((char **)t38) = t3;
+ t39 = (t7 + 20U);
+ *((char **)t39) = t4;
+ t40 = (t7 + 28U);
+ *((char **)t40) = t5;
+ t41 = (t7 + 36U);
+ *((char **)t41) = t8;
+ t42 = xsi_access_variable_all(t2);
+ t43 = (t42 + 56U);
+ t44 = *((char **)t43);
+ t30 = (0 + 0U);
+ t43 = (t44 + t30);
+ t45 = (t28 + 56U);
+ t46 = *((char **)t45);
+ t45 = (t46 + 0);
+ t47 = (t0 + 20224U);
+ t48 = *((char **)t47);
+ t49 = *((int *)t48);
+ t50 = (t49 + 1);
+ t51 = (0 - t50);
+ t52 = (t51 * -1);
+ t52 = (t52 + 1);
+ t52 = (t52 * 1U);
+ memcpy(t45, t43, t52);
+ t9 = (t28 + 56U);
+ t10 = *((char **)t9);
+ t9 = (t24 + 0U);
+ t11 = *((int *)t9);
+ t13 = (t0 + 20224U);
+ t17 = *((char **)t13);
+ t14 = *((int *)t17);
+ t15 = (t14 - 1);
+ t12 = (t11 - t15);
+ t13 = (t24 + 4U);
+ t16 = *((int *)t13);
+ t18 = (t24 + 8U);
+ t20 = *((int *)t18);
+ xsi_vhdl_check_range_of_slice(t11, t16, t20, t15, 0, -1);
+ t23 = (t12 * 1U);
+ t30 = (0 + t23);
+ t19 = (t10 + t30);
+ t25 = (t3 + 0);
+ t31 = (t0 + 20224U);
+ t32 = *((char **)t31);
+ t21 = *((int *)t32);
+ t22 = (t21 - 1);
+ t26 = (0 - t22);
+ t52 = (t26 * -1);
+ t52 = (t52 + 1);
+ t53 = (1U * t52);
+ memcpy(t25, t19, t53);
+ t9 = (t28 + 56U);
+ t10 = *((char **)t9);
+ t9 = (t24 + 0U);
+ t11 = *((int *)t9);
+ t13 = (t24 + 0U);
+ t15 = *((int *)t13);
+ t17 = (t24 + 4U);
+ t16 = *((int *)t17);
+ t18 = (t24 + 8U);
+ t20 = *((int *)t18);
+ if (t15 > t16)
+ goto LAB2;
+
+LAB3: if (t20 == -1)
+ goto LAB7;
+
+LAB8: t14 = t16;
+
+LAB4: t12 = (t11 - t14);
+ t19 = (t0 + 20224U);
+ t25 = *((char **)t19);
+ t21 = *((int *)t25);
+ t19 = (t24 + 4U);
+ t22 = *((int *)t19);
+ t31 = (t24 + 8U);
+ t26 = *((int *)t31);
+ xsi_vhdl_check_range_of_slice(t11, t22, t26, t14, t21, -1);
+ t23 = (t12 * 1U);
+ t30 = (0 + t23);
+ t32 = (t10 + t30);
+ t34 = (t5 + 0);
+ t35 = (t24 + 0U);
+ t29 = *((int *)t35);
+ t36 = (t24 + 4U);
+ t49 = *((int *)t36);
+ t42 = (t24 + 8U);
+ t50 = *((int *)t42);
+ if (t29 > t49)
+ goto LAB9;
+
+LAB10: if (t50 == -1)
+ goto LAB14;
+
+LAB15: t27 = t49;
+
+LAB11: t43 = (t0 + 20224U);
+ t44 = *((char **)t43);
+ t51 = *((int *)t44);
+ t54 = (t51 - t27);
+ t52 = (t54 * -1);
+ t52 = (t52 + 1);
+ t53 = (1U * t52);
+ memcpy(t34, t32, t53);
+
+LAB1: return;
+LAB2: if (t20 == 1)
+ goto LAB5;
+
+LAB6: t14 = t15;
+ goto LAB4;
+
+LAB5: t14 = t16;
+ goto LAB4;
+
+LAB7: t14 = t15;
+ goto LAB4;
+
+LAB9: if (t50 == 1)
+ goto LAB12;
+
+LAB13: t27 = t29;
+ goto LAB11;
+
+LAB12: t27 = t49;
+ goto LAB11;
+
+LAB14: t27 = t29;
+ goto LAB11;
+
+}
+
+void xilinxcorelib_a_4048593843_3212880686_sub_2068494565_3212880686(char *t0, char *t1, char *t2, char *t3, char *t4)
+{
+ char t5[152];
+ char t6[32];
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+ char *t16;
+ char *t17;
+ char *t18;
+ char *t19;
+ char *t20;
+ char *t21;
+ unsigned char t22;
+ int t23;
+ int t24;
+
+LAB0: t7 = (t5 + 4U);
+ t8 = (t0 + 33256);
+ t9 = (t7 + 56U);
+ *((char **)t9) = t8;
+ t10 = (t7 + 40U);
+ *((char **)t10) = 0;
+ t11 = (t7 + 64U);
+ *((int *)t11) = 1;
+ t12 = (t7 + 48U);
+ *((char **)t12) = 0;
+ t13 = (t5 + 76U);
+ t14 = (t0 + 33256);
+ t15 = (t13 + 56U);
+ *((char **)t15) = t14;
+ t16 = (t13 + 40U);
+ *((char **)t16) = 0;
+ t17 = (t13 + 64U);
+ *((int *)t17) = 1;
+ t18 = (t13 + 48U);
+ *((char **)t18) = 0;
+ t19 = (t6 + 4U);
+ *((char **)t19) = t2;
+ t20 = (t6 + 12U);
+ *((char **)t20) = t3;
+ t21 = (t6 + 20U);
+ *((char **)t21) = t4;
+ xsi_access_variable_assign(t7, t3);
+ t8 = xsi_access_variable_all(t7);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ t9 = (t10 + 88U);
+ t22 = xsi_access_variable_is_null(t9);
+ if (t22 != 0)
+ goto LAB2;
+
+LAB4: t8 = xsi_access_variable_all(t7);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ t9 = (t10 + 88U);
+ xsi_access_variable_assign(t13, t9);
+ t8 = xsi_access_variable_all(t13);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ t9 = (t10 + 16U);
+ xsi_access_variable_set_value(t9, 0);
+
+LAB3: xsi_access_variable_deallocate(t7);
+ t22 = xsi_access_variable_is_null(t13);
+ if (t22 != 0)
+ goto LAB5;
+
+LAB7:
+LAB6: xsi_access_variable_assign(t3, t13);
+ t23 = *((int *)t4);
+ t24 = (t23 - 1);
+ t8 = (t4 + 0);
+ *((int *)t8) = t24;
+
+LAB1: xsi_access_variable_delete(t13);
+ xsi_access_variable_delete(t7);
+ return;
+LAB2: xsi_access_variable_set_value(t13, 0);
+ goto LAB3;
+
+LAB5: xsi_access_variable_set_value(t2, 0);
+ goto LAB6;
+
+}
+
+void xilinxcorelib_a_4048593843_3212880686_sub_3751606365_3212880686(char *t0, char *t1, char *t2, char *t3)
+{
+ char t4[200];
+ char t5[24];
+ char t15[8];
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t16;
+ char *t17;
+ char *t18;
+ char *t19;
+ unsigned char t20;
+ int t21;
+ int t22;
+
+LAB0: t6 = (t4 + 4U);
+ t7 = (t0 + 33256);
+ t8 = (t6 + 56U);
+ *((char **)t8) = t7;
+ t9 = (t6 + 40U);
+ *((char **)t9) = 0;
+ t10 = (t6 + 64U);
+ *((int *)t10) = 1;
+ t11 = (t6 + 48U);
+ *((char **)t11) = 0;
+ t12 = (t4 + 76U);
+ t13 = ((STD_STANDARD) + 384);
+ t14 = (t12 + 88U);
+ *((char **)t14) = t13;
+ t16 = (t12 + 56U);
+ *((char **)t16) = t15;
+ *((int *)t15) = 0;
+ t17 = (t12 + 80U);
+ *((unsigned int *)t17) = 4U;
+ t18 = (t5 + 4U);
+ *((char **)t18) = t2;
+ t19 = (t5 + 12U);
+ *((char **)t19) = t3;
+ t20 = xsi_access_variable_is_null(t2);
+ if ((!(t20)) != 0)
+ goto LAB2;
+
+LAB4:
+LAB3: t7 = (t12 + 56U);
+ t8 = *((char **)t7);
+ t21 = *((int *)t8);
+ t7 = (t3 + 0);
+ *((int *)t7) = t21;
+
+LAB1: xsi_access_variable_delete(t6);
+ return;
+LAB2: xsi_access_variable_assign(t6, t2);
+ t7 = (t12 + 56U);
+ t8 = *((char **)t7);
+ t7 = (t8 + 0);
+ *((int *)t7) = 1;
+
+LAB5: t7 = xsi_access_variable_all(t6);
+ t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ t8 = (t9 + 16U);
+ t20 = xsi_access_variable_is_null(t8);
+ if ((!(t20)) != 0)
+ goto LAB6;
+
+LAB8: goto LAB3;
+
+LAB6: t10 = (t12 + 56U);
+ t11 = *((char **)t10);
+ t21 = *((int *)t11);
+ t22 = (t21 + 1);
+ t10 = (t12 + 56U);
+ t13 = *((char **)t10);
+ t10 = (t13 + 0);
+ *((int *)t10) = t22;
+ t7 = xsi_access_variable_all(t6);
+ t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ t8 = (t9 + 16U);
+ xsi_access_variable_assign(t6, t8);
+ goto LAB5;
+
+LAB7:;
+}
+
+char *xilinxcorelib_a_4048593843_3212880686_sub_4190946951_3212880686(char *t1, char *t2, int t3, int t4, int t5)
+{
+ char t6[248];
+ char t7[16];
+ char t16[16];
+ char t35[16];
+ char t50[16];
+ char *t0;
+ int t8;
+ int t9;
+ unsigned int t10;
+ char *t11;
+ char *t12;
+ int t13;
+ int t14;
+ unsigned int t15;
+ int t17;
+ char *t18;
+ char *t19;
+ int t20;
+ unsigned int t21;
+ char *t22;
+ char *t23;
+ char *t24;
+ char *t25;
+ char *t26;
+ char *t27;
+ int t28;
+ int t29;
+ char *t30;
+ char *t31;
+ int t32;
+ int t33;
+ unsigned int t34;
+ int t36;
+ char *t37;
+ char *t38;
+ int t39;
+ unsigned int t40;
+ char *t41;
+ char *t42;
+ char *t43;
+ char *t44;
+ char *t45;
+ char *t46;
+ char *t47;
+ char *t48;
+ char *t49;
+ char *t51;
+ char *t52;
+ char *t53;
+ char *t54;
+ unsigned char t55;
+
+LAB0: t8 = (t4 - 1);
+ t9 = (0 - t8);
+ t10 = (t9 * -1);
+ t10 = (t10 + 1);
+ t10 = (t10 * 1U);
+ t11 = xsi_get_transient_memory(t10);
+ memset(t11, 0, t10);
+ t12 = t11;
+ memset(t12, (unsigned char)2, t10);
+ t13 = (t4 - 1);
+ t14 = (0 - t13);
+ t15 = (t14 * -1);
+ t15 = (t15 + 1);
+ t15 = (t15 * 1U);
+ t17 = (t4 - 1);
+ t18 = (t16 + 0U);
+ t19 = (t18 + 0U);
+ *((int *)t19) = t17;
+ t19 = (t18 + 4U);
+ *((int *)t19) = 0;
+ t19 = (t18 + 8U);
+ *((int *)t19) = -1;
+ t20 = (0 - t17);
+ t21 = (t20 * -1);
+ t21 = (t21 + 1);
+ t19 = (t18 + 12U);
+ *((unsigned int *)t19) = t21;
+ t19 = (t6 + 4U);
+ t22 = ((IEEE_P_2592010699) + 4024);
+ t23 = (t19 + 88U);
+ *((char **)t23) = t22;
+ t24 = (char *)alloca(t15);
+ t25 = (t19 + 56U);
+ *((char **)t25) = t24;
+ memcpy(t24, t11, t15);
+ t26 = (t19 + 64U);
+ *((char **)t26) = t16;
+ t27 = (t19 + 80U);
+ *((unsigned int *)t27) = t15;
+ t28 = (t5 - 1);
+ t29 = (0 - t28);
+ t21 = (t29 * -1);
+ t21 = (t21 + 1);
+ t21 = (t21 * 1U);
+ t30 = xsi_get_transient_memory(t21);
+ memset(t30, 0, t21);
+ t31 = t30;
+ memset(t31, (unsigned char)2, t21);
+ t32 = (t5 - 1);
+ t33 = (0 - t32);
+ t34 = (t33 * -1);
+ t34 = (t34 + 1);
+ t34 = (t34 * 1U);
+ t36 = (t5 - 1);
+ t37 = (t35 + 0U);
+ t38 = (t37 + 0U);
+ *((int *)t38) = t36;
+ t38 = (t37 + 4U);
+ *((int *)t38) = 0;
+ t38 = (t37 + 8U);
+ *((int *)t38) = -1;
+ t39 = (0 - t36);
+ t40 = (t39 * -1);
+ t40 = (t40 + 1);
+ t38 = (t37 + 12U);
+ *((unsigned int *)t38) = t40;
+ t38 = (t6 + 124U);
+ t41 = ((IEEE_P_2592010699) + 4024);
+ t42 = (t38 + 88U);
+ *((char **)t42) = t41;
+ t43 = (char *)alloca(t34);
+ t44 = (t38 + 56U);
+ *((char **)t44) = t43;
+ memcpy(t43, t30, t34);
+ t45 = (t38 + 64U);
+ *((char **)t45) = t35;
+ t46 = (t38 + 80U);
+ *((unsigned int *)t46) = t34;
+ t47 = (t7 + 4U);
+ *((int *)t47) = t3;
+ t48 = (t7 + 8U);
+ *((int *)t48) = t4;
+ t49 = (t7 + 12U);
+ *((int *)t49) = t5;
+ t51 = ieee_p_3499444699_sub_2213602152_3499444699(IEEE_P_3499444699, t50, t3, t4);
+ t52 = (t19 + 56U);
+ t53 = *((char **)t52);
+ t52 = (t53 + 0);
+ t54 = (t50 + 12U);
+ t40 = *((unsigned int *)t54);
+ t40 = (t40 * 1U);
+ memcpy(t52, t51, t40);
+ t55 = (t5 <= t4);
+ if (t55 != 0)
+ goto LAB2;
+
+LAB4: t11 = (t19 + 56U);
+ t12 = *((char **)t11);
+ t11 = (t16 + 0U);
+ t8 = *((int *)t11);
+ t9 = (t5 - 1);
+ t10 = (t8 - t9);
+ t18 = (t16 + 4U);
+ t13 = *((int *)t18);
+ t22 = (t16 + 8U);
+ t14 = *((int *)t22);
+ xsi_vhdl_check_range_of_slice(t8, t13, t14, t9, 0, -1);
+ t15 = (t10 * 1U);
+ t21 = (0 + t15);
+ t23 = (t12 + t21);
+ t25 = (t38 + 56U);
+ t26 = *((char **)t25);
+ t25 = (t26 + 0);
+ t17 = (t5 - 1);
+ t20 = (0 - t17);
+ t34 = (t20 * -1);
+ t34 = (t34 + 1);
+ t40 = (1U * t34);
+ memcpy(t25, t23, t40);
+
+LAB3: t11 = (t38 + 56U);
+ t12 = *((char **)t11);
+ t11 = (t35 + 12U);
+ t10 = *((unsigned int *)t11);
+ t10 = (t10 * 1U);
+ t0 = xsi_get_transient_memory(t10);
+ memcpy(t0, t12, t10);
+ t18 = (t35 + 0U);
+ t8 = *((int *)t18);
+ t22 = (t35 + 4U);
+ t9 = *((int *)t22);
+ t23 = (t35 + 8U);
+ t13 = *((int *)t23);
+ t25 = (t2 + 0U);
+ t26 = (t25 + 0U);
+ *((int *)t26) = t8;
+ t26 = (t25 + 4U);
+ *((int *)t26) = t9;
+ t26 = (t25 + 8U);
+ *((int *)t26) = t13;
+ t14 = (t9 - t8);
+ t15 = (t14 * t13);
+ t15 = (t15 + 1);
+ t26 = (t25 + 12U);
+ *((unsigned int *)t26) = t15;
+
+LAB1: return t0;
+LAB2: t11 = (t19 + 56U);
+ t12 = *((char **)t11);
+ t11 = (t16 + 0U);
+ t8 = *((int *)t11);
+ t9 = (t4 - 1);
+ t10 = (t8 - t9);
+ t13 = (t4 - t5);
+ t18 = (t16 + 4U);
+ t14 = *((int *)t18);
+ t22 = (t16 + 8U);
+ t17 = *((int *)t22);
+ xsi_vhdl_check_range_of_slice(t8, t14, t17, t9, t13, -1);
+ t15 = (t10 * 1U);
+ t21 = (0 + t15);
+ t23 = (t12 + t21);
+ t25 = (t38 + 56U);
+ t26 = *((char **)t25);
+ t25 = (t26 + 0);
+ t20 = (t4 - 1);
+ t28 = (t4 - t5);
+ t29 = (t28 - t20);
+ t34 = (t29 * -1);
+ t34 = (t34 + 1);
+ t40 = (1U * t34);
+ memcpy(t25, t23, t40);
+ goto LAB3;
+
+LAB5:;
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_0(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+
+LAB0:
+LAB3: t1 = (t0 + 29624);
+ t2 = (t1 + 56U);
+ t3 = *((char **)t2);
+ t4 = (t3 + 56U);
+ t5 = *((char **)t4);
+ *((unsigned char *)t5) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2:
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_1(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+
+LAB0:
+LAB3: t1 = (t0 + 29688);
+ t2 = (t1 + 56U);
+ t3 = *((char **)t2);
+ t4 = (t3 + 56U);
+ t5 = *((char **)t4);
+ *((unsigned char *)t5) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2:
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_2(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+
+LAB0:
+LAB3: t1 = (t0 + 29752);
+ t2 = (t1 + 56U);
+ t3 = *((char **)t2);
+ t4 = (t3 + 56U);
+ t5 = *((char **)t4);
+ *((unsigned char *)t5) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2:
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_3(char *t0)
+{
+ char *t1;
+ char *t2;
+ int t3;
+ char *t4;
+ int t5;
+ int t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+
+LAB0:
+LAB3: t1 = (t0 + 8528U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20464U);
+ t4 = *((char **)t1);
+ t5 = *((int *)t4);
+ t6 = (t3 * t5);
+ t1 = (t0 + 29816);
+ t7 = (t1 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t6;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t11 = (t0 + 29208);
+ *((int *)t11) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_4(char *t0)
+{
+ char *t1;
+ char *t2;
+ int t3;
+ char *t4;
+ int t5;
+ int t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+
+LAB0:
+LAB3: t1 = (t0 + 8688U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t5 = *((int *)t4);
+ t6 = (t3 * t5);
+ t1 = (t0 + 29880);
+ t7 = (t1 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t6;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t11 = (t0 + 29224);
+ *((int *)t11) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_5(char *t0)
+{
+ char *t1;
+ char *t2;
+ int t3;
+ char *t4;
+ int t5;
+ int t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+
+LAB0:
+LAB3: t1 = (t0 + 8848U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20464U);
+ t4 = *((char **)t1);
+ t5 = *((int *)t4);
+ t6 = (t3 * t5);
+ t1 = (t0 + 29944);
+ t7 = (t1 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t6;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t11 = (t0 + 29240);
+ *((int *)t11) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_6(char *t0)
+{
+ char *t1;
+ char *t2;
+ int t3;
+ char *t4;
+ int t5;
+ int t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+
+LAB0:
+LAB3: t1 = (t0 + 9008U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t5 = *((int *)t4);
+ t6 = (t3 * t5);
+ t1 = (t0 + 30008);
+ t7 = (t1 + 56U);
+ t8 = *((char **)t7);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t6;
+ xsi_driver_first_trans_fast(t1);
+
+LAB2: t11 = (t0 + 29256);
+ *((int *)t11) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_7(char *t0)
+{
+ unsigned char t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+
+LAB0: t1 = (8 == 2);
+ if (t1 != 0)
+ goto LAB3;
+
+LAB4:
+LAB5: t7 = (t0 + 30072);
+ t8 = (t7 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ *((unsigned char *)t11) = (unsigned char)2;
+ xsi_driver_first_trans_fast(t7);
+
+LAB2:
+LAB1: return;
+LAB3: t2 = (t0 + 30072);
+ t3 = (t2 + 56U);
+ t4 = *((char **)t3);
+ t5 = (t4 + 56U);
+ t6 = *((char **)t5);
+ *((unsigned char *)t6) = (unsigned char)3;
+ xsi_driver_first_trans_fast(t2);
+ goto LAB2;
+
+LAB6: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_8(char *t0)
+{
+ char *t1;
+ char *t2;
+ int t3;
+ char *t4;
+ int t5;
+ unsigned char t6;
+ char *t7;
+ int t8;
+ char *t9;
+ int t10;
+ int t11;
+ char *t12;
+ char *t13;
+ char *t14;
+ char *t15;
+ int t16;
+
+LAB0: t1 = (t0 + 9488U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 9968U);
+ t4 = *((char **)t1);
+ t5 = *((int *)t4);
+ t6 = (t3 >= t5);
+ if (t6 != 0)
+ goto LAB2;
+
+LAB4: t1 = (t0 + 20464U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t5 = (8192 * t3);
+ t1 = (t0 + 9488U);
+ t4 = *((char **)t1);
+ t8 = *((int *)t4);
+ t10 = (t5 + t8);
+ t1 = (t0 + 9968U);
+ t7 = *((char **)t1);
+ t11 = *((int *)t7);
+ t16 = (t10 - t11);
+ t1 = (t0 + 30136);
+ t9 = (t1 + 56U);
+ t12 = *((char **)t9);
+ t13 = (t12 + 56U);
+ t14 = *((char **)t13);
+ *((int *)t14) = t16;
+ xsi_driver_first_trans_fast(t1);
+
+LAB3: t1 = (t0 + 9808U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 9648U);
+ t4 = *((char **)t1);
+ t5 = *((int *)t4);
+ t6 = (t3 >= t5);
+ if (t6 != 0)
+ goto LAB5;
+
+LAB7: t1 = (t0 + 20344U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t5 = (8192 * t3);
+ t1 = (t0 + 9808U);
+ t4 = *((char **)t1);
+ t8 = *((int *)t4);
+ t10 = (t5 + t8);
+ t1 = (t0 + 9648U);
+ t7 = *((char **)t1);
+ t11 = *((int *)t7);
+ t16 = (t10 - t11);
+ t1 = (t0 + 30200);
+ t9 = (t1 + 56U);
+ t12 = *((char **)t9);
+ t13 = (t12 + 56U);
+ t14 = *((char **)t13);
+ *((int *)t14) = t16;
+ xsi_driver_first_trans_fast(t1);
+
+LAB6: t1 = (t0 + 29272);
+ *((int *)t1) = 1;
+
+LAB1: return;
+LAB2: t1 = (t0 + 9488U);
+ t7 = *((char **)t1);
+ t8 = *((int *)t7);
+ t1 = (t0 + 9968U);
+ t9 = *((char **)t1);
+ t10 = *((int *)t9);
+ t11 = (t8 - t10);
+ t1 = (t0 + 30136);
+ t12 = (t1 + 56U);
+ t13 = *((char **)t12);
+ t14 = (t13 + 56U);
+ t15 = *((char **)t14);
+ *((int *)t15) = t11;
+ xsi_driver_first_trans_fast(t1);
+ goto LAB3;
+
+LAB5: t1 = (t0 + 9808U);
+ t7 = *((char **)t1);
+ t8 = *((int *)t7);
+ t1 = (t0 + 9648U);
+ t9 = *((char **)t1);
+ t10 = *((int *)t9);
+ t11 = (t8 - t10);
+ t1 = (t0 + 30200);
+ t12 = (t1 + 56U);
+ t13 = *((char **)t12);
+ t14 = (t13 + 56U);
+ t15 = *((char **)t14);
+ *((int *)t15) = t11;
+ xsi_driver_first_trans_fast(t1);
+ goto LAB6;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_9(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 13168U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 30264);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 29288);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_10(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 13328U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 30328);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 29304);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_11(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 13808U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 30392);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 29320);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_12(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 13968U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 30456);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 29336);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_13(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 14288U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 30520);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 29352);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_14(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 14608U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 30584);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 29368);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_15(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+
+LAB0:
+LAB3: t1 = xsi_get_transient_memory(13U);
+ memset(t1, 0, 13U);
+ t2 = t1;
+ memset(t2, (unsigned char)2, 13U);
+ t3 = (t0 + 30648);
+ t4 = (t3 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ memcpy(t7, t1, 13U);
+ xsi_driver_first_trans_fast_port(t3);
+
+LAB2:
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_16(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+
+LAB0:
+LAB3: t1 = xsi_get_transient_memory(13U);
+ memset(t1, 0, 13U);
+ t2 = t1;
+ memset(t2, (unsigned char)2, 13U);
+ t3 = (t0 + 30712);
+ t4 = (t3 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ memcpy(t7, t1, 13U);
+ xsi_driver_first_trans_fast_port(t3);
+
+LAB2:
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_17(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 10288U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 30776);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 29384);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_18(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 10128U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 30840);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 29400);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_19(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 10608U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 30904);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 29416);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_20(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+
+LAB0:
+LAB3: t1 = (t0 + 10448U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 30968);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t8 = (t0 + 29432);
+ *((int *)t8) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_21(char *t0)
+{
+ char t13[16];
+ char t26[16];
+ char t77[16];
+ char *t1;
+ char *t2;
+ int t3;
+ char *t4;
+ unsigned char t5;
+ unsigned char t6;
+ unsigned char t7;
+ char *t8;
+ char *t9;
+ char *t10;
+ char *t11;
+ char *t12;
+ unsigned char t14;
+ unsigned char t15;
+ unsigned char t16;
+ unsigned char t17;
+ unsigned char t18;
+ unsigned char t19;
+ char *t20;
+ char *t21;
+ int t22;
+ int t23;
+ int t24;
+ int t25;
+ char *t27;
+ int t28;
+ int t29;
+ int t30;
+ char *t31;
+ int t32;
+ char *t33;
+ char *t34;
+ unsigned int t35;
+ int t36;
+ int t37;
+ unsigned int t38;
+ unsigned int t39;
+ int t40;
+ int t41;
+ int t42;
+ int t43;
+ char *t44;
+ char *t45;
+ int t46;
+ int t47;
+ int t48;
+ int t49;
+ int t50;
+ unsigned int t51;
+ unsigned int t52;
+ char *t53;
+ char *t54;
+ char *t55;
+ int t56;
+ int t57;
+ int t58;
+ int t59;
+ char *t60;
+ char *t61;
+ int t62;
+ int t63;
+ int t64;
+ int t65;
+ char *t66;
+ char *t67;
+ int t68;
+ unsigned int t69;
+ char *t70;
+ char *t71;
+ char *t72;
+ char *t73;
+ char *t74;
+ char *t75;
+ char *t76;
+ char *t78;
+ unsigned int t79;
+ char *t80;
+ char *t81;
+ char *t82;
+ char *t83;
+ char *t84;
+
+LAB0: t1 = (t0 + 20824U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20944U);
+ t4 = *((char **)t1);
+ t1 = (t4 + 0);
+ *((int *)t1) = t3;
+ t1 = (t0 + 12528U);
+ t2 = *((char **)t1);
+ t5 = *((unsigned char *)t2);
+ t6 = (t5 == (unsigned char)3);
+ if (t6 != 0)
+ goto LAB2;
+
+LAB4: t1 = (t0 + 4328U);
+ t6 = xsi_signal_has_event(t1);
+ if (t6 == 1)
+ goto LAB10;
+
+LAB11: t5 = (unsigned char)0;
+
+LAB12: if (t5 != 0)
+ goto LAB8;
+
+LAB9:
+LAB3: t1 = (t0 + 11568U);
+ t2 = *((char **)t1);
+ t5 = *((unsigned char *)t2);
+ t6 = (t5 == (unsigned char)3);
+ if (t6 != 0)
+ goto LAB112;
+
+LAB114: t1 = (t0 + 4008U);
+ t6 = xsi_signal_has_event(t1);
+ if (t6 == 1)
+ goto LAB120;
+
+LAB121: t5 = (unsigned char)0;
+
+LAB122: if (t5 != 0)
+ goto LAB118;
+
+LAB119:
+LAB113: t1 = (t0 + 21064U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 31928);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ memcpy(t10, t2, 8U);
+ xsi_driver_first_trans_delta(t1, 0U, 8U, 100LL);
+ t11 = (t0 + 31928);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+ t1 = (t0 + 21184U);
+ t2 = *((char **)t1);
+ t3 = (0 - 1);
+ t35 = (t3 * -1);
+ t38 = (1U * t35);
+ t39 = (0 + t38);
+ t1 = (t2 + t39);
+ t5 = *((unsigned char *)t1);
+ t4 = (t0 + 31992);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ *((unsigned char *)t11) = t5;
+ xsi_driver_first_trans_delta(t4, 0U, 1, 100LL);
+ t12 = (t0 + 31992);
+ xsi_driver_intertial_reject(t12, 100LL, 100LL);
+ t1 = (t0 + 21184U);
+ t2 = *((char **)t1);
+ t3 = (1 - 1);
+ t35 = (t3 * -1);
+ t38 = (1U * t35);
+ t39 = (0 + t38);
+ t1 = (t2 + t39);
+ t5 = *((unsigned char *)t1);
+ t4 = (t0 + 32056);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ *((unsigned char *)t11) = t5;
+ xsi_driver_first_trans_delta(t4, 0U, 1, 100LL);
+ t12 = (t0 + 32056);
+ xsi_driver_intertial_reject(t12, 100LL, 100LL);
+ t1 = (t0 + 29448);
+ *((int *)t1) = 1;
+
+LAB1: return;
+LAB2: t7 = xilinxcorelib_a_4048593843_3212880686_sub_2978940197_3212880686(t0, 0);
+ t1 = (t0 + 31032);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((unsigned char *)t10) = t7;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31032);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+ t5 = xilinxcorelib_a_4048593843_3212880686_sub_2978940197_3212880686(t0, 0);
+ t1 = (t0 + 31096);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = t5;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31096);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = (t0 + 31160);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((int *)t9) = 0;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31160);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = (t0 + 31224);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((int *)t9) = 0;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31224);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = xsi_get_transient_memory(14U);
+ memset(t1, 0, 14U);
+ t2 = t1;
+ memset(t2, (unsigned char)2, 14U);
+ t4 = (t0 + 31288);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ memcpy(t11, t1, 14U);
+ xsi_driver_first_trans_delta(t4, 0U, 14U, 100LL);
+ t12 = (t0 + 31288);
+ xsi_driver_intertial_reject(t12, 100LL, 100LL);
+ t5 = xilinxcorelib_a_4048593843_3212880686_sub_2978940197_3212880686(t0, 0);
+ t1 = (t0 + 31352);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = t5;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31352);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t5 = xilinxcorelib_a_4048593843_3212880686_sub_2978940197_3212880686(t0, 0);
+ t1 = (t0 + 31416);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = t5;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31416);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = (t0 + 27952);
+ t2 = (t0 + 22064U);
+ t4 = (t0 + 22136U);
+ t8 = (t0 + 20824U);
+ t9 = *((char **)t8);
+ t8 = (t9 + 0);
+ xilinxcorelib_a_4048593843_3212880686_sub_1807611230_3212880686(t0, t1, t2, t4, t8);
+ t5 = (0 == 1);
+ if (t5 != 0)
+ goto LAB5;
+
+LAB7: t1 = (t0 + 21064U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 21064U);
+ t4 = *((char **)t1);
+ t1 = (t4 + 0);
+ memcpy(t1, t2, 8U);
+
+LAB6: t1 = xsi_get_transient_memory(2U);
+ memset(t1, 0, 2U);
+ t2 = t1;
+ memset(t2, (unsigned char)2, 2U);
+ t4 = (t0 + 21184U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ memcpy(t4, t1, 2U);
+ goto LAB3;
+
+LAB5: t1 = (t0 + 47480);
+ t4 = (t0 + 46584U);
+ t8 = xilinxcorelib_a_4048593843_3212880686_sub_3703097363_3212880686(t0, t13, t1, t4, 8);
+ t9 = (t0 + 21064U);
+ t10 = *((char **)t9);
+ t9 = (t10 + 0);
+ memcpy(t9, t8, 8U);
+ goto LAB6;
+
+LAB8: t2 = (t0 + 12688U);
+ t8 = *((char **)t2);
+ t16 = *((unsigned char *)t8);
+ t17 = (t16 == (unsigned char)3);
+ if (t17 == 1)
+ goto LAB16;
+
+LAB17: t15 = (unsigned char)0;
+
+LAB18: if (t15 != 0)
+ goto LAB13;
+
+LAB15: t1 = (t0 + 14128U);
+ t2 = *((char **)t1);
+ t5 = *((unsigned char *)t2);
+ t1 = (t0 + 31416);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((unsigned char *)t10) = t5;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31416);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+
+LAB14: t1 = (t0 + 8528U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 31224);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31224);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+ t5 = (0 == 0);
+ if (t5 != 0)
+ goto LAB19;
+
+LAB21: t1 = (t0 + 9168U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 8368U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 + t22);
+ t1 = (t0 + 20464U);
+ t8 = *((char **)t1);
+ t24 = *((int *)t8);
+ t25 = (t23 / t24);
+ t28 = (13 + 1);
+ t1 = ieee_p_3499444699_sub_2213602152_3499444699(IEEE_P_3499444699, t13, t25, t28);
+ t9 = (t0 + 31288);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ t12 = (t11 + 56U);
+ t20 = *((char **)t12);
+ memcpy(t20, t1, 14U);
+ xsi_driver_first_trans_delta(t9, 0U, 14U, 100LL);
+ t21 = (t0 + 31288);
+ xsi_driver_intertial_reject(t21, 100LL, 100LL);
+
+LAB20: t1 = (t0 + 4528U);
+ t2 = *((char **)t1);
+ t6 = *((unsigned char *)t2);
+ t7 = (t6 == (unsigned char)3);
+ if (t7 == 1)
+ goto LAB28;
+
+LAB29: t5 = (unsigned char)0;
+
+LAB30: if (t5 != 0)
+ goto LAB25;
+
+LAB27: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 19984U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t22 - 1);
+ t1 = (t0 + 20464U);
+ t8 = *((char **)t1);
+ t24 = *((int *)t8);
+ t25 = (t23 * t24);
+ t28 = (t25 + 1);
+ t5 = (t3 >= t28);
+ if (t5 != 0)
+ goto LAB36;
+
+LAB38: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 19984U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t22 - 2);
+ t1 = (t0 + 20464U);
+ t8 = *((char **)t1);
+ t24 = *((int *)t8);
+ t25 = (t23 * t24);
+ t28 = (t25 + 1);
+ t5 = (t3 >= t28);
+ if (t5 != 0)
+ goto LAB39;
+
+LAB40: t1 = (t0 + 31032);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31032);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = (t0 + 31096);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31096);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+
+LAB37:
+LAB26: t1 = (t0 + 4528U);
+ t2 = *((char **)t1);
+ t5 = *((unsigned char *)t2);
+ t6 = (t5 == (unsigned char)3);
+ if (t6 != 0)
+ goto LAB41;
+
+LAB43:
+LAB42: t5 = (0 == 1);
+ if (t5 != 0)
+ goto LAB69;
+
+LAB71: t5 = (0 == 2);
+ if (t5 != 0)
+ goto LAB78;
+
+LAB79: t5 = (0 == 3);
+ if (t5 != 0)
+ goto LAB86;
+
+LAB87: t5 = (0 == 4);
+ if (t5 != 0)
+ goto LAB94;
+
+LAB95:
+LAB70: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (t3 - 1);
+ t1 = (t0 + 20464U);
+ t4 = *((char **)t1);
+ t23 = *((int *)t4);
+ t24 = (t22 / t23);
+ t25 = (1 + t24);
+ t1 = (t0 + 21544U);
+ t8 = *((char **)t1);
+ t28 = *((int *)t8);
+ t29 = (t28 - 1);
+ t6 = (t25 == t29);
+ if (t6 == 1)
+ goto LAB105;
+
+LAB106: t5 = (unsigned char)0;
+
+LAB107: if (t5 != 0)
+ goto LAB102;
+
+LAB104: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (t3 - 1);
+ t1 = (t0 + 20464U);
+ t4 = *((char **)t1);
+ t23 = *((int *)t4);
+ t24 = (t22 / t23);
+ t25 = (1 + t24);
+ t1 = (t0 + 21544U);
+ t8 = *((char **)t1);
+ t28 = *((int *)t8);
+ t5 = (t25 >= t28);
+ if (t5 != 0)
+ goto LAB108;
+
+LAB109: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (t3 - 1);
+ t1 = (t0 + 20464U);
+ t4 = *((char **)t1);
+ t23 = *((int *)t4);
+ t24 = (t22 / t23);
+ t25 = (1 + t24);
+ t1 = (t0 + 21664U);
+ t8 = *((char **)t1);
+ t28 = *((int *)t8);
+ t5 = (t25 < t28);
+ if (t5 != 0)
+ goto LAB110;
+
+LAB111:
+LAB103: goto LAB3;
+
+LAB10: t2 = (t0 + 4368U);
+ t4 = *((char **)t2);
+ t7 = *((unsigned char *)t4);
+ t14 = (t7 == (unsigned char)3);
+ t5 = t14;
+ goto LAB12;
+
+LAB13: t2 = (t0 + 31416);
+ t10 = (t2 + 56U);
+ t11 = *((char **)t10);
+ t12 = (t11 + 56U);
+ t20 = *((char **)t12);
+ *((unsigned char *)t20) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t2, 0U, 1, 100LL);
+ t21 = (t0 + 31416);
+ xsi_driver_intertial_reject(t21, 100LL, 100LL);
+ goto LAB14;
+
+LAB16: t2 = (t0 + 12528U);
+ t9 = *((char **)t2);
+ t18 = *((unsigned char *)t9);
+ t19 = (t18 == (unsigned char)2);
+ t15 = t19;
+ goto LAB18;
+
+LAB19: t1 = (t0 + 9168U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t6 = (t3 < 1);
+ if (t6 != 0)
+ goto LAB22;
+
+LAB24: t1 = (t0 + 9168U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (t3 - 1);
+ t1 = (t0 + 20464U);
+ t4 = *((char **)t1);
+ t23 = *((int *)t4);
+ t24 = (t22 / t23);
+ t25 = (1 + t24);
+ t1 = ieee_p_3499444699_sub_2213602152_3499444699(IEEE_P_3499444699, t13, t25, 13);
+ t9 = ((IEEE_P_2592010699) + 4024);
+ t8 = xsi_base_array_concat(t8, t26, t9, (char)97, t1, t13, (char)99, (unsigned char)2, (char)101);
+ t10 = (t0 + 31288);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ t20 = (t12 + 56U);
+ t21 = *((char **)t20);
+ memcpy(t21, t8, 14U);
+ xsi_driver_first_trans_delta(t10, 0U, 14U, 100LL);
+ t27 = (t0 + 31288);
+ xsi_driver_intertial_reject(t27, 100LL, 100LL);
+
+LAB23: goto LAB20;
+
+LAB22: t1 = xsi_get_transient_memory(14U);
+ memset(t1, 0, 14U);
+ t4 = t1;
+ memset(t4, (unsigned char)2, 14U);
+ t8 = (t0 + 31288);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ memcpy(t12, t1, 14U);
+ xsi_driver_first_trans_delta(t8, 0U, 14U, 100LL);
+ t20 = (t0 + 31288);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+ goto LAB23;
+
+LAB25: t1 = (t0 + 20944U);
+ t8 = *((char **)t1);
+ t3 = *((int *)t8);
+ t1 = (t0 + 20464U);
+ t9 = *((char **)t1);
+ t22 = *((int *)t9);
+ t23 = (t3 + t22);
+ t1 = (t0 + 19984U);
+ t10 = *((char **)t1);
+ t24 = *((int *)t10);
+ t25 = (t24 - 1);
+ t1 = (t0 + 20464U);
+ t11 = *((char **)t1);
+ t28 = *((int *)t11);
+ t29 = (t25 * t28);
+ t30 = (t29 + 1);
+ t16 = (t23 >= t30);
+ if (t16 != 0)
+ goto LAB31;
+
+LAB33: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20464U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 + t22);
+ t1 = (t0 + 19984U);
+ t8 = *((char **)t1);
+ t24 = *((int *)t8);
+ t25 = (t24 - 2);
+ t1 = (t0 + 20464U);
+ t9 = *((char **)t1);
+ t28 = *((int *)t9);
+ t29 = (t25 * t28);
+ t30 = (t29 + 1);
+ t5 = (t23 >= t30);
+ if (t5 != 0)
+ goto LAB34;
+
+LAB35: t1 = (t0 + 31032);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31032);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = (t0 + 31096);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31096);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+
+LAB32: goto LAB26;
+
+LAB28: t1 = (t0 + 10288U);
+ t4 = *((char **)t1);
+ t14 = *((unsigned char *)t4);
+ t15 = (t14 == (unsigned char)2);
+ t5 = t15;
+ goto LAB30;
+
+LAB31: t1 = (t0 + 31032);
+ t12 = (t1 + 56U);
+ t20 = *((char **)t12);
+ t21 = (t20 + 56U);
+ t27 = *((char **)t21);
+ *((unsigned char *)t27) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t31 = (t0 + 31032);
+ xsi_driver_intertial_reject(t31, 100LL, 100LL);
+ t1 = (t0 + 31096);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31096);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ goto LAB32;
+
+LAB34: t1 = (t0 + 31032);
+ t10 = (t1 + 56U);
+ t11 = *((char **)t10);
+ t12 = (t11 + 56U);
+ t20 = *((char **)t12);
+ *((unsigned char *)t20) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t21 = (t0 + 31032);
+ xsi_driver_intertial_reject(t21, 100LL, 100LL);
+ t1 = (t0 + 31096);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31096);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ goto LAB32;
+
+LAB36: t1 = (t0 + 31032);
+ t9 = (t1 + 56U);
+ t10 = *((char **)t9);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ *((unsigned char *)t12) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t20 = (t0 + 31032);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+ t1 = (t0 + 31096);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31096);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ goto LAB37;
+
+LAB39: t1 = (t0 + 31032);
+ t9 = (t1 + 56U);
+ t10 = *((char **)t9);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ *((unsigned char *)t12) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t20 = (t0 + 31032);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+ t1 = (t0 + 31096);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31096);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ goto LAB37;
+
+LAB41: t1 = (t0 + 10288U);
+ t4 = *((char **)t1);
+ t7 = *((unsigned char *)t4);
+ t14 = (t7 != (unsigned char)3);
+ if (t14 != 0)
+ goto LAB44;
+
+LAB46:
+LAB45: goto LAB42;
+
+LAB44: t1 = (t0 + 20944U);
+ t8 = *((char **)t1);
+ t3 = *((int *)t8);
+ t1 = (t0 + 20464U);
+ t9 = *((char **)t1);
+ t22 = *((int *)t9);
+ t23 = (t3 / t22);
+ t1 = (t0 + 19984U);
+ t10 = *((char **)t1);
+ t24 = *((int *)t10);
+ t15 = (t23 == t24);
+ if (t15 != 0)
+ goto LAB47;
+
+LAB49: t1 = (t0 + 20944U);
+ t11 = *((char **)t1);
+ t25 = *((int *)t11);
+ t1 = (t0 + 20464U);
+ t12 = *((char **)t1);
+ t28 = *((int *)t12);
+ t29 = (t25 / t28);
+ t30 = (t29 + 1);
+ t1 = (t0 + 19984U);
+ t20 = *((char **)t1);
+ t32 = *((int *)t20);
+ t16 = (t30 == t32);
+ if (t16 != 0)
+ goto LAB50;
+
+LAB51: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20464U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 / t22);
+ t24 = (t23 + 2);
+ t1 = (t0 + 19984U);
+ t8 = *((char **)t1);
+ t25 = *((int *)t8);
+ t5 = (t24 == t25);
+ if (t5 != 0)
+ goto LAB57;
+
+LAB58: t1 = (t0 + 20464U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 47497);
+ *((int *)t1) = t3;
+ t4 = (t0 + 47501);
+ *((int *)t4) = 1;
+ t22 = t3;
+ t23 = 1;
+
+LAB64: if (t22 >= t23)
+ goto LAB65;
+
+LAB67: t1 = (t0 + 8528U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (t3 + 1);
+ t23 = xsi_vhdl_mod(t22, 8192);
+ t1 = (t0 + 31160);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t23;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31160);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+
+LAB48: goto LAB45;
+
+LAB47: goto LAB48;
+
+LAB50: t1 = (t0 + 31032);
+ t21 = (t1 + 56U);
+ t27 = *((char **)t21);
+ t31 = (t27 + 56U);
+ t33 = *((char **)t31);
+ *((unsigned char *)t33) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t34 = (t0 + 31032);
+ xsi_driver_intertial_reject(t34, 100LL, 100LL);
+ t1 = (t0 + 20464U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 47481);
+ *((int *)t1) = t3;
+ t4 = (t0 + 47485);
+ *((int *)t4) = 1;
+ t22 = t3;
+ t23 = 1;
+
+LAB52: if (t22 >= t23)
+ goto LAB53;
+
+LAB55: t1 = (t0 + 8528U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (t3 + 1);
+ t23 = xsi_vhdl_mod(t22, 8192);
+ t1 = (t0 + 31160);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t23;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31160);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+ goto LAB48;
+
+LAB53: t8 = (t0 + 27952);
+ t9 = (t0 + 22064U);
+ t10 = (t0 + 22136U);
+ t11 = (t0 + 3888U);
+ t12 = *((char **)t11);
+ t11 = (t0 + 20224U);
+ t20 = *((char **)t11);
+ t24 = *((int *)t20);
+ t11 = (t0 + 47481);
+ t25 = *((int *)t11);
+ t28 = (t24 * t25);
+ t29 = (t28 - 1);
+ t35 = (7 - t29);
+ t21 = (t0 + 20224U);
+ t27 = *((char **)t21);
+ t30 = *((int *)t27);
+ t21 = (t0 + 47481);
+ t32 = *((int *)t21);
+ t36 = (t32 - 1);
+ t37 = (t30 * t36);
+ xsi_vhdl_check_range_of_slice(7, 0, -1, t29, t37, -1);
+ t38 = (t35 * 1U);
+ t39 = (0 + t38);
+ t31 = (t12 + t39);
+ t33 = (t0 + 20224U);
+ t34 = *((char **)t33);
+ t40 = *((int *)t34);
+ t33 = (t0 + 47481);
+ t41 = *((int *)t33);
+ t42 = (t40 * t41);
+ t43 = (t42 - 1);
+ t44 = (t0 + 20224U);
+ t45 = *((char **)t44);
+ t46 = *((int *)t45);
+ t44 = (t0 + 47481);
+ t47 = *((int *)t44);
+ t48 = (t47 - 1);
+ t49 = (t46 * t48);
+ t50 = (t49 - t43);
+ t51 = (t50 * -1);
+ t51 = (t51 + 1);
+ t52 = (1U * t51);
+ t53 = (char *)alloca(t52);
+ memcpy(t53, t31, t52);
+ t54 = (t0 + 20224U);
+ t55 = *((char **)t54);
+ t56 = *((int *)t55);
+ t54 = (t0 + 47481);
+ t57 = *((int *)t54);
+ t58 = (t56 * t57);
+ t59 = (t58 - 1);
+ t60 = (t0 + 20224U);
+ t61 = *((char **)t60);
+ t62 = *((int *)t61);
+ t60 = (t0 + 47481);
+ t63 = *((int *)t60);
+ t64 = (t63 - 1);
+ t65 = (t62 * t64);
+ t66 = (t13 + 0U);
+ t67 = (t66 + 0U);
+ *((int *)t67) = t59;
+ t67 = (t66 + 4U);
+ *((int *)t67) = t65;
+ t67 = (t66 + 8U);
+ *((int *)t67) = -1;
+ t68 = (t65 - t59);
+ t69 = (t68 * -1);
+ t69 = (t69 + 1);
+ t67 = (t66 + 12U);
+ *((unsigned int *)t67) = t69;
+ t67 = (t0 + 20824U);
+ t70 = *((char **)t67);
+ t67 = (t70 + 0);
+ t71 = (t0 + 14928U);
+ t72 = *((char **)t71);
+ t5 = *((unsigned char *)t72);
+ t71 = (t0 + 5648U);
+ t73 = *((char **)t71);
+ t6 = *((unsigned char *)t73);
+ t74 = ((IEEE_P_2592010699) + 4024);
+ t71 = xsi_base_array_concat(t71, t26, t74, (char)99, t5, (char)99, t6, (char)101);
+ t75 = (t0 + 5808U);
+ t76 = *((char **)t75);
+ t7 = *((unsigned char *)t76);
+ t78 = ((IEEE_P_2592010699) + 4024);
+ t75 = xsi_base_array_concat(t75, t77, t78, (char)97, t71, t26, (char)99, t7, (char)101);
+ t69 = (1U + 1U);
+ t79 = (t69 + 1U);
+ t80 = (char *)alloca(t79);
+ memcpy(t80, t75, t79);
+ xilinxcorelib_a_4048593843_3212880686_sub_2129810750_3212880686(t0, t8, t9, t10, t53, t13, t67, t80);
+
+LAB54: t1 = (t0 + 47481);
+ t22 = *((int *)t1);
+ t2 = (t0 + 47485);
+ t23 = *((int *)t2);
+ if (t22 == t23)
+ goto LAB55;
+
+LAB56: t3 = (t22 + -1);
+ t22 = t3;
+ t4 = (t0 + 47481);
+ *((int *)t4) = t22;
+ goto LAB52;
+
+LAB57: t1 = (t0 + 31096);
+ t9 = (t1 + 56U);
+ t10 = *((char **)t9);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ *((unsigned char *)t12) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t20 = (t0 + 31096);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+ t1 = (t0 + 20464U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 47489);
+ *((int *)t1) = t3;
+ t4 = (t0 + 47493);
+ *((int *)t4) = 1;
+ t22 = t3;
+ t23 = 1;
+
+LAB59: if (t22 >= t23)
+ goto LAB60;
+
+LAB62: t1 = (t0 + 8528U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (t3 + 1);
+ t23 = xsi_vhdl_mod(t22, 8192);
+ t1 = (t0 + 31160);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t23;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31160);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+ goto LAB48;
+
+LAB60: t8 = (t0 + 27952);
+ t9 = (t0 + 22064U);
+ t10 = (t0 + 22136U);
+ t11 = (t0 + 3888U);
+ t12 = *((char **)t11);
+ t11 = (t0 + 20224U);
+ t20 = *((char **)t11);
+ t24 = *((int *)t20);
+ t11 = (t0 + 47489);
+ t25 = *((int *)t11);
+ t28 = (t24 * t25);
+ t29 = (t28 - 1);
+ t35 = (7 - t29);
+ t21 = (t0 + 20224U);
+ t27 = *((char **)t21);
+ t30 = *((int *)t27);
+ t21 = (t0 + 47489);
+ t32 = *((int *)t21);
+ t36 = (t32 - 1);
+ t37 = (t30 * t36);
+ xsi_vhdl_check_range_of_slice(7, 0, -1, t29, t37, -1);
+ t38 = (t35 * 1U);
+ t39 = (0 + t38);
+ t31 = (t12 + t39);
+ t33 = (t0 + 20224U);
+ t34 = *((char **)t33);
+ t40 = *((int *)t34);
+ t33 = (t0 + 47489);
+ t41 = *((int *)t33);
+ t42 = (t40 * t41);
+ t43 = (t42 - 1);
+ t44 = (t0 + 20224U);
+ t45 = *((char **)t44);
+ t46 = *((int *)t45);
+ t44 = (t0 + 47489);
+ t47 = *((int *)t44);
+ t48 = (t47 - 1);
+ t49 = (t46 * t48);
+ t50 = (t49 - t43);
+ t51 = (t50 * -1);
+ t51 = (t51 + 1);
+ t52 = (1U * t51);
+ t54 = (char *)alloca(t52);
+ memcpy(t54, t31, t52);
+ t55 = (t0 + 20224U);
+ t60 = *((char **)t55);
+ t56 = *((int *)t60);
+ t55 = (t0 + 47489);
+ t57 = *((int *)t55);
+ t58 = (t56 * t57);
+ t59 = (t58 - 1);
+ t61 = (t0 + 20224U);
+ t66 = *((char **)t61);
+ t62 = *((int *)t66);
+ t61 = (t0 + 47489);
+ t63 = *((int *)t61);
+ t64 = (t63 - 1);
+ t65 = (t62 * t64);
+ t67 = (t13 + 0U);
+ t70 = (t67 + 0U);
+ *((int *)t70) = t59;
+ t70 = (t67 + 4U);
+ *((int *)t70) = t65;
+ t70 = (t67 + 8U);
+ *((int *)t70) = -1;
+ t68 = (t65 - t59);
+ t69 = (t68 * -1);
+ t69 = (t69 + 1);
+ t70 = (t67 + 12U);
+ *((unsigned int *)t70) = t69;
+ t70 = (t0 + 20824U);
+ t71 = *((char **)t70);
+ t70 = (t71 + 0);
+ t72 = (t0 + 14928U);
+ t73 = *((char **)t72);
+ t5 = *((unsigned char *)t73);
+ t72 = (t0 + 5648U);
+ t74 = *((char **)t72);
+ t6 = *((unsigned char *)t74);
+ t75 = ((IEEE_P_2592010699) + 4024);
+ t72 = xsi_base_array_concat(t72, t26, t75, (char)99, t5, (char)99, t6, (char)101);
+ t76 = (t0 + 5808U);
+ t78 = *((char **)t76);
+ t7 = *((unsigned char *)t78);
+ t81 = ((IEEE_P_2592010699) + 4024);
+ t76 = xsi_base_array_concat(t76, t77, t81, (char)97, t72, t26, (char)99, t7, (char)101);
+ t69 = (1U + 1U);
+ t79 = (t69 + 1U);
+ t82 = (char *)alloca(t79);
+ memcpy(t82, t76, t79);
+ xilinxcorelib_a_4048593843_3212880686_sub_2129810750_3212880686(t0, t8, t9, t10, t54, t13, t70, t82);
+
+LAB61: t1 = (t0 + 47489);
+ t22 = *((int *)t1);
+ t2 = (t0 + 47493);
+ t23 = *((int *)t2);
+ if (t22 == t23)
+ goto LAB62;
+
+LAB63: t3 = (t22 + -1);
+ t22 = t3;
+ t4 = (t0 + 47489);
+ *((int *)t4) = t22;
+ goto LAB59;
+
+LAB65: t8 = (t0 + 27952);
+ t9 = (t0 + 22064U);
+ t10 = (t0 + 22136U);
+ t11 = (t0 + 3888U);
+ t12 = *((char **)t11);
+ t11 = (t0 + 20224U);
+ t20 = *((char **)t11);
+ t24 = *((int *)t20);
+ t11 = (t0 + 47497);
+ t25 = *((int *)t11);
+ t28 = (t24 * t25);
+ t29 = (t28 - 1);
+ t35 = (7 - t29);
+ t21 = (t0 + 20224U);
+ t27 = *((char **)t21);
+ t30 = *((int *)t27);
+ t21 = (t0 + 47497);
+ t32 = *((int *)t21);
+ t36 = (t32 - 1);
+ t37 = (t30 * t36);
+ xsi_vhdl_check_range_of_slice(7, 0, -1, t29, t37, -1);
+ t38 = (t35 * 1U);
+ t39 = (0 + t38);
+ t31 = (t12 + t39);
+ t33 = (t0 + 20224U);
+ t34 = *((char **)t33);
+ t40 = *((int *)t34);
+ t33 = (t0 + 47497);
+ t41 = *((int *)t33);
+ t42 = (t40 * t41);
+ t43 = (t42 - 1);
+ t44 = (t0 + 20224U);
+ t45 = *((char **)t44);
+ t46 = *((int *)t45);
+ t44 = (t0 + 47497);
+ t47 = *((int *)t44);
+ t48 = (t47 - 1);
+ t49 = (t46 * t48);
+ t50 = (t49 - t43);
+ t51 = (t50 * -1);
+ t51 = (t51 + 1);
+ t52 = (1U * t51);
+ t55 = (char *)alloca(t52);
+ memcpy(t55, t31, t52);
+ t60 = (t0 + 20224U);
+ t61 = *((char **)t60);
+ t56 = *((int *)t61);
+ t60 = (t0 + 47497);
+ t57 = *((int *)t60);
+ t58 = (t56 * t57);
+ t59 = (t58 - 1);
+ t66 = (t0 + 20224U);
+ t67 = *((char **)t66);
+ t62 = *((int *)t67);
+ t66 = (t0 + 47497);
+ t63 = *((int *)t66);
+ t64 = (t63 - 1);
+ t65 = (t62 * t64);
+ t70 = (t13 + 0U);
+ t71 = (t70 + 0U);
+ *((int *)t71) = t59;
+ t71 = (t70 + 4U);
+ *((int *)t71) = t65;
+ t71 = (t70 + 8U);
+ *((int *)t71) = -1;
+ t68 = (t65 - t59);
+ t69 = (t68 * -1);
+ t69 = (t69 + 1);
+ t71 = (t70 + 12U);
+ *((unsigned int *)t71) = t69;
+ t71 = (t0 + 20824U);
+ t72 = *((char **)t71);
+ t71 = (t72 + 0);
+ t73 = (t0 + 14928U);
+ t74 = *((char **)t73);
+ t5 = *((unsigned char *)t74);
+ t73 = (t0 + 5648U);
+ t75 = *((char **)t73);
+ t6 = *((unsigned char *)t75);
+ t76 = ((IEEE_P_2592010699) + 4024);
+ t73 = xsi_base_array_concat(t73, t26, t76, (char)99, t5, (char)99, t6, (char)101);
+ t78 = (t0 + 5808U);
+ t81 = *((char **)t78);
+ t7 = *((unsigned char *)t81);
+ t83 = ((IEEE_P_2592010699) + 4024);
+ t78 = xsi_base_array_concat(t78, t77, t83, (char)97, t73, t26, (char)99, t7, (char)101);
+ t69 = (1U + 1U);
+ t79 = (t69 + 1U);
+ t84 = (char *)alloca(t79);
+ memcpy(t84, t78, t79);
+ xilinxcorelib_a_4048593843_3212880686_sub_2129810750_3212880686(t0, t8, t9, t10, t55, t13, t71, t84);
+
+LAB66: t1 = (t0 + 47497);
+ t22 = *((int *)t1);
+ t2 = (t0 + 47501);
+ t23 = *((int *)t2);
+ if (t22 == t23)
+ goto LAB67;
+
+LAB68: t3 = (t22 + -1);
+ t22 = t3;
+ t4 = (t0 + 47497);
+ *((int *)t4) = t22;
+ goto LAB64;
+
+LAB69: t7 = (1 == 1);
+ if (t7 == 1)
+ goto LAB75;
+
+LAB76: t6 = (unsigned char)0;
+
+LAB77: if (t6 != 0)
+ goto LAB72;
+
+LAB74: t1 = (t0 + 21544U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = 8191;
+ t1 = (t0 + 21664U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = 8191;
+
+LAB73: goto LAB70;
+
+LAB72: t1 = (t0 + 20584U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (8191 - t3);
+ t1 = (t0 + 21544U);
+ t4 = *((char **)t1);
+ t1 = (t4 + 0);
+ *((int *)t1) = t22;
+ t1 = (t0 + 20584U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (8191 - t3);
+ t1 = (t0 + 21664U);
+ t4 = *((char **)t1);
+ t1 = (t4 + 0);
+ *((int *)t1) = t22;
+ goto LAB73;
+
+LAB75: t14 = (0 == 0);
+ t6 = t14;
+ goto LAB77;
+
+LAB78: t7 = (1 == 1);
+ if (t7 == 1)
+ goto LAB83;
+
+LAB84: t6 = (unsigned char)0;
+
+LAB85: if (t6 != 0)
+ goto LAB80;
+
+LAB82: t1 = (t0 + 21544U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = 8191;
+ t1 = (t0 + 21664U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = 8190;
+
+LAB81: goto LAB70;
+
+LAB80: t1 = (t0 + 20584U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (8191 - t3);
+ t1 = (t0 + 21544U);
+ t4 = *((char **)t1);
+ t1 = (t4 + 0);
+ *((int *)t1) = t22;
+ t1 = (t0 + 20584U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (8190 - t3);
+ t1 = (t0 + 21664U);
+ t4 = *((char **)t1);
+ t1 = (t4 + 0);
+ *((int *)t1) = t22;
+ goto LAB81;
+
+LAB83: t14 = (0 == 0);
+ t6 = t14;
+ goto LAB85;
+
+LAB86: t7 = (1 == 1);
+ if (t7 == 1)
+ goto LAB91;
+
+LAB92: t6 = (unsigned char)0;
+
+LAB93: if (t6 != 0)
+ goto LAB88;
+
+LAB90: t1 = (t0 + 5168U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46664U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 21544U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t3;
+ t1 = (t0 + 5168U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46664U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 21664U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t3;
+
+LAB89: goto LAB70;
+
+LAB88: t1 = (t0 + 5168U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46664U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 20584U);
+ t8 = *((char **)t4);
+ t22 = *((int *)t8);
+ t23 = (t3 - t22);
+ t4 = (t0 + 21544U);
+ t9 = *((char **)t4);
+ t4 = (t9 + 0);
+ *((int *)t4) = t23;
+ t1 = (t0 + 5168U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46664U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 20584U);
+ t8 = *((char **)t4);
+ t22 = *((int *)t8);
+ t23 = (t3 - t22);
+ t4 = (t0 + 21664U);
+ t9 = *((char **)t4);
+ t4 = (t9 + 0);
+ *((int *)t4) = t23;
+ goto LAB89;
+
+LAB91: t14 = (0 == 0);
+ t6 = t14;
+ goto LAB93;
+
+LAB94: t7 = (1 == 1);
+ if (t7 == 1)
+ goto LAB99;
+
+LAB100: t6 = (unsigned char)0;
+
+LAB101: if (t6 != 0)
+ goto LAB96;
+
+LAB98: t1 = (t0 + 5328U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46680U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 21544U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t3;
+ t1 = (t0 + 5488U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46696U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 21664U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t3;
+
+LAB97: goto LAB70;
+
+LAB96: t1 = (t0 + 5328U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46680U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 20584U);
+ t8 = *((char **)t4);
+ t22 = *((int *)t8);
+ t23 = (t3 - t22);
+ t4 = (t0 + 21544U);
+ t9 = *((char **)t4);
+ t4 = (t9 + 0);
+ *((int *)t4) = t23;
+ t1 = (t0 + 5488U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46696U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 20584U);
+ t8 = *((char **)t4);
+ t22 = *((int *)t8);
+ t23 = (t3 - t22);
+ t4 = (t0 + 21664U);
+ t9 = *((char **)t4);
+ t4 = (t9 + 0);
+ *((int *)t4) = t23;
+ goto LAB97;
+
+LAB99: t14 = (0 == 0);
+ t6 = t14;
+ goto LAB101;
+
+LAB102: t1 = (t0 + 31352);
+ t10 = (t1 + 56U);
+ t11 = *((char **)t10);
+ t12 = (t11 + 56U);
+ t20 = *((char **)t12);
+ *((unsigned char *)t20) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t21 = (t0 + 31352);
+ xsi_driver_intertial_reject(t21, 100LL, 100LL);
+ goto LAB103;
+
+LAB105: t1 = (t0 + 4528U);
+ t9 = *((char **)t1);
+ t7 = *((unsigned char *)t9);
+ t14 = (t7 == (unsigned char)3);
+ t5 = t14;
+ goto LAB107;
+
+LAB108: t1 = (t0 + 31352);
+ t9 = (t1 + 56U);
+ t10 = *((char **)t9);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ *((unsigned char *)t12) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t20 = (t0 + 31352);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+ goto LAB103;
+
+LAB110: t1 = (t0 + 31352);
+ t9 = (t1 + 56U);
+ t10 = *((char **)t9);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ *((unsigned char *)t12) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t20 = (t0 + 31352);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+ goto LAB103;
+
+LAB112: t1 = (t0 + 31480);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((unsigned char *)t10) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31480);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+ t1 = (t0 + 31544);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31544);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = (t0 + 31608);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((int *)t9) = 0;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31608);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = (t0 + 31672);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((int *)t9) = 0;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31672);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = xsi_get_transient_memory(14U);
+ memset(t1, 0, 14U);
+ t2 = t1;
+ memset(t2, (unsigned char)2, 14U);
+ t4 = (t0 + 31736);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ memcpy(t11, t1, 14U);
+ xsi_driver_first_trans_delta(t4, 0U, 14U, 100LL);
+ t12 = (t0 + 31736);
+ xsi_driver_intertial_reject(t12, 100LL, 100LL);
+ t1 = (t0 + 31800);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31800);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = (t0 + 31864);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31864);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t5 = (0 == 1);
+ if (t5 != 0)
+ goto LAB115;
+
+LAB117: t1 = (t0 + 21064U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 21064U);
+ t4 = *((char **)t1);
+ t1 = (t4 + 0);
+ memcpy(t1, t2, 8U);
+
+LAB116: t1 = xsi_get_transient_memory(2U);
+ memset(t1, 0, 2U);
+ t2 = t1;
+ memset(t2, (unsigned char)2, 2U);
+ t4 = (t0 + 21184U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ memcpy(t4, t1, 2U);
+ goto LAB113;
+
+LAB115: t1 = (t0 + 47505);
+ t4 = (t0 + 46584U);
+ t8 = xilinxcorelib_a_4048593843_3212880686_sub_3703097363_3212880686(t0, t13, t1, t4, 8);
+ t9 = (t0 + 21064U);
+ t10 = *((char **)t9);
+ t9 = (t10 + 0);
+ memcpy(t9, t8, 8U);
+ goto LAB116;
+
+LAB118: t2 = (t0 + 14448U);
+ t8 = *((char **)t2);
+ t15 = *((unsigned char *)t8);
+ t2 = (t0 + 31864);
+ t9 = (t2 + 56U);
+ t10 = *((char **)t9);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ *((unsigned char *)t12) = t15;
+ xsi_driver_first_trans_delta(t2, 0U, 1, 100LL);
+ t20 = (t0 + 31864);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+ t1 = (t0 + 8688U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 31672);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31672);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+ t5 = (0 == 0);
+ if (t5 != 0)
+ goto LAB123;
+
+LAB125: t1 = (t0 + 9328U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 / t22);
+ t24 = (t23 + 2);
+ t25 = (13 + 1);
+ t1 = ieee_p_3499444699_sub_2213602152_3499444699(IEEE_P_3499444699, t13, t24, t25);
+ t8 = (t0 + 31736);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ memcpy(t12, t1, 14U);
+ xsi_driver_first_trans_delta(t8, 0U, 14U, 100LL);
+ t20 = (t0 + 31736);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+
+LAB124: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 / t22);
+ t5 = (t23 == 0);
+ if (t5 != 0)
+ goto LAB126;
+
+LAB128: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 / t22);
+ t5 = (t23 == 1);
+ if (t5 != 0)
+ goto LAB129;
+
+LAB130: t1 = (t0 + 31480);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31480);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = (t0 + 31544);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31544);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+
+LAB127: t1 = (t0 + 4208U);
+ t2 = *((char **)t1);
+ t5 = *((unsigned char *)t2);
+ t6 = (t5 == (unsigned char)3);
+ if (t6 != 0)
+ goto LAB131;
+
+LAB133:
+LAB132: t5 = (0 == 1);
+ if (t5 != 0)
+ goto LAB159;
+
+LAB161: t5 = (0 == 2);
+ if (t5 != 0)
+ goto LAB168;
+
+LAB169: t5 = (0 == 3);
+ if (t5 != 0)
+ goto LAB176;
+
+LAB177: t5 = (0 == 4);
+ if (t5 != 0)
+ goto LAB184;
+
+LAB185:
+LAB160: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 / t22);
+ t1 = (t0 + 21304U);
+ t8 = *((char **)t1);
+ t24 = *((int *)t8);
+ t25 = (t24 + 1);
+ t6 = (t23 == t25);
+ if (t6 == 1)
+ goto LAB195;
+
+LAB196: t5 = (unsigned char)0;
+
+LAB197: if (t5 != 0)
+ goto LAB192;
+
+LAB194: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 / t22);
+ t1 = (t0 + 21304U);
+ t8 = *((char **)t1);
+ t24 = *((int *)t8);
+ t5 = (t23 <= t24);
+ if (t5 != 0)
+ goto LAB198;
+
+LAB199: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 / t22);
+ t1 = (t0 + 21424U);
+ t8 = *((char **)t1);
+ t24 = *((int *)t8);
+ t5 = (t23 > t24);
+ if (t5 != 0)
+ goto LAB200;
+
+LAB201:
+LAB193: goto LAB113;
+
+LAB120: t2 = (t0 + 4048U);
+ t4 = *((char **)t2);
+ t7 = *((unsigned char *)t4);
+ t14 = (t7 == (unsigned char)3);
+ t5 = t14;
+ goto LAB122;
+
+LAB123: t1 = (t0 + 9328U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 / t22);
+ t1 = ieee_p_3499444699_sub_2213602152_3499444699(IEEE_P_3499444699, t13, t23, 13);
+ t9 = ((IEEE_P_2592010699) + 4024);
+ t8 = xsi_base_array_concat(t8, t26, t9, (char)97, t1, t13, (char)99, (unsigned char)2, (char)101);
+ t10 = (t0 + 31736);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ t20 = (t12 + 56U);
+ t21 = *((char **)t20);
+ memcpy(t21, t8, 14U);
+ xsi_driver_first_trans_delta(t10, 0U, 14U, 100LL);
+ t27 = (t0 + 31736);
+ xsi_driver_intertial_reject(t27, 100LL, 100LL);
+ goto LAB124;
+
+LAB126: t1 = (t0 + 31480);
+ t8 = (t1 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ *((unsigned char *)t11) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t12 = (t0 + 31480);
+ xsi_driver_intertial_reject(t12, 100LL, 100LL);
+ t1 = (t0 + 31544);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31544);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ goto LAB127;
+
+LAB129: t1 = (t0 + 31480);
+ t8 = (t1 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ *((unsigned char *)t11) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t12 = (t0 + 31480);
+ xsi_driver_intertial_reject(t12, 100LL, 100LL);
+ t1 = (t0 + 31544);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31544);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ goto LAB127;
+
+LAB131: t1 = (t0 + 10128U);
+ t4 = *((char **)t1);
+ t7 = *((unsigned char *)t4);
+ t14 = (t7 != (unsigned char)3);
+ if (t14 != 0)
+ goto LAB134;
+
+LAB136:
+LAB135: goto LAB132;
+
+LAB134: t1 = (t0 + 20944U);
+ t8 = *((char **)t1);
+ t3 = *((int *)t8);
+ t1 = (t0 + 20344U);
+ t9 = *((char **)t1);
+ t22 = *((int *)t9);
+ t23 = (t3 / t22);
+ t15 = (t23 == 2);
+ if (t15 != 0)
+ goto LAB137;
+
+LAB139: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 / t22);
+ t5 = (t23 == 1);
+ if (t5 != 0)
+ goto LAB145;
+
+LAB146: t1 = (t0 + 20944U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 20344U);
+ t4 = *((char **)t1);
+ t22 = *((int *)t4);
+ t23 = (t3 / t22);
+ t5 = (t23 == 0);
+ if (t5 != 0)
+ goto LAB152;
+
+LAB153: t1 = (t0 + 20344U);
+ t8 = *((char **)t1);
+ t24 = *((int *)t8);
+ t1 = (t0 + 47522);
+ *((int *)t1) = t24;
+ t9 = (t0 + 47526);
+ *((int *)t9) = 1;
+ t25 = t24;
+ t28 = 1;
+
+LAB154: if (t25 >= t28)
+ goto LAB155;
+
+LAB157: t1 = (t0 + 8688U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (t3 + 1);
+ t23 = xsi_vhdl_mod(t22, 8192);
+ t1 = (t0 + 31608);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t23;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31608);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+
+LAB138: goto LAB135;
+
+LAB137: t1 = (t0 + 31544);
+ t10 = (t1 + 56U);
+ t11 = *((char **)t10);
+ t12 = (t11 + 56U);
+ t20 = *((char **)t12);
+ *((unsigned char *)t20) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t21 = (t0 + 31544);
+ xsi_driver_intertial_reject(t21, 100LL, 100LL);
+ t1 = (t0 + 20344U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 47506);
+ *((int *)t1) = t3;
+ t4 = (t0 + 47510);
+ *((int *)t4) = 1;
+ t22 = t3;
+ t23 = 1;
+
+LAB140: if (t22 >= t23)
+ goto LAB141;
+
+LAB143: t1 = (t0 + 8688U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (t3 + 1);
+ t23 = xsi_vhdl_mod(t22, 8192);
+ t1 = (t0 + 31608);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t23;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31608);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+ goto LAB138;
+
+LAB141: t8 = (t0 + 27952);
+ t9 = (t0 + 22136U);
+ t10 = (t0 + 21064U);
+ t11 = *((char **)t10);
+ t10 = (t0 + 20224U);
+ t12 = *((char **)t10);
+ t24 = *((int *)t12);
+ t10 = (t0 + 47506);
+ t25 = *((int *)t10);
+ t28 = (t24 * t25);
+ t29 = (t28 - 1);
+ t35 = (7 - t29);
+ t20 = (t0 + 20224U);
+ t21 = *((char **)t20);
+ t30 = *((int *)t21);
+ t20 = (t0 + 47506);
+ t32 = *((int *)t20);
+ t36 = (t32 - 1);
+ t37 = (t30 * t36);
+ xsi_vhdl_check_range_of_slice(7, 0, -1, t29, t37, -1);
+ t38 = (t35 * 1U);
+ t39 = (0 + t38);
+ t27 = (t11 + t39);
+ t31 = (t0 + 20224U);
+ t33 = *((char **)t31);
+ t40 = *((int *)t33);
+ t31 = (t0 + 47506);
+ t41 = *((int *)t31);
+ t42 = (t40 * t41);
+ t43 = (t42 - 1);
+ t34 = (t0 + 20224U);
+ t44 = *((char **)t34);
+ t46 = *((int *)t44);
+ t34 = (t0 + 47506);
+ t47 = *((int *)t34);
+ t48 = (t47 - 1);
+ t49 = (t46 * t48);
+ t45 = (t13 + 0U);
+ t60 = (t45 + 0U);
+ *((int *)t60) = t43;
+ t60 = (t45 + 4U);
+ *((int *)t60) = t49;
+ t60 = (t45 + 8U);
+ *((int *)t60) = -1;
+ t50 = (t49 - t43);
+ t51 = (t50 * -1);
+ t51 = (t51 + 1);
+ t60 = (t45 + 12U);
+ *((unsigned int *)t60) = t51;
+ t60 = (t0 + 21184U);
+ t61 = *((char **)t60);
+ xilinxcorelib_a_4048593843_3212880686_sub_2966016925_3212880686(t0, t8, t9, t27, t13, t61);
+ t1 = (t0 + 27952);
+ t2 = (t0 + 22064U);
+ t4 = (t0 + 22136U);
+ t8 = (t0 + 20824U);
+ t9 = *((char **)t8);
+ t8 = (t9 + 0);
+ xilinxcorelib_a_4048593843_3212880686_sub_2068494565_3212880686(t0, t1, t2, t4, t8);
+
+LAB142: t1 = (t0 + 47506);
+ t22 = *((int *)t1);
+ t2 = (t0 + 47510);
+ t23 = *((int *)t2);
+ if (t22 == t23)
+ goto LAB143;
+
+LAB144: t3 = (t22 + -1);
+ t22 = t3;
+ t4 = (t0 + 47506);
+ *((int *)t4) = t22;
+ goto LAB140;
+
+LAB145: t1 = (t0 + 31544);
+ t8 = (t1 + 56U);
+ t9 = *((char **)t8);
+ t10 = (t9 + 56U);
+ t11 = *((char **)t10);
+ *((unsigned char *)t11) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t12 = (t0 + 31544);
+ xsi_driver_intertial_reject(t12, 100LL, 100LL);
+ t1 = (t0 + 31480);
+ t2 = (t1 + 56U);
+ t4 = *((char **)t2);
+ t8 = (t4 + 56U);
+ t9 = *((char **)t8);
+ *((unsigned char *)t9) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t10 = (t0 + 31480);
+ xsi_driver_intertial_reject(t10, 100LL, 100LL);
+ t1 = (t0 + 20344U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t1 = (t0 + 47514);
+ *((int *)t1) = t3;
+ t4 = (t0 + 47518);
+ *((int *)t4) = 1;
+ t22 = t3;
+ t23 = 1;
+
+LAB147: if (t22 >= t23)
+ goto LAB148;
+
+LAB150: t1 = (t0 + 8688U);
+ t2 = *((char **)t1);
+ t3 = *((int *)t2);
+ t22 = (t3 + 1);
+ t23 = xsi_vhdl_mod(t22, 8192);
+ t1 = (t0 + 31608);
+ t4 = (t1 + 56U);
+ t8 = *((char **)t4);
+ t9 = (t8 + 56U);
+ t10 = *((char **)t9);
+ *((int *)t10) = t23;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t11 = (t0 + 31608);
+ xsi_driver_intertial_reject(t11, 100LL, 100LL);
+ goto LAB138;
+
+LAB148: t8 = (t0 + 27952);
+ t9 = (t0 + 22136U);
+ t10 = (t0 + 21064U);
+ t11 = *((char **)t10);
+ t10 = (t0 + 20224U);
+ t12 = *((char **)t10);
+ t24 = *((int *)t12);
+ t10 = (t0 + 47514);
+ t25 = *((int *)t10);
+ t28 = (t24 * t25);
+ t29 = (t28 - 1);
+ t35 = (7 - t29);
+ t20 = (t0 + 20224U);
+ t21 = *((char **)t20);
+ t30 = *((int *)t21);
+ t20 = (t0 + 47514);
+ t32 = *((int *)t20);
+ t36 = (t32 - 1);
+ t37 = (t30 * t36);
+ xsi_vhdl_check_range_of_slice(7, 0, -1, t29, t37, -1);
+ t38 = (t35 * 1U);
+ t39 = (0 + t38);
+ t27 = (t11 + t39);
+ t31 = (t0 + 20224U);
+ t33 = *((char **)t31);
+ t40 = *((int *)t33);
+ t31 = (t0 + 47514);
+ t41 = *((int *)t31);
+ t42 = (t40 * t41);
+ t43 = (t42 - 1);
+ t34 = (t0 + 20224U);
+ t44 = *((char **)t34);
+ t46 = *((int *)t44);
+ t34 = (t0 + 47514);
+ t47 = *((int *)t34);
+ t48 = (t47 - 1);
+ t49 = (t46 * t48);
+ t45 = (t13 + 0U);
+ t60 = (t45 + 0U);
+ *((int *)t60) = t43;
+ t60 = (t45 + 4U);
+ *((int *)t60) = t49;
+ t60 = (t45 + 8U);
+ *((int *)t60) = -1;
+ t50 = (t49 - t43);
+ t51 = (t50 * -1);
+ t51 = (t51 + 1);
+ t60 = (t45 + 12U);
+ *((unsigned int *)t60) = t51;
+ t60 = (t0 + 21184U);
+ t61 = *((char **)t60);
+ xilinxcorelib_a_4048593843_3212880686_sub_2966016925_3212880686(t0, t8, t9, t27, t13, t61);
+ t1 = (t0 + 27952);
+ t2 = (t0 + 22064U);
+ t4 = (t0 + 22136U);
+ t8 = (t0 + 20824U);
+ t9 = *((char **)t8);
+ t8 = (t9 + 0);
+ xilinxcorelib_a_4048593843_3212880686_sub_2068494565_3212880686(t0, t1, t2, t4, t8);
+
+LAB149: t1 = (t0 + 47514);
+ t22 = *((int *)t1);
+ t2 = (t0 + 47518);
+ t23 = *((int *)t2);
+ if (t22 == t23)
+ goto LAB150;
+
+LAB151: t3 = (t22 + -1);
+ t22 = t3;
+ t4 = (t0 + 47514);
+ *((int *)t4) = t22;
+ goto LAB147;
+
+LAB152: goto LAB138;
+
+LAB155: t10 = (t0 + 27952);
+ t11 = (t0 + 22136U);
+ t12 = (t0 + 21064U);
+ t20 = *((char **)t12);
+ t12 = (t0 + 20224U);
+ t21 = *((char **)t12);
+ t29 = *((int *)t21);
+ t12 = (t0 + 47522);
+ t30 = *((int *)t12);
+ t32 = (t29 * t30);
+ t36 = (t32 - 1);
+ t35 = (7 - t36);
+ t27 = (t0 + 20224U);
+ t31 = *((char **)t27);
+ t37 = *((int *)t31);
+ t27 = (t0 + 47522);
+ t40 = *((int *)t27);
+ t41 = (t40 - 1);
+ t42 = (t37 * t41);
+ xsi_vhdl_check_range_of_slice(7, 0, -1, t36, t42, -1);
+ t38 = (t35 * 1U);
+ t39 = (0 + t38);
+ t33 = (t20 + t39);
+ t34 = (t0 + 20224U);
+ t44 = *((char **)t34);
+ t43 = *((int *)t44);
+ t34 = (t0 + 47522);
+ t46 = *((int *)t34);
+ t47 = (t43 * t46);
+ t48 = (t47 - 1);
+ t45 = (t0 + 20224U);
+ t60 = *((char **)t45);
+ t49 = *((int *)t60);
+ t45 = (t0 + 47522);
+ t50 = *((int *)t45);
+ t56 = (t50 - 1);
+ t57 = (t49 * t56);
+ t61 = (t13 + 0U);
+ t66 = (t61 + 0U);
+ *((int *)t66) = t48;
+ t66 = (t61 + 4U);
+ *((int *)t66) = t57;
+ t66 = (t61 + 8U);
+ *((int *)t66) = -1;
+ t58 = (t57 - t48);
+ t51 = (t58 * -1);
+ t51 = (t51 + 1);
+ t66 = (t61 + 12U);
+ *((unsigned int *)t66) = t51;
+ t66 = (t0 + 21184U);
+ t67 = *((char **)t66);
+ xilinxcorelib_a_4048593843_3212880686_sub_2966016925_3212880686(t0, t10, t11, t33, t13, t67);
+ t1 = (t0 + 27952);
+ t2 = (t0 + 22064U);
+ t4 = (t0 + 22136U);
+ t8 = (t0 + 20824U);
+ t9 = *((char **)t8);
+ t8 = (t9 + 0);
+ xilinxcorelib_a_4048593843_3212880686_sub_2068494565_3212880686(t0, t1, t2, t4, t8);
+
+LAB156: t1 = (t0 + 47522);
+ t25 = *((int *)t1);
+ t2 = (t0 + 47526);
+ t28 = *((int *)t2);
+ if (t25 == t28)
+ goto LAB157;
+
+LAB158: t3 = (t25 + -1);
+ t25 = t3;
+ t4 = (t0 + 47522);
+ *((int *)t4) = t25;
+ goto LAB154;
+
+LAB159: t7 = (1 == 1);
+ if (t7 == 1)
+ goto LAB165;
+
+LAB166: t6 = (unsigned char)0;
+
+LAB167: if (t6 != 0)
+ goto LAB162;
+
+LAB164: t1 = (t0 + 21304U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = 4;
+ t1 = (t0 + 21424U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = 4;
+
+LAB163: goto LAB160;
+
+LAB162: t3 = (4 - 2);
+ t1 = (t0 + 21304U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = t3;
+ t3 = (4 - 2);
+ t1 = (t0 + 21424U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = t3;
+ goto LAB163;
+
+LAB165: t14 = (0 == 0);
+ t6 = t14;
+ goto LAB167;
+
+LAB168: t7 = (1 == 1);
+ if (t7 == 1)
+ goto LAB173;
+
+LAB174: t6 = (unsigned char)0;
+
+LAB175: if (t6 != 0)
+ goto LAB170;
+
+LAB172: t1 = (t0 + 21304U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = 4;
+ t1 = (t0 + 21424U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = 5;
+
+LAB171: goto LAB160;
+
+LAB170: t3 = (4 - 2);
+ t1 = (t0 + 21304U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = t3;
+ t3 = (5 - 2);
+ t1 = (t0 + 21424U);
+ t2 = *((char **)t1);
+ t1 = (t2 + 0);
+ *((int *)t1) = t3;
+ goto LAB171;
+
+LAB173: t14 = (0 == 0);
+ t6 = t14;
+ goto LAB175;
+
+LAB176: t7 = (1 == 1);
+ if (t7 == 1)
+ goto LAB181;
+
+LAB182: t6 = (unsigned char)0;
+
+LAB183: if (t6 != 0)
+ goto LAB178;
+
+LAB180: t1 = (t0 + 4688U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46616U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 21304U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t3;
+ t1 = (t0 + 4688U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46616U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 21424U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t3;
+
+LAB179: goto LAB160;
+
+LAB178: t1 = (t0 + 4688U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46616U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t22 = (t3 - 2);
+ t4 = (t0 + 21304U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t22;
+ t1 = (t0 + 4688U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46616U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t22 = (t3 - 2);
+ t4 = (t0 + 21424U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t22;
+ goto LAB179;
+
+LAB181: t14 = (0 == 0);
+ t6 = t14;
+ goto LAB183;
+
+LAB184: t7 = (1 == 1);
+ if (t7 == 1)
+ goto LAB189;
+
+LAB190: t6 = (unsigned char)0;
+
+LAB191: if (t6 != 0)
+ goto LAB186;
+
+LAB188: t1 = (t0 + 4848U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46632U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 21304U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t3;
+ t1 = (t0 + 5008U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46648U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t4 = (t0 + 21424U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t3;
+
+LAB187: goto LAB160;
+
+LAB186: t1 = (t0 + 4848U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46632U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t22 = (t3 - 2);
+ t4 = (t0 + 21304U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t22;
+ t1 = (t0 + 5008U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 46648U);
+ t3 = ieee_p_3620187407_sub_514432868_3620187407(IEEE_P_3620187407, t2, t1);
+ t22 = (t3 - 2);
+ t4 = (t0 + 21424U);
+ t8 = *((char **)t4);
+ t4 = (t8 + 0);
+ *((int *)t4) = t22;
+ goto LAB187;
+
+LAB189: t14 = (0 == 0);
+ t6 = t14;
+ goto LAB191;
+
+LAB192: t1 = (t0 + 31800);
+ t10 = (t1 + 56U);
+ t11 = *((char **)t10);
+ t12 = (t11 + 56U);
+ t20 = *((char **)t12);
+ *((unsigned char *)t20) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t21 = (t0 + 31800);
+ xsi_driver_intertial_reject(t21, 100LL, 100LL);
+ goto LAB193;
+
+LAB195: t1 = (t0 + 4208U);
+ t9 = *((char **)t1);
+ t7 = *((unsigned char *)t9);
+ t14 = (t7 == (unsigned char)3);
+ t5 = t14;
+ goto LAB197;
+
+LAB198: t1 = (t0 + 31800);
+ t9 = (t1 + 56U);
+ t10 = *((char **)t9);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ *((unsigned char *)t12) = (unsigned char)3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t20 = (t0 + 31800);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+ goto LAB193;
+
+LAB200: t1 = (t0 + 31800);
+ t9 = (t1 + 56U);
+ t10 = *((char **)t9);
+ t11 = (t10 + 56U);
+ t12 = *((char **)t11);
+ *((unsigned char *)t12) = (unsigned char)2;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t20 = (t0 + 31800);
+ xsi_driver_intertial_reject(t20, 100LL, 100LL);
+ goto LAB193;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_22(char *t0)
+{
+ char *t1;
+ char *t2;
+ char *t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+
+LAB0:
+LAB3: t1 = (t0 + 14768U);
+ t2 = *((char **)t1);
+ t1 = (t0 + 32120);
+ t3 = (t1 + 56U);
+ t4 = *((char **)t3);
+ t5 = (t4 + 56U);
+ t6 = *((char **)t5);
+ memcpy(t6, t2, 8U);
+ xsi_driver_first_trans_fast_port(t1);
+
+LAB2: t7 = (t0 + 29512);
+ *((int *)t7) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_23(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+
+LAB0:
+LAB3: t1 = (t0 + 15088U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 32184);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t8 = (t0 + 32184);
+ xsi_driver_intertial_reject(t8, 100LL, 100LL);
+
+LAB2: t9 = (t0 + 29528);
+ *((int *)t9) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+static void xilinxcorelib_a_4048593843_3212880686_p_24(char *t0)
+{
+ char *t1;
+ char *t2;
+ unsigned char t3;
+ char *t4;
+ char *t5;
+ char *t6;
+ char *t7;
+ char *t8;
+ char *t9;
+
+LAB0:
+LAB3: t1 = (t0 + 15248U);
+ t2 = *((char **)t1);
+ t3 = *((unsigned char *)t2);
+ t1 = (t0 + 32248);
+ t4 = (t1 + 56U);
+ t5 = *((char **)t4);
+ t6 = (t5 + 56U);
+ t7 = *((char **)t6);
+ *((unsigned char *)t7) = t3;
+ xsi_driver_first_trans_delta(t1, 0U, 1, 100LL);
+ t8 = (t0 + 32248);
+ xsi_driver_intertial_reject(t8, 100LL, 100LL);
+
+LAB2: t9 = (t0 + 29544);
+ *((int *)t9) = 1;
+
+LAB1: return;
+LAB4: goto LAB2;
+
+}
+
+
+extern void xilinxcorelib_a_4048593843_3212880686_init()
+{
+ static char *pe[] = {(void *)xilinxcorelib_a_4048593843_3212880686_p_0,(void *)xilinxcorelib_a_4048593843_3212880686_p_1,(void *)xilinxcorelib_a_4048593843_3212880686_p_2,(void *)xilinxcorelib_a_4048593843_3212880686_p_3,(void *)xilinxcorelib_a_4048593843_3212880686_p_4,(void *)xilinxcorelib_a_4048593843_3212880686_p_5,(void *)xilinxcorelib_a_4048593843_3212880686_p_6,(void *)xilinxcorelib_a_4048593843_3212880686_p_7,(void *)xilinxcorelib_a_4048593843_3212880686_p_8,(void *)xilinxcorelib_a_4048593843_3212880686_p_9,(void *)xilinxcorelib_a_4048593843_3212880686_p_10,(void *)xilinxcorelib_a_4048593843_3212880686_p_11,(void *)xilinxcorelib_a_4048593843_3212880686_p_12,(void *)xilinxcorelib_a_4048593843_3212880686_p_13,(void *)xilinxcorelib_a_4048593843_3212880686_p_14,(void *)xilinxcorelib_a_4048593843_3212880686_p_15,(void *)xilinxcorelib_a_4048593843_3212880686_p_16,(void *)xilinxcorelib_a_4048593843_3212880686_p_17,(void *)xilinxcorelib_a_4048593843_3212880686_p_18,(void *)xilinxcorelib_a_4048593843_3212880686_p_19,(void *)xilinxcorelib_a_4048593843_3212880686_p_20,(void *)xilinxcorelib_a_4048593843_3212880686_p_21,(void *)xilinxcorelib_a_4048593843_3212880686_p_22,(void *)xilinxcorelib_a_4048593843_3212880686_p_23,(void *)xilinxcorelib_a_4048593843_3212880686_p_24};
+ static char *se[] = {(void *)xilinxcorelib_a_4048593843_3212880686_sub_1842417276_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_1315575287_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_2978940197_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_3672023036_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_3703097363_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_2234054365_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_1807611230_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_2129810750_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_2966016925_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_2068494565_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_3751606365_3212880686,(void *)xilinxcorelib_a_4048593843_3212880686_sub_4190946951_3212880686};
+ xsi_register_didat("xilinxcorelib_a_4048593843_3212880686", "isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.didat");
+ xsi_register_executes(pe);
+ xsi_register_subprogram_executes(se);
+}
diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.didat b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.didat
new file mode 100755
index 0000000000000000000000000000000000000000..3761deab3b70efb5cbb71e493a480bbf8bbc496f
GIT binary patch
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diff --git a/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.nt64.obj b/ipcore_dir/isim/fifo_usb_if_isim_beh.exe.sim/xilinxcorelib/a_4048593843_3212880686.nt64.obj
new file mode 100755
index 0000000000000000000000000000000000000000..c5a321a061df30dde47ce0244df9510238bcef82
GIT binary patch
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+
+<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>194</xtag-isim-property-value></TD></TR>
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+<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
+<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.0624 sec, 472461 KB</xtag-isim-property-value></TD></TR>
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+<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
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new file mode 100755
index 0000000000000000000000000000000000000000..0fd53f51107e5035b82c6b2c49893168e4da27e0
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new file mode 100755
index 0000000000000000000000000000000000000000..c0acd525ea08a8c18a422d52df1b4e05b5aad74e
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diff --git a/ipcore_dir/isim/precompiled.exe.sim/ieee/p_3620187407.didat b/ipcore_dir/isim/precompiled.exe.sim/ieee/p_3620187407.didat
new file mode 100755
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diff --git a/ipcore_dir/isim/precompiled.exe.sim/ieee/p_3972351953.didat b/ipcore_dir/isim/precompiled.exe.sim/ieee/p_3972351953.didat
new file mode 100755
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diff --git a/ipcore_dir/isim/precompiled.exe.sim/ieee/p_4165608084.didat b/ipcore_dir/isim/precompiled.exe.sim/ieee/p_4165608084.didat
new file mode 100755
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GIT binary patch
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diff --git a/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs b/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs
new file mode 100644
index 0000000..f84336a
--- /dev/null
+++ b/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+</messages>
+
diff --git a/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs b/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
new file mode 100644
index 0000000..0fd9d6a
--- /dev/null
+++ b/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated -->
+<!-- by the Xilinx ISE software. Any direct editing or -->
+<!-- changes made to this file may result in unpredictable -->
+<!-- behavior or data corruption. It is strongly advised that -->
+<!-- users do not edit the contents of this file. -->
+<!-- -->
+<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/horacio/Dropbox/work_private/lago/lago-fpga-sync_vhdl/ipcore_dir/tmp/_cg/fifo.vhd" into library work</arg>
+</msg>
+
+</messages>
+
diff --git a/ipcore_dir/tmp/_xmsgs/xst.xmsgs b/ipcore_dir/tmp/_xmsgs/xst.xmsgs
new file mode 100644
index 0000000..0d2735a
--- /dev/null
+++ b/ipcore_dir/tmp/_xmsgs/xst.xmsgs
@@ -0,0 +1,2274 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="UtilitiesC" num="159" delta="new" >Message file "<arg fmt="%s" index="1">usenglish/ip.msg</arg>" wasn't found.
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">1</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">1</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">4</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">5</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">6</arg>: (<arg fmt="%d" index="2">3</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">7</arg>: (<arg fmt="%d" index="2">3</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">8</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">9</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">10</arg>: (<arg fmt="%d" index="2">5</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">11</arg>: (<arg fmt="%d" index="2">5</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">12</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">13</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">14</arg>: (<arg fmt="%d" index="2">7</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">15</arg>: (<arg fmt="%d" index="2">7</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">1</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">1</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">4</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">5</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">6</arg>: (<arg fmt="%d" index="2">3</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">7</arg>: (<arg fmt="%d" index="2">3</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">8</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">9</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">10</arg>: (<arg fmt="%d" index="2">5</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">11</arg>: (<arg fmt="%d" index="2">5</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">12</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">13</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">14</arg>: (<arg fmt="%d" index="2">7</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">15</arg>: (<arg fmt="%d" index="2">7</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_input_block.vhd</arg>" line <arg fmt="%d" index="2">88</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_input_block.vhd</arg>" line <arg fmt="%d" index="2">88</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%d" index="2">780</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/fifo_generator_v6_2/ramfifo/fifo_generator_ramfifo.vhd</arg>" line <arg fmt="%d" index="2">358</arg>: Unconnected output port '<arg fmt="%s" index="3">INT_CLK_I</arg>' of component '<arg fmt="%s" index="4">input_blk</arg>'.
+</msg>
+
+<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/fifo_generator_v6_2/ramfifo/memory.vhd</arg>" line <arg fmt="%d" index="2">470</arg>: Unconnected output port '<arg fmt="%s" index="3">DOUTA</arg>' of component '<arg fmt="%s" index="4">blk_mem_gen_v4_2_xst</arg>'.
+</msg>
+
+<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/fifo_generator_v6_2/ramfifo/memory.vhd</arg>" line <arg fmt="%d" index="2">470</arg>: Unconnected output port '<arg fmt="%s" index="3">RDADDRECC</arg>' of component '<arg fmt="%s" index="4">blk_mem_gen_v4_2_xst</arg>'.
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">1</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
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+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">1</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
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+
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+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
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+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">2</arg>: (<arg fmt="%d" index="2">1</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">3</arg>: (<arg fmt="%d" index="2">1</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">4</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">5</arg>: (<arg fmt="%d" index="2">2</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">6</arg>: (<arg fmt="%d" index="2">3</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">7</arg>: (<arg fmt="%d" index="2">3</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">8</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">9</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">10</arg>: (<arg fmt="%d" index="2">5</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">11</arg>: (<arg fmt="%d" index="2">5</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">12</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">13</arg>: (<arg fmt="%d" index="2">6</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">14</arg>: (<arg fmt="%d" index="2">7</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">15</arg>: (<arg fmt="%d" index="2">7</arg>,<arg fmt="%d" index="3">16384</arg>) : <arg fmt="%d" index="4">1</arg>x<arg fmt="%d" index="5">16384</arg> u:<arg fmt="%d" index="6">1</arg>
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_input_block.vhd</arg>" line <arg fmt="%d" index="2">691</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_input_block.vhd</arg>" line <arg fmt="%d" index="2">707</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%d" index="2">1539</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%d" index="2">1552</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="752" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%d" index="2">1599</arg>: Unconnected input port '<arg fmt="%s" index="3">ADDR_IN</arg>' of component '<arg fmt="%s" index="4">blk_mem_gen_mux</arg>' is tied to default value.
+</msg>
+
+<msg type="warning" file="Xst" num="752" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%d" index="2">1599</arg>: Unconnected input port '<arg fmt="%s" index="3">SBITERRIN</arg>' of component '<arg fmt="%s" index="4">blk_mem_gen_mux</arg>' is tied to default value.
+</msg>
+
+<msg type="warning" file="Xst" num="752" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%d" index="2">1599</arg>: Unconnected input port '<arg fmt="%s" index="3">DBITERRIN</arg>' of component '<arg fmt="%s" index="4">blk_mem_gen_mux</arg>' is tied to default value.
+</msg>
+
+<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%d" index="2">1599</arg>: Unconnected output port '<arg fmt="%s" index="3">SBITERR</arg>' of component '<arg fmt="%s" index="4">blk_mem_gen_mux</arg>'.
+</msg>
+
+<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%d" index="2">1599</arg>: Unconnected output port '<arg fmt="%s" index="3">DBITERR</arg>' of component '<arg fmt="%s" index="4">blk_mem_gen_mux</arg>'.
+</msg>
+
+<msg type="warning" file="Xst" num="753" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_generic_cstr.vhd</arg>" line <arg fmt="%d" index="2">1599</arg>: Unconnected output port '<arg fmt="%s" index="3">RDADDRECC</arg>' of component '<arg fmt="%s" index="4">blk_mem_gen_mux</arg>'.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">976</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addra_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="2096" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_prim_width.vhd</arg>" line <arg fmt="%d" index="2">977</arg>: Use of null array slice on signal <<arg fmt="%s" index="3">addrb_pad</arg>> is not supported.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_mux.vhd</arg>" line <arg fmt="%d" index="2">470</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_mux.vhd</arg>" line <arg fmt="%d" index="2">472</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_mux.vhd</arg>" line <arg fmt="%d" index="2">872</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="info" file="Xst" num="2679" delta="new" >Register <<arg fmt="%s" index="1">rdaddrecc_lat</arg>> in unit <<arg fmt="%s" index="2">blk_mem_gen_mux.1</arg>> has a constant value of <arg fmt="%s" index="3">000000000000000</arg> during circuit operation. The register is replaced by logic.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_mux.vhd</arg>" line <arg fmt="%d" index="2">470</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_mux.vhd</arg>" line <arg fmt="%d" index="2">472</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="warning" file="Xst" num="795" delta="new" >"<arg fmt="%s" index="1">/home/horacio/work/lago/lago-fpga-sync_vhdl/ipcore_dir/./tmp/_cg/_bbx/blk_mem_gen_v4_2/blk_mem_gen_mux.vhd</arg>" line <arg fmt="%d" index="2">872</arg>: Size of operands are different : result is <false>.
+</msg>
+
+<msg type="info" file="Xst" num="2679" delta="new" >Register <<arg fmt="%s" index="1">rdaddrecc_lat</arg>> in unit <<arg fmt="%s" index="2">blk_mem_gen_mux.2</arg>> has a constant value of <arg fmt="%s" index="3">000000000000000</arg> during circuit operation. The register is replaced by logic.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">RD_RST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">WR_RST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">SRST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_EMPTY_THRESH_ASSERT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">CLK</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_FULL_THRESH_NEGATE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_FULL_THRESH_ASSERT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INT_CLK</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_FULL_THRESH</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_EMPTY_THRESH_NEGATE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_EMPTY_THRESH</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">WR_ACK_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">ALMOST_EMPTY_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">DATA_COUNT_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">SBITERR_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">UNDERFLOW_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">WR_DATA_COUNT_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_EMPTY_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">OVERFLOW_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">ALMOST_FULL_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">VALID_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">RD_DATA_COUNT_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">DBITERR_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">INJECTSBITERR_I</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">RSTA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">WEB<0></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">DINB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">INJECTDBITERR_I</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">RDADDRECC_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">DOUTA_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">SBITERR_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">CLKB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">RDADDRECC</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">DBITERR_I</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">ERROR_INTERNAL</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">DECODER_DOUTB</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">DECODER_DOUTA</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MEM_LAT_RST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">ADDR_IN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">DBITERRIN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MEM_REGCE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">WE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MEM_REG_RST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MUX_REGCE<0></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MUX_RST<0></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">SBITERRIN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">rdaddrecc_lat</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MEM_LAT_RST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">ADDR_IN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">DBITERRIN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MEM_REGCE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">WE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MEM_REG_RST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MUX_REGCE<0></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">MUX_RST<0></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">SBITERRIN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">rdaddrecc_lat</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_FULL_THRESH_NEGATE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_FULL_THRESH_ASSERT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">RD_PNTR_WR<1:0></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_FULL_THRESH</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">wr_rst_d1</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">diff_pntr_pad<0></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEA</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">REGCEB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_b</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_doutp_a</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_b<31:1></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">pad_dout_a<31:4></arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_b</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a4</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_dinp_a</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_b<31:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a32</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">pad_din_a<31:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_b9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">pad_addr_a9</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_b<35:1></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">full_dout_a<35:4></arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">full_din_a72</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">RAM_ALMOST_EMPTY</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">RD_PNTR_PLUS2</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">WR_PNTR_PLUS3</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">RD_PNTR_WR<1:0></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">WR_RST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">ram_almost_full_i</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">1</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_EMPTY_THRESH_ASSERT</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DATA_COUNT</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">RAM_REGOUT_EN</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">ALMOST_FULL_FB</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_EMPTY_THRESH_NEGATE</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">PROG_EMPTY_THRESH</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">RAM_WR_EN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">valid_fwft_dc</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">valid_fwft</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_almost_empty</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">SRST_FULL_FF</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">RAM_RD_EN</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">wr_ack_i</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_afull_i</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">ram_afull_fb</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">overflow_i</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">DBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTDBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">SBITERR</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1305" delta="new" >Output <<arg fmt="%s" index="1">RDADDRECC</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INJECTSBITERR</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">sbiterr_sdp</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">sbiterr_array</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">rst_enb</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">rst_ena</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">rdaddrecc_reg</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">rdaddrecc_out</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">rdaddrecc_lat</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">rdaddrecc_last</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr9</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr8</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr7</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr6</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr5</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr4</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr3</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr2</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr14</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr13</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr12</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr11</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr10</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr1</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr0</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_sbiterr</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr9</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr8</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr7</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr6</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr5</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr4</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr3</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr2</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr14</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr13</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr12</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr11</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr10</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr1</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr0</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">ram_dbiterr</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">dbiterr_sdp</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">dbiterr_array</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0000000000000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">addrb_in</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">SRST</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">zero_din_width</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">00000000</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">tmp_ram_regout_en</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">tmp_ram_regce</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">sbiterr_i</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="653" delta="new" >Signal <<arg fmt="%s" index="1">ram_rd_en_d1</arg>> is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">0</arg>.
+</msg>
+
+<msg type="warning" file="Xst" num="646" delta="new" >Signal <<arg fmt="%s" index="1">dbiterr_i</arg>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">regce_i</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">memsrst_i</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">memrd_rst_i</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">BACKUP_MARKER</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">INT_CLK</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">BACKUP</arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">debug_wr_pntr_w</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">debug_wr_pntr_r</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">debug_wr_pntr_plus2_w</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">debug_wr_pntr_plus1_w</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">debug_rd_pntr_w</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">debug_rd_pntr_r</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">debug_rd_pntr_plus1_r</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">DEBUG_WR_PNTR</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">DEBUG_RD_PNTR</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">DEBUG_RAM_WR_EN</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">DEBUG_RAM_RD_EN</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">DEBUG_RAM_FULL</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="1780" delta="new" >Signal <<arg fmt="%s" index="1">DEBUG_RAM_EMPTY</arg>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_2</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_3</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_4</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_5</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_6</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_7</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_8</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_9</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_10</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_11</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">diff_pntr_pad_12</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">wr_pf_as</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">U0/grf.rf/gcx.clkx/rd_pntr_bin_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">fifo_fifo_generator_v6_2_xst_1</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">U0/grf.rf/gcx.clkx/rd_pntr_bin_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">fifo_fifo_generator_v6_2_xst_1</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">fifo_fifo_generator_v6_2_xst_1</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">fifo_fifo_generator_v6_2_xst_1</arg>>.
+</msg>
+
+<msg type="warning" file="Xst" num="2677" delta="new" >Node <<arg fmt="%s" index="1">U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/has_mux_a.A/sel_pipe_0</arg>> of sequential type is unconnected in block <<arg fmt="%s" index="2">fifo_fifo_generator_v6_2_xst_1</arg>>.
+</msg>
+
+<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
+</msg>
+
+</messages>
+
diff --git a/ipcore_dir/xaw2verilog.log b/ipcore_dir/xaw2verilog.log
new file mode 100755
index 0000000..d09c75c
--- /dev/null
+++ b/ipcore_dir/xaw2verilog.log
@@ -0,0 +1 @@
+xaw2verilog: Completed successfully
diff --git a/ipcore_dir/xaw2vhdl.log b/ipcore_dir/xaw2vhdl.log
new file mode 100755
index 0000000..2c5d2b8
--- /dev/null
+++ b/ipcore_dir/xaw2vhdl.log
@@ -0,0 +1 @@
+xaw2vhdl: Completed successfully
diff --git a/kcpsm3.vhd b/kcpsm3.vhd
new file mode 100644
index 0000000..e1e5804
--- /dev/null
+++ b/kcpsm3.vhd
@@ -0,0 +1,1901 @@
+-- PicoBlaze
+--
+-- Constant (K) Coded Programmable State Machine for Spartan-3 Devices.
+-- Also suitable for use with Virtex-II(PRO) and Virtex-4 devices.
+--
+-- Includes additional code for enhanced VHDL simulation.
+--
+-- Version : 1.30
+-- Version Date : 14th June 2004
+-- Reasons : Avoid issue caused when ENABLE INTERRUPT is used when interrupts are
+-- already enabled when an an interrupt input is applied.
+-- Improved design for faster ZERO and CARRY flag logic
+--
+--
+-- Previous Version : 1.20
+-- Version Date : 9th July 2003
+--
+-- Start of design entry : 19th May 2003
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+-- Instruction disassembly concept inspired by the work of Prof. Dr.-Ing. Bernhard Lang.
+-- University of Applied Sciences, Osnabrueck, Germany.
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2003. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Furthermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Format of this file.
+--
+-- This file contains the definition of KCPSM3 as one complete module with sections
+-- created using generate loops. This 'flat' approach has been adopted to decrease
+-- the time taken to load the module into simulators and the synthesis process.
+--
+-- The module defines the implementation of the logic using Xilinx primitives.
+-- These ensure predictable synthesis results and maximise the density of the implementation.
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- Standard IEEE libraries
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for KCPSM3
+--
+entity kcpsm3 is
+ Port ( address : out std_logic_vector(9 downto 0);
+ instruction : in std_logic_vector(17 downto 0);
+ port_id : out std_logic_vector(7 downto 0);
+ write_strobe : out std_logic;
+ out_port : out std_logic_vector(7 downto 0);
+ read_strobe : out std_logic;
+ in_port : in std_logic_vector(7 downto 0);
+ interrupt : in std_logic;
+ interrupt_ack : out std_logic;
+ reset : in std_logic;
+ clk : in std_logic);
+ end kcpsm3;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for KCPSM3
+--
+architecture low_level_definition of kcpsm3 is
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in KCPSM3
+--
+------------------------------------------------------------------------------------
+--
+-- Fundamental control and decode signals
+--
+signal t_state : std_logic;
+signal not_t_state : std_logic;
+signal internal_reset : std_logic;
+signal reset_delay : std_logic;
+signal move_group : std_logic;
+signal condition_met : std_logic;
+signal normal_count : std_logic;
+signal call_type : std_logic;
+signal push_or_pop_type : std_logic;
+signal valid_to_move : std_logic;
+--
+-- Flag signals
+--
+signal flag_type : std_logic;
+signal flag_write : std_logic;
+signal flag_enable : std_logic;
+signal zero_flag : std_logic;
+signal sel_shadow_zero : std_logic;
+signal low_zero : std_logic;
+signal high_zero : std_logic;
+signal low_zero_carry : std_logic;
+signal high_zero_carry : std_logic;
+signal zero_carry : std_logic;
+signal zero_fast_route : std_logic;
+signal low_parity : std_logic;
+signal high_parity : std_logic;
+signal parity_carry : std_logic;
+signal parity : std_logic;
+signal carry_flag : std_logic;
+signal sel_parity : std_logic;
+signal sel_arith_carry : std_logic;
+signal sel_shift_carry : std_logic;
+signal sel_shadow_carry : std_logic;
+signal sel_carry : std_logic_vector(3 downto 0);
+signal carry_fast_route : std_logic;
+--
+-- Interrupt signals
+--
+signal active_interrupt : std_logic;
+signal int_pulse : std_logic;
+signal clean_int : std_logic;
+signal shadow_carry : std_logic;
+signal shadow_zero : std_logic;
+signal int_enable : std_logic;
+signal int_update_enable : std_logic;
+signal int_enable_value : std_logic;
+signal interrupt_ack_internal : std_logic;
+--
+-- Program Counter signals
+--
+signal pc : std_logic_vector(9 downto 0);
+signal pc_vector : std_logic_vector(9 downto 0);
+signal pc_vector_carry : std_logic_vector(8 downto 0);
+signal inc_pc_vector : std_logic_vector(9 downto 0);
+signal pc_value : std_logic_vector(9 downto 0);
+signal pc_value_carry : std_logic_vector(8 downto 0);
+signal inc_pc_value : std_logic_vector(9 downto 0);
+signal pc_enable : std_logic;
+--
+-- Data Register signals
+--
+signal sx : std_logic_vector(7 downto 0);
+signal sy : std_logic_vector(7 downto 0);
+signal register_type : std_logic;
+signal register_write : std_logic;
+signal register_enable : std_logic;
+signal second_operand : std_logic_vector(7 downto 0);
+--
+-- Scratch Pad Memory signals
+--
+signal memory_data : std_logic_vector(7 downto 0);
+signal store_data : std_logic_vector(7 downto 0);
+signal memory_type : std_logic;
+signal memory_write : std_logic;
+signal memory_enable : std_logic;
+--
+-- Stack signals
+--
+signal stack_pop_data : std_logic_vector(9 downto 0);
+signal stack_ram_data : std_logic_vector(9 downto 0);
+signal stack_address : std_logic_vector(4 downto 0);
+signal half_stack_address : std_logic_vector(4 downto 0);
+signal stack_address_carry : std_logic_vector(3 downto 0);
+signal next_stack_address : std_logic_vector(4 downto 0);
+signal stack_write_enable : std_logic;
+signal not_active_interrupt : std_logic;
+--
+-- ALU signals
+--
+signal logical_result : std_logic_vector(7 downto 0);
+signal logical_value : std_logic_vector(7 downto 0);
+signal sel_logical : std_logic;
+signal shift_result : std_logic_vector(7 downto 0);
+signal shift_value : std_logic_vector(7 downto 0);
+signal sel_shift : std_logic;
+signal high_shift_in : std_logic;
+signal low_shift_in : std_logic;
+signal shift_in : std_logic;
+signal shift_carry : std_logic;
+signal shift_carry_value : std_logic;
+signal arith_result : std_logic_vector(7 downto 0);
+signal arith_value : std_logic_vector(7 downto 0);
+signal half_arith : std_logic_vector(7 downto 0);
+signal arith_internal_carry : std_logic_vector(7 downto 0);
+signal sel_arith_carry_in : std_logic;
+signal arith_carry_in : std_logic;
+signal invert_arith_carry : std_logic;
+signal arith_carry_out : std_logic;
+signal sel_arith : std_logic;
+signal arith_carry : std_logic;
+--
+-- ALU multiplexer signals
+--
+signal input_fetch_type : std_logic;
+signal sel_group : std_logic;
+signal alu_group : std_logic_vector(7 downto 0);
+signal input_group : std_logic_vector(7 downto 0);
+signal alu_result : std_logic_vector(7 downto 0);
+--
+-- read and write strobes
+--
+signal io_initial_decode : std_logic;
+signal write_active : std_logic;
+signal read_active : std_logic;
+--
+--
+------------------------------------------------------------------------------------
+--
+-- Attributes to define LUT contents during implementation for primitives not
+-- contained within generate loops. In each case the information is repeated
+-- in the generic map for functional simulation
+--
+attribute INIT : string;
+attribute INIT of t_state_lut : label is "1";
+attribute INIT of int_pulse_lut : label is "0080";
+attribute INIT of int_update_lut : label is "EAAA";
+attribute INIT of int_value_lut : label is "04";
+attribute INIT of move_group_lut : label is "7400";
+attribute INIT of condition_met_lut : label is "5A3C";
+attribute INIT of normal_count_lut : label is "2F";
+attribute INIT of call_type_lut : label is "1000";
+attribute INIT of push_pop_lut : label is "5400";
+attribute INIT of valid_move_lut : label is "D";
+attribute INIT of flag_type_lut : label is "41FC";
+attribute INIT of flag_enable_lut : label is "8";
+attribute INIT of low_zero_lut : label is "0001";
+attribute INIT of high_zero_lut : label is "0001";
+attribute INIT of sel_shadow_zero_lut : label is "3F";
+attribute INIT of low_parity_lut : label is "6996";
+attribute INIT of high_parity_lut : label is "6996";
+attribute INIT of sel_parity_lut : label is "F3FF";
+attribute INIT of sel_arith_carry_lut : label is "F3";
+attribute INIT of sel_shift_carry_lut : label is "C";
+attribute INIT of sel_shadow_carry_lut : label is "3";
+attribute INIT of register_type_lut : label is "0145";
+attribute INIT of register_enable_lut : label is "8";
+attribute INIT of memory_type_lut : label is "0400";
+attribute INIT of memory_enable_lut : label is "8000";
+attribute INIT of sel_logical_lut : label is "FFE2";
+attribute INIT of low_shift_in_lut : label is "E4";
+attribute INIT of high_shift_in_lut : label is "E4";
+attribute INIT of shift_carry_lut : label is "E4";
+attribute INIT of sel_arith_lut : label is "1F";
+attribute INIT of input_fetch_type_lut : label is "0002";
+attribute INIT of io_decode_lut : label is "0010";
+attribute INIT of write_active_lut : label is "4000";
+attribute INIT of read_active_lut : label is "0100";
+--
+------------------------------------------------------------------------------------
+--
+-- Start of KCPSM3 circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+--
+------------------------------------------------------------------------------------
+--
+-- Fundamental Control
+--
+-- Definition of T-state and internal reset
+--
+------------------------------------------------------------------------------------
+--
+ t_state_lut: LUT1
+ --synthesis translate_off
+ generic map (INIT => X"1")
+ --synthesis translate_on
+ port map( I0 => t_state,
+ O => not_t_state );
+
+ toggle_flop: FDR
+ port map ( D => not_t_state,
+ Q => t_state,
+ R => internal_reset,
+ C => clk);
+
+ reset_flop1: FDS
+ port map ( D => '0',
+ Q => reset_delay,
+ S => reset,
+ C => clk);
+
+ reset_flop2: FDS
+ port map ( D => reset_delay,
+ Q => internal_reset,
+ S => reset,
+ C => clk);
+--
+------------------------------------------------------------------------------------
+--
+-- Interrupt input logic, Interrupt enable and shadow Flags.
+--
+-- Captures interrupt input and enables the shadow flags.
+-- Decodes instructions which set and reset the interrupt enable flip-flop.
+--
+------------------------------------------------------------------------------------
+--
+
+ -- Interrupt capture
+
+ int_capture_flop: FDR
+ port map ( D => interrupt,
+ Q => clean_int,
+ R => internal_reset,
+ C => clk);
+
+ int_pulse_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0080")
+ --synthesis translate_on
+ port map( I0 => t_state,
+ I1 => clean_int,
+ I2 => int_enable,
+ I3 => active_interrupt,
+ O => int_pulse );
+
+ int_flop: FDR
+ port map ( D => int_pulse,
+ Q => active_interrupt,
+ R => internal_reset,
+ C => clk);
+
+ ack_flop: FD
+ port map ( D => active_interrupt,
+ Q => interrupt_ack_internal,
+ C => clk);
+
+ interrupt_ack <= interrupt_ack_internal;
+
+ -- Shadow flags
+
+ shadow_carry_flop: FDE
+ port map ( D => carry_flag,
+ Q => shadow_carry,
+ CE => active_interrupt,
+ C => clk);
+
+ shadow_zero_flop: FDE
+ port map ( D => zero_flag,
+ Q => shadow_zero,
+ CE => active_interrupt,
+ C => clk);
+
+ -- Decode instructions that set or reset interrupt enable
+
+ int_update_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"EAAA")
+ --synthesis translate_on
+ port map( I0 => active_interrupt,
+ I1 => instruction(15),
+ I2 => instruction(16),
+ I3 => instruction(17),
+ O => int_update_enable );
+
+ int_value_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"04")
+ --synthesis translate_on
+ port map( I0 => active_interrupt,
+ I1 => instruction(0),
+ I2 => interrupt_ack_internal,
+ O => int_enable_value );
+
+ int_enable_flop: FDRE
+ port map ( D => int_enable_value,
+ Q => int_enable,
+ CE => int_update_enable,
+ R => internal_reset,
+ C => clk);
+--
+------------------------------------------------------------------------------------
+--
+-- Decodes for the control of the program counter and CALL/RETURN stack
+--
+------------------------------------------------------------------------------------
+--
+ move_group_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"7400")
+ --synthesis translate_on
+ port map( I0 => instruction(14),
+ I1 => instruction(15),
+ I2 => instruction(16),
+ I3 => instruction(17),
+ O => move_group );
+
+ condition_met_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"5A3C")
+ --synthesis translate_on
+ port map( I0 => carry_flag,
+ I1 => zero_flag,
+ I2 => instruction(10),
+ I3 => instruction(11),
+ O => condition_met );
+
+ normal_count_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"2F")
+ --synthesis translate_on
+ port map( I0 => instruction(12),
+ I1 => condition_met,
+ I2 => move_group,
+ O => normal_count );
+
+ call_type_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"1000")
+ --synthesis translate_on
+ port map( I0 => instruction(14),
+ I1 => instruction(15),
+ I2 => instruction(16),
+ I3 => instruction(17),
+ O => call_type );
+
+ push_pop_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"5400")
+ --synthesis translate_on
+ port map( I0 => instruction(14),
+ I1 => instruction(15),
+ I2 => instruction(16),
+ I3 => instruction(17),
+ O => push_or_pop_type );
+
+ valid_move_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"D")
+ --synthesis translate_on
+ port map( I0 => instruction(12),
+ I1 => condition_met,
+ O => valid_to_move );
+--
+------------------------------------------------------------------------------------
+--
+-- The ZERO and CARRY Flags
+--
+------------------------------------------------------------------------------------
+--
+ -- Enable for flags
+
+ flag_type_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"41FC")
+ --synthesis translate_on
+ port map( I0 => instruction(14),
+ I1 => instruction(15),
+ I2 => instruction(16),
+ I3 => instruction(17),
+ O => flag_type );
+
+ flag_write_flop: FD
+ port map ( D => flag_type,
+ Q => flag_write,
+ C => clk);
+
+ flag_enable_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"8")
+ --synthesis translate_on
+ port map( I0 => t_state,
+ I1 => flag_write,
+ O => flag_enable );
+
+ -- Zero Flag
+
+ low_zero_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0001")
+ --synthesis translate_on
+ port map( I0 => alu_result(0),
+ I1 => alu_result(1),
+ I2 => alu_result(2),
+ I3 => alu_result(3),
+ O => low_zero );
+
+ high_zero_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0001")
+ --synthesis translate_on
+ port map( I0 => alu_result(4),
+ I1 => alu_result(5),
+ I2 => alu_result(6),
+ I3 => alu_result(7),
+ O => high_zero );
+
+ low_zero_muxcy: MUXCY
+ port map( DI => '0',
+ CI => '1',
+ S => low_zero,
+ O => low_zero_carry );
+
+ high_zero_cymux: MUXCY
+ port map( DI => '0',
+ CI => low_zero_carry,
+ S => high_zero,
+ O => high_zero_carry );
+
+ sel_shadow_zero_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"3F")
+ --synthesis translate_on
+ port map( I0 => shadow_zero,
+ I1 => instruction(16),
+ I2 => instruction(17),
+ O => sel_shadow_zero );
+
+ zero_cymux: MUXCY
+ port map( DI => shadow_zero,
+ CI => high_zero_carry,
+ S => sel_shadow_zero,
+ O => zero_carry );
+
+ zero_xor: XORCY
+ port map( LI => '0',
+ CI => zero_carry,
+ O => zero_fast_route);
+
+ zero_flag_flop: FDRE
+ port map ( D => zero_fast_route,
+ Q => zero_flag,
+ CE => flag_enable,
+ R => internal_reset,
+ C => clk);
+
+ -- Parity detection
+
+ low_parity_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"6996")
+ --synthesis translate_on
+ port map( I0 => logical_result(0),
+ I1 => logical_result(1),
+ I2 => logical_result(2),
+ I3 => logical_result(3),
+ O => low_parity );
+
+ high_parity_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"6996")
+ --synthesis translate_on
+ port map( I0 => logical_result(4),
+ I1 => logical_result(5),
+ I2 => logical_result(6),
+ I3 => logical_result(7),
+ O => high_parity );
+
+ parity_muxcy: MUXCY
+ port map( DI => '0',
+ CI => '1',
+ S => low_parity,
+ O => parity_carry );
+
+ parity_xor: XORCY
+ port map( LI => high_parity,
+ CI => parity_carry,
+ O => parity);
+
+ -- CARRY flag selection
+
+ sel_parity_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"F3FF")
+ --synthesis translate_on
+ port map( I0 => parity,
+ I1 => instruction(13),
+ I2 => instruction(15),
+ I3 => instruction(16),
+ O => sel_parity );
+
+ sel_arith_carry_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"F3")
+ --synthesis translate_on
+ port map( I0 => arith_carry,
+ I1 => instruction(16),
+ I2 => instruction(17),
+ O => sel_arith_carry );
+
+ sel_shift_carry_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"C")
+ --synthesis translate_on
+ port map( I0 => shift_carry,
+ I1 => instruction(15),
+ O => sel_shift_carry );
+
+ sel_shadow_carry_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"3")
+ --synthesis translate_on
+ port map( I0 => shadow_carry,
+ I1 => instruction(17),
+ O => sel_shadow_carry );
+
+ sel_shadow_muxcy: MUXCY
+ port map( DI => shadow_carry,
+ CI => '0',
+ S => sel_shadow_carry,
+ O => sel_carry(0) );
+
+ sel_shift_muxcy: MUXCY
+ port map( DI => shift_carry,
+ CI => sel_carry(0),
+ S => sel_shift_carry,
+ O => sel_carry(1) );
+
+ sel_arith_muxcy: MUXCY
+ port map( DI => arith_carry,
+ CI => sel_carry(1),
+ S => sel_arith_carry,
+ O => sel_carry(2) );
+
+ sel_parity_muxcy: MUXCY
+ port map( DI => parity,
+ CI => sel_carry(2),
+ S => sel_parity,
+ O => sel_carry(3) );
+
+ carry_xor: XORCY
+ port map( LI => '0',
+ CI => sel_carry(3),
+ O => carry_fast_route);
+
+ carry_flag_flop: FDRE
+ port map ( D => carry_fast_route,
+ Q => carry_flag,
+ CE => flag_enable,
+ R => internal_reset,
+ C => clk);
+--
+------------------------------------------------------------------------------------
+--
+-- The Program Counter
+--
+-- Definition of a 10-bit counter which can be loaded from two sources
+--
+------------------------------------------------------------------------------------
+--
+
+ invert_enable: INV -- Inverter should be implemented in the CE to flip flops
+ port map( I => t_state,
+ O => pc_enable);
+
+ pc_loop: for i in 0 to 9 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ --
+ attribute INIT : string;
+ attribute INIT of vector_select_mux : label is "E4";
+ attribute INIT of value_select_mux : label is "E4";
+ --
+ begin
+
+ vector_select_mux: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"E4")
+ --synthesis translate_on
+ port map( I0 => instruction(15),
+ I1 => instruction(i),
+ I2 => stack_pop_data(i),
+ O => pc_vector(i) );
+
+ value_select_mux: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"E4")
+ --synthesis translate_on
+ port map( I0 => normal_count,
+ I1 => inc_pc_vector(i),
+ I2 => pc(i),
+ O => pc_value(i) );
+
+ register_bit: FDRSE
+ port map ( D => inc_pc_value(i),
+ Q => pc(i),
+ R => internal_reset,
+ S => active_interrupt,
+ CE => pc_enable,
+ C => clk);
+
+ pc_lsb_carry: if i=0 generate
+ begin
+
+ pc_vector_muxcy: MUXCY
+ port map( DI => '0',
+ CI => instruction(13),
+ S => pc_vector(i),
+ O => pc_vector_carry(i));
+
+ pc_vector_xor: XORCY
+ port map( LI => pc_vector(i),
+ CI => instruction(13),
+ O => inc_pc_vector(i));
+
+ pc_value_muxcy: MUXCY
+ port map( DI => '0',
+ CI => normal_count,
+ S => pc_value(i),
+ O => pc_value_carry(i));
+
+ pc_value_xor: XORCY
+ port map( LI => pc_value(i),
+ CI => normal_count,
+ O => inc_pc_value(i));
+
+ end generate pc_lsb_carry;
+
+ pc_mid_carry: if i>0 and i<9 generate
+ begin
+
+ pc_vector_muxcy: MUXCY
+ port map( DI => '0',
+ CI => pc_vector_carry(i-1),
+ S => pc_vector(i),
+ O => pc_vector_carry(i));
+
+ pc_vector_xor: XORCY
+ port map( LI => pc_vector(i),
+ CI => pc_vector_carry(i-1),
+ O => inc_pc_vector(i));
+
+ pc_value_muxcy: MUXCY
+ port map( DI => '0',
+ CI => pc_value_carry(i-1),
+ S => pc_value(i),
+ O => pc_value_carry(i));
+
+ pc_value_xor: XORCY
+ port map( LI => pc_value(i),
+ CI => pc_value_carry(i-1),
+ O => inc_pc_value(i));
+
+ end generate pc_mid_carry;
+
+ pc_msb_carry: if i=9 generate
+ begin
+
+ pc_vector_xor: XORCY
+ port map( LI => pc_vector(i),
+ CI => pc_vector_carry(i-1),
+ O => inc_pc_vector(i));
+
+ pc_value_xor: XORCY
+ port map( LI => pc_value(i),
+ CI => pc_value_carry(i-1),
+ O => inc_pc_value(i));
+
+ end generate pc_msb_carry;
+
+ end generate pc_loop;
+
+ address <= pc;
+--
+------------------------------------------------------------------------------------
+--
+-- Register Bank and second operand selection.
+--
+-- Definition of an 8-bit dual port RAM with 16 locations
+-- including write enable decode.
+--
+-- Outputs are assigned to PORT_ID and OUT_PORT.
+--
+------------------------------------------------------------------------------------
+--
+ -- Forming decode signal
+
+ register_type_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0145")
+ --synthesis translate_on
+ port map( I0 => active_interrupt,
+ I1 => instruction(15),
+ I2 => instruction(16),
+ I3 => instruction(17),
+ O => register_type );
+
+ register_write_flop: FD
+ port map ( D => register_type,
+ Q => register_write,
+ C => clk);
+
+ register_enable_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"8")
+ --synthesis translate_on
+ port map( I0 => t_state,
+ I1 => register_write,
+ O => register_enable );
+
+ reg_loop: for i in 0 to 7 generate
+ --
+ -- Attribute to define RAM contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ --
+ attribute INIT : string;
+ attribute INIT of register_bit : label is "0000";
+ attribute INIT of operand_select_mux : label is "E4";
+ --
+ begin
+
+ register_bit: RAM16X1D
+ --synthesis translate_off
+ generic map(INIT => X"0000")
+ --synthesis translate_on
+ port map ( D => alu_result(i),
+ WE => register_enable,
+ WCLK => clk,
+ A0 => instruction(8),
+ A1 => instruction(9),
+ A2 => instruction(10),
+ A3 => instruction(11),
+ DPRA0 => instruction(4),
+ DPRA1 => instruction(5),
+ DPRA2 => instruction(6),
+ DPRA3 => instruction(7),
+ SPO => sx(i),
+ DPO => sy(i));
+
+ operand_select_mux: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"E4")
+ --synthesis translate_on
+ port map( I0 => instruction(12),
+ I1 => instruction(i),
+ I2 => sy(i),
+ O => second_operand(i) );
+
+ end generate reg_loop;
+
+ out_port <= sx;
+ port_id <= second_operand;
+--
+------------------------------------------------------------------------------------
+--
+-- Store Memory
+--
+-- Definition of an 8-bit single port RAM with 64 locations
+-- including write enable decode.
+--
+------------------------------------------------------------------------------------
+--
+ -- Forming decode signal
+
+ memory_type_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0400")
+ --synthesis translate_on
+ port map( I0 => active_interrupt,
+ I1 => instruction(15),
+ I2 => instruction(16),
+ I3 => instruction(17),
+ O => memory_type );
+
+ memory_write_flop: FD
+ port map ( D => memory_type,
+ Q => memory_write,
+ C => clk);
+
+ memory_enable_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"8000")
+ --synthesis translate_on
+ port map( I0 => t_state,
+ I1 => instruction(13),
+ I2 => instruction(14),
+ I3 => memory_write,
+ O => memory_enable );
+
+ store_loop: for i in 0 to 7 generate
+ --
+ -- Attribute to define RAM contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ --
+ attribute INIT : string;
+ attribute INIT of memory_bit : label is "0000000000000000";
+ --
+ begin
+
+ memory_bit: RAM64X1S
+ --synthesis translate_off
+ generic map(INIT => X"0000000000000000")
+ --synthesis translate_on
+ port map ( D => sx(i),
+ WE => memory_enable,
+ WCLK => clk,
+ A0 => second_operand(0),
+ A1 => second_operand(1),
+ A2 => second_operand(2),
+ A3 => second_operand(3),
+ A4 => second_operand(4),
+ A5 => second_operand(5),
+ O => memory_data(i));
+
+ store_flop: FD
+ port map ( D => memory_data(i),
+ Q => store_data(i),
+ C => clk);
+
+ end generate store_loop;
+--
+------------------------------------------------------------------------------------
+--
+-- Logical operations
+--
+-- Definition of AND, OR, XOR and LOAD functions which also provides TEST.
+-- Includes pipeline stage used to form ALU multiplexer including decode.
+--
+------------------------------------------------------------------------------------
+--
+ sel_logical_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"FFE2")
+ --synthesis translate_on
+ port map( I0 => instruction(14),
+ I1 => instruction(15),
+ I2 => instruction(16),
+ I3 => instruction(17),
+ O => sel_logical );
+
+ logical_loop: for i in 0 to 7 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ attribute INIT : string;
+ attribute INIT of logical_lut : label is "6E8A";
+ --
+ begin
+
+ logical_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"6E8A")
+ --synthesis translate_on
+ port map( I0 => second_operand(i),
+ I1 => sx(i),
+ I2 => instruction(13),
+ I3 => instruction(14),
+ O => logical_value(i));
+
+ logical_flop: FDR
+ port map ( D => logical_value(i),
+ Q => logical_result(i),
+ R => sel_logical,
+ C => clk);
+
+ end generate logical_loop;
+--
+--
+------------------------------------------------------------------------------------
+--
+-- Shift and Rotate operations
+--
+-- Includes pipeline stage used to form ALU multiplexer including decode.
+--
+------------------------------------------------------------------------------------
+--
+ sel_shift_inv: INV -- Inverter should be implemented in the reset to flip flops
+ port map( I => instruction(17),
+ O => sel_shift);
+
+ -- Bit to input to shift register
+
+ high_shift_in_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"E4")
+ --synthesis translate_on
+ port map( I0 => instruction(1),
+ I1 => sx(0),
+ I2 => instruction(0),
+ O => high_shift_in );
+
+ low_shift_in_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"E4")
+ --synthesis translate_on
+ port map( I0 => instruction(1),
+ I1 => carry_flag,
+ I2 => sx(7),
+ O => low_shift_in );
+
+ shift_in_muxf5: MUXF5
+ port map( I1 => high_shift_in,
+ I0 => low_shift_in,
+ S => instruction(2),
+ O => shift_in );
+
+ -- Forming shift carry signal
+
+ shift_carry_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"E4")
+ --synthesis translate_on
+ port map( I0 => instruction(3),
+ I1 => sx(7),
+ I2 => sx(0),
+ O => shift_carry_value );
+
+ pipeline_bit: FD
+ port map ( D => shift_carry_value,
+ Q => shift_carry,
+ C => clk);
+
+ shift_loop: for i in 0 to 7 generate
+ begin
+
+ lsb_shift: if i=0 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ attribute INIT : string;
+ attribute INIT of shift_mux_lut : label is "E4";
+ --
+ begin
+
+ shift_mux_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"E4")
+ --synthesis translate_on
+ port map( I0 => instruction(3),
+ I1 => shift_in,
+ I2 => sx(i+1),
+ O => shift_value(i) );
+
+ end generate lsb_shift;
+
+ mid_shift: if i>0 and i<7 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ attribute INIT : string;
+ attribute INIT of shift_mux_lut : label is "E4";
+ --
+ begin
+
+ shift_mux_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"E4")
+ --synthesis translate_on
+ port map( I0 => instruction(3),
+ I1 => sx(i-1),
+ I2 => sx(i+1),
+ O => shift_value(i) );
+
+ end generate mid_shift;
+
+ msb_shift: if i=7 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ attribute INIT : string;
+ attribute INIT of shift_mux_lut : label is "E4";
+ --
+ begin
+
+ shift_mux_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"E4")
+ --synthesis translate_on
+ port map( I0 => instruction(3),
+ I1 => sx(i-1),
+ I2 => shift_in,
+ O => shift_value(i) );
+
+ end generate msb_shift;
+
+ shift_flop: FDR
+ port map ( D => shift_value(i),
+ Q => shift_result(i),
+ R => sel_shift,
+ C => clk);
+
+ end generate shift_loop;
+--
+------------------------------------------------------------------------------------
+--
+-- Arithmetic operations
+--
+-- Definition of ADD, ADDCY, SUB and SUBCY functions which also provides COMPARE.
+-- Includes pipeline stage used to form ALU multiplexer including decode.
+--
+------------------------------------------------------------------------------------
+--
+ sel_arith_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"1F")
+ --synthesis translate_on
+ port map( I0 => instruction(14),
+ I1 => instruction(15),
+ I2 => instruction(16),
+ O => sel_arith );
+
+ arith_loop: for i in 0 to 7 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ attribute INIT : string;
+ attribute INIT of arith_lut : label is "96";
+ --
+ begin
+
+ lsb_arith: if i=0 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ attribute INIT : string;
+ attribute INIT of arith_carry_in_lut : label is "6C";
+ --
+ begin
+
+ arith_carry_in_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"6C")
+ --synthesis translate_on
+ port map( I0 => instruction(13),
+ I1 => instruction(14),
+ I2 => carry_flag,
+ O => sel_arith_carry_in );
+
+ arith_carry_in_muxcy: MUXCY
+ port map( DI => '0',
+ CI => '1',
+ S => sel_arith_carry_in,
+ O => arith_carry_in);
+
+ arith_muxcy: MUXCY
+ port map( DI => sx(i),
+ CI => arith_carry_in,
+ S => half_arith(i),
+ O => arith_internal_carry(i));
+
+ arith_xor: XORCY
+ port map( LI => half_arith(i),
+ CI => arith_carry_in,
+ O => arith_value(i));
+
+ end generate lsb_arith;
+
+ mid_arith: if i>0 and i<7 generate
+ begin
+
+ arith_muxcy: MUXCY
+ port map( DI => sx(i),
+ CI => arith_internal_carry(i-1),
+ S => half_arith(i),
+ O => arith_internal_carry(i));
+
+ arith_xor: XORCY
+ port map( LI => half_arith(i),
+ CI => arith_internal_carry(i-1),
+ O => arith_value(i));
+
+ end generate mid_arith;
+
+ msb_arith: if i=7 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ attribute INIT : string;
+ attribute INIT of arith_carry_out_lut : label is "2";
+ --
+ begin
+
+ arith_muxcy: MUXCY
+ port map( DI => sx(i),
+ CI => arith_internal_carry(i-1),
+ S => half_arith(i),
+ O => arith_internal_carry(i));
+
+ arith_xor: XORCY
+ port map( LI => half_arith(i),
+ CI => arith_internal_carry(i-1),
+ O => arith_value(i));
+
+ arith_carry_out_lut: LUT1
+ --synthesis translate_off
+ generic map (INIT => X"2")
+ --synthesis translate_on
+ port map( I0 => instruction(14),
+ O => invert_arith_carry );
+
+ arith_carry_out_xor: XORCY
+ port map( LI => invert_arith_carry,
+ CI => arith_internal_carry(i),
+ O => arith_carry_out);
+
+ arith_carry_flop: FDR
+ port map ( D => arith_carry_out,
+ Q => arith_carry,
+ R => sel_arith,
+ C => clk);
+
+ end generate msb_arith;
+
+ arith_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"96")
+ --synthesis translate_on
+ port map( I0 => sx(i),
+ I1 => second_operand(i),
+ I2 => instruction(14),
+ O => half_arith(i));
+
+ arith_flop: FDR
+ port map ( D => arith_value(i),
+ Q => arith_result(i),
+ R => sel_arith,
+ C => clk);
+
+ end generate arith_loop;
+--
+--
+------------------------------------------------------------------------------------
+--
+-- ALU multiplexer
+--
+------------------------------------------------------------------------------------
+--
+ input_fetch_type_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0002")
+ --synthesis translate_on
+ port map( I0 => instruction(14),
+ I1 => instruction(15),
+ I2 => instruction(16),
+ I3 => instruction(17),
+ O => input_fetch_type );
+
+ sel_group_flop: FD
+ port map ( D => input_fetch_type,
+ Q => sel_group,
+ C => clk);
+
+ alu_mux_loop: for i in 0 to 7 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ attribute INIT : string;
+ attribute INIT of or_lut : label is "FE";
+ attribute INIT of mux_lut : label is "E4";
+ --
+ begin
+
+ or_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"FE")
+ --synthesis translate_on
+ port map( I0 => logical_result(i),
+ I1 => arith_result(i),
+ I2 => shift_result(i),
+ O => alu_group(i));
+
+ mux_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"E4")
+ --synthesis translate_on
+ port map( I0 => instruction(13),
+ I1 => in_port(i),
+ I2 => store_data(i),
+ O => input_group(i));
+
+ shift_in_muxf5: MUXF5
+ port map( I1 => input_group(i),
+ I0 => alu_group(i),
+ S => sel_group,
+ O => alu_result(i) );
+
+ end generate alu_mux_loop;
+--
+------------------------------------------------------------------------------------
+--
+-- Read and Write Strobes
+--
+------------------------------------------------------------------------------------
+--
+ io_decode_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0010")
+ --synthesis translate_on
+ port map( I0 => active_interrupt,
+ I1 => instruction(13),
+ I2 => instruction(14),
+ I3 => instruction(16),
+ O => io_initial_decode );
+
+ write_active_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"4000")
+ --synthesis translate_on
+ port map( I0 => t_state,
+ I1 => instruction(15),
+ I2 => instruction(17),
+ I3 => io_initial_decode,
+ O => write_active );
+
+ write_strobe_flop: FDR
+ port map ( D => write_active,
+ Q => write_strobe,
+ R => internal_reset,
+ C => clk);
+
+ read_active_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0100")
+ --synthesis translate_on
+ port map( I0 => t_state,
+ I1 => instruction(15),
+ I2 => instruction(17),
+ I3 => io_initial_decode,
+ O => read_active );
+
+ read_strobe_flop: FDR
+ port map ( D => read_active,
+ Q => read_strobe,
+ R => internal_reset,
+ C => clk);
+--
+------------------------------------------------------------------------------------
+--
+-- Program CALL/RETURN stack
+--
+-- Provided the counter and memory for a 32 deep stack supporting nested
+-- subroutine calls to a depth of 31 levels.
+--
+------------------------------------------------------------------------------------
+--
+ -- Stack memory is 32 locations of 10-bit single port.
+
+ stack_ram_inv: INV -- Inverter should be implemented in the WE to RAM
+ port map( I => t_state,
+ O => stack_write_enable);
+
+ stack_ram_loop: for i in 0 to 9 generate
+ --
+ -- Attribute to define RAM contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ --
+ attribute INIT : string;
+ attribute INIT of stack_bit : label is "00000000";
+ --
+ begin
+
+ stack_bit: RAM32X1S
+ --synthesis translate_off
+ generic map(INIT => X"00000000")
+ --synthesis translate_on
+ port map ( D => pc(i),
+ WE => stack_write_enable,
+ WCLK => clk,
+ A0 => stack_address(0),
+ A1 => stack_address(1),
+ A2 => stack_address(2),
+ A3 => stack_address(3),
+ A4 => stack_address(4),
+ O => stack_ram_data(i));
+
+ stack_flop: FD
+ port map ( D => stack_ram_data(i),
+ Q => stack_pop_data(i),
+ C => clk);
+
+ end generate stack_ram_loop;
+
+ -- Stack address pointer is a 5-bit counter
+
+ stack_count_inv: INV -- Inverter should be implemented in the CE to the flip-flops
+ port map( I => active_interrupt,
+ O => not_active_interrupt);
+
+ stack_count_loop: for i in 0 to 4 generate
+ begin
+
+ register_bit: FDRE
+ port map ( D => next_stack_address(i),
+ Q => stack_address(i),
+ R => internal_reset,
+ CE => not_active_interrupt,
+ C => clk);
+
+ lsb_stack_count: if i=0 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ --
+ attribute INIT : string;
+ attribute INIT of count_lut : label is "6555";
+ --
+ begin
+
+ count_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"6555")
+ --synthesis translate_on
+ port map( I0 => stack_address(i),
+ I1 => t_state,
+ I2 => valid_to_move,
+ I3 => push_or_pop_type,
+ O => half_stack_address(i) );
+
+ count_muxcy: MUXCY
+ port map( DI => stack_address(i),
+ CI => '0',
+ S => half_stack_address(i),
+ O => stack_address_carry(i));
+
+ count_xor: XORCY
+ port map( LI => half_stack_address(i),
+ CI => '0',
+ O => next_stack_address(i));
+
+ end generate lsb_stack_count;
+
+ mid_stack_count: if i>0 and i<4 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ --
+ attribute INIT : string;
+ attribute INIT of count_lut : label is "A999";
+ --
+ begin
+
+ count_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"A999")
+ --synthesis translate_on
+ port map( I0 => stack_address(i),
+ I1 => t_state,
+ I2 => valid_to_move,
+ I3 => call_type,
+ O => half_stack_address(i) );
+
+ count_muxcy: MUXCY
+ port map( DI => stack_address(i),
+ CI => stack_address_carry(i-1),
+ S => half_stack_address(i),
+ O => stack_address_carry(i));
+
+ count_xor: XORCY
+ port map( LI => half_stack_address(i),
+ CI => stack_address_carry(i-1),
+ O => next_stack_address(i));
+
+ end generate mid_stack_count;
+
+
+ msb_stack_count: if i=4 generate
+ --
+ -- Attribute to define LUT contents during implementation
+ -- The information is repeated in the generic map for functional simulation
+ --
+ attribute INIT : string;
+ attribute INIT of count_lut : label is "A999";
+ --
+ begin
+
+ count_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"A999")
+ --synthesis translate_on
+ port map( I0 => stack_address(i),
+ I1 => t_state,
+ I2 => valid_to_move,
+ I3 => call_type,
+ O => half_stack_address(i) );
+
+ count_xor: XORCY
+ port map( LI => half_stack_address(i),
+ CI => stack_address_carry(i-1),
+ O => next_stack_address(i));
+
+ end generate msb_stack_count;
+
+ end generate stack_count_loop;
+
+--
+------------------------------------------------------------------------------------
+--
+-- End of description for KCPSM3 macro.
+--
+------------------------------------------------------------------------------------
+--
+--**********************************************************************************
+-- Code for simulation purposes only after this line
+--**********************************************************************************
+--
+------------------------------------------------------------------------------------
+--
+-- Code for simulation.
+--
+-- Disassemble the instruction codes to form a text string variable for display.
+-- Determine status of reset and flags and present in the form of a text string.
+-- Provide a local variables to simulate the contents of each register and scratch
+-- pad memory location.
+--
+------------------------------------------------------------------------------------
+--
+ --All of this section is ignored during synthesis.
+ --synthesis translate off
+
+ simulation: process (clk, instruction)
+ --
+ --complete instruction decode
+ --
+ variable kcpsm3_opcode : string(1 to 19);
+ --
+ --Status of flags and processor
+ --
+ variable kcpsm3_status : string(1 to 13):= "NZ, NC, Reset";
+
+ --
+ --contents of each register
+ --
+ variable s0_contents : std_logic_vector(7 downto 0):=X"00";
+ variable s1_contents : std_logic_vector(7 downto 0):=X"00";
+ variable s2_contents : std_logic_vector(7 downto 0):=X"00";
+ variable s3_contents : std_logic_vector(7 downto 0):=X"00";
+ variable s4_contents : std_logic_vector(7 downto 0):=X"00";
+ variable s5_contents : std_logic_vector(7 downto 0):=X"00";
+ variable s6_contents : std_logic_vector(7 downto 0):=X"00";
+ variable s7_contents : std_logic_vector(7 downto 0):=X"00";
+ variable s8_contents : std_logic_vector(7 downto 0):=X"00";
+ variable s9_contents : std_logic_vector(7 downto 0):=X"00";
+ variable sa_contents : std_logic_vector(7 downto 0):=X"00";
+ variable sb_contents : std_logic_vector(7 downto 0):=X"00";
+ variable sc_contents : std_logic_vector(7 downto 0):=X"00";
+ variable sd_contents : std_logic_vector(7 downto 0):=X"00";
+ variable se_contents : std_logic_vector(7 downto 0):=X"00";
+ variable sf_contents : std_logic_vector(7 downto 0):=X"00";
+ --
+ --contents of each scratch pad memory location
+ --
+ variable spm00_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm01_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm02_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm03_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm04_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm05_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm06_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm07_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm08_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm09_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm0a_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm0b_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm0c_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm0d_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm0e_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm0f_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm10_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm11_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm12_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm13_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm14_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm15_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm16_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm17_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm18_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm19_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm1a_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm1b_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm1c_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm1d_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm1e_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm1f_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm20_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm21_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm22_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm23_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm24_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm25_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm26_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm27_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm28_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm29_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm2a_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm2b_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm2c_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm2d_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm2e_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm2f_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm30_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm31_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm32_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm33_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm34_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm35_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm36_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm37_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm38_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm39_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm3a_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm3b_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm3c_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm3d_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm3e_contents : std_logic_vector(7 downto 0):=X"00";
+ variable spm3f_contents : std_logic_vector(7 downto 0):=X"00";
+ --
+ --temporary variables
+ --
+ variable sx_decode : string(1 to 2); --sX register specification
+ variable sy_decode : string(1 to 2); --sY register specification
+ variable kk_decode : string(1 to 2); --constant value specification
+ variable aaa_decode : string(1 to 3); --address specification
+ --
+ --------------------------------------------------------------------------------
+ --
+ -- Function to convert 4-bit binary nibble to hexadecimal character
+ --
+ --------------------------------------------------------------------------------
+ --
+ function hexcharacter (nibble: std_logic_vector(3 downto 0))
+ return character is
+ variable hex: character;
+ begin
+ case nibble is
+ when "0000" => hex := '0';
+ when "0001" => hex := '1';
+ when "0010" => hex := '2';
+ when "0011" => hex := '3';
+ when "0100" => hex := '4';
+ when "0101" => hex := '5';
+ when "0110" => hex := '6';
+ when "0111" => hex := '7';
+ when "1000" => hex := '8';
+ when "1001" => hex := '9';
+ when "1010" => hex := 'A';
+ when "1011" => hex := 'B';
+ when "1100" => hex := 'C';
+ when "1101" => hex := 'D';
+ when "1110" => hex := 'E';
+ when "1111" => hex := 'F';
+ when others => hex := 'x';
+ end case;
+ return hex;
+ end hexcharacter;
+ --
+ --------------------------------------------------------------------------------
+ --
+ begin
+
+ -- decode first register
+ sx_decode(1) := 's';
+ sx_decode(2) := hexcharacter(instruction(11 downto 8));
+
+ -- decode second register
+ sy_decode(1) := 's';
+ sy_decode(2) := hexcharacter(instruction(7 downto 4));
+
+ -- decode constant value
+ kk_decode(1) := hexcharacter(instruction(7 downto 4));
+ kk_decode(2) := hexcharacter(instruction(3 downto 0));
+
+ -- address value
+ aaa_decode(1) := hexcharacter("00" & instruction(9 downto 8));
+ aaa_decode(2) := hexcharacter(instruction(7 downto 4));
+ aaa_decode(3) := hexcharacter(instruction(3 downto 0));
+
+ -- decode instruction
+ case instruction(17 downto 12) is
+ when "000000" => kcpsm3_opcode := "LOAD " & sx_decode & ',' & kk_decode & " ";
+ when "000001" => kcpsm3_opcode := "LOAD " & sx_decode & ',' & sy_decode & " ";
+ when "001010" => kcpsm3_opcode := "AND " & sx_decode & ',' & kk_decode & " ";
+ when "001011" => kcpsm3_opcode := "AND " & sx_decode & ',' & sy_decode & " ";
+ when "001100" => kcpsm3_opcode := "OR " & sx_decode & ',' & kk_decode & " ";
+ when "001101" => kcpsm3_opcode := "OR " & sx_decode & ',' & sy_decode & " ";
+ when "001110" => kcpsm3_opcode := "XOR " & sx_decode & ',' & kk_decode & " ";
+ when "001111" => kcpsm3_opcode := "XOR " & sx_decode & ',' & sy_decode & " ";
+ when "010010" => kcpsm3_opcode := "TEST " & sx_decode & ',' & kk_decode & " ";
+ when "010011" => kcpsm3_opcode := "TEST " & sx_decode & ',' & sy_decode & " ";
+ when "011000" => kcpsm3_opcode := "ADD " & sx_decode & ',' & kk_decode & " ";
+ when "011001" => kcpsm3_opcode := "ADD " & sx_decode & ',' & sy_decode & " ";
+ when "011010" => kcpsm3_opcode := "ADDCY " & sx_decode & ',' & kk_decode & " ";
+ when "011011" => kcpsm3_opcode := "ADDCY " & sx_decode & ',' & sy_decode & " ";
+ when "011100" => kcpsm3_opcode := "SUB " & sx_decode & ',' & kk_decode & " ";
+ when "011101" => kcpsm3_opcode := "SUB " & sx_decode & ',' & sy_decode & " ";
+ when "011110" => kcpsm3_opcode := "SUBCY " & sx_decode & ',' & kk_decode & " ";
+ when "011111" => kcpsm3_opcode := "SUBCY " & sx_decode & ',' & sy_decode & " ";
+ when "010100" => kcpsm3_opcode := "COMPARE " & sx_decode & ',' & kk_decode & " ";
+ when "010101" => kcpsm3_opcode := "COMPARE " & sx_decode & ',' & sy_decode & " ";
+ when "100000" =>
+ case instruction(3 downto 0) is
+ when "0110" => kcpsm3_opcode := "SL0 " & sx_decode & " ";
+ when "0111" => kcpsm3_opcode := "SL1 " & sx_decode & " ";
+ when "0100" => kcpsm3_opcode := "SLX " & sx_decode & " ";
+ when "0000" => kcpsm3_opcode := "SLA " & sx_decode & " ";
+ when "0010" => kcpsm3_opcode := "RL " & sx_decode & " ";
+ when "1110" => kcpsm3_opcode := "SR0 " & sx_decode & " ";
+ when "1111" => kcpsm3_opcode := "SR1 " & sx_decode & " ";
+ when "1010" => kcpsm3_opcode := "SRX " & sx_decode & " ";
+ when "1000" => kcpsm3_opcode := "SRA " & sx_decode & " ";
+ when "1100" => kcpsm3_opcode := "RR " & sx_decode & " ";
+ when others => kcpsm3_opcode := "Invalid Instruction";
+ end case;
+ when "101100" => kcpsm3_opcode := "OUTPUT " & sx_decode & ',' & kk_decode & " ";
+ when "101101" => kcpsm3_opcode := "OUTPUT " & sx_decode & ",(" & sy_decode & ") ";
+ when "000100" => kcpsm3_opcode := "INPUT " & sx_decode & ',' & kk_decode & " ";
+ when "000101" => kcpsm3_opcode := "INPUT " & sx_decode & ",(" & sy_decode & ") ";
+ when "101110" => kcpsm3_opcode := "STORE " & sx_decode & ',' & kk_decode & " ";
+ when "101111" => kcpsm3_opcode := "STORE " & sx_decode & ",(" & sy_decode & ") ";
+ when "000110" => kcpsm3_opcode := "FETCH " & sx_decode & ',' & kk_decode & " ";
+ when "000111" => kcpsm3_opcode := "FETCH " & sx_decode & ",(" & sy_decode & ") ";
+ when "110100" => kcpsm3_opcode := "JUMP " & aaa_decode & " ";
+ when "110101" =>
+ case instruction(11 downto 10) is
+ when "00" => kcpsm3_opcode := "JUMP Z," & aaa_decode & " ";
+ when "01" => kcpsm3_opcode := "JUMP NZ," & aaa_decode & " ";
+ when "10" => kcpsm3_opcode := "JUMP C," & aaa_decode & " ";
+ when "11" => kcpsm3_opcode := "JUMP NC," & aaa_decode & " ";
+ when others => kcpsm3_opcode := "Invalid Instruction";
+ end case;
+ when "110000" => kcpsm3_opcode := "CALL " & aaa_decode & " ";
+ when "110001" =>
+ case instruction(11 downto 10) is
+ when "00" => kcpsm3_opcode := "CALL Z," & aaa_decode & " ";
+ when "01" => kcpsm3_opcode := "CALL NZ," & aaa_decode & " ";
+ when "10" => kcpsm3_opcode := "CALL C," & aaa_decode & " ";
+ when "11" => kcpsm3_opcode := "CALL NC," & aaa_decode & " ";
+ when others => kcpsm3_opcode := "Invalid Instruction";
+ end case;
+ when "101010" => kcpsm3_opcode := "RETURN ";
+ when "101011" =>
+ case instruction(11 downto 10) is
+ when "00" => kcpsm3_opcode := "RETURN Z ";
+ when "01" => kcpsm3_opcode := "RETURN NZ ";
+ when "10" => kcpsm3_opcode := "RETURN C ";
+ when "11" => kcpsm3_opcode := "RETURN NC ";
+ when others => kcpsm3_opcode := "Invalid Instruction";
+ end case;
+ when "111000" =>
+ case instruction(0) is
+ when '0' => kcpsm3_opcode := "RETURNI DISABLE ";
+ when '1' => kcpsm3_opcode := "RETURNI ENABLE ";
+ when others => kcpsm3_opcode := "Invalid Instruction";
+ end case;
+ when "111100" =>
+ case instruction(0) is
+ when '0' => kcpsm3_opcode := "DISABLE INTERRUPT ";
+ when '1' => kcpsm3_opcode := "ENABLE INTERRUPT ";
+ when others => kcpsm3_opcode := "Invalid Instruction";
+ end case;
+ when others => kcpsm3_opcode := "Invalid Instruction";
+ end case;
+
+ if clk'event and clk='1' then
+
+ --reset and flag status information
+ if reset='1' or reset_delay='1' then
+ kcpsm3_status := "NZ, NC, Reset";
+ else
+ kcpsm3_status(7 to 13) := " ";
+ if flag_enable='1' then
+ if zero_carry='1' then
+ kcpsm3_status(1 to 4) := " Z, ";
+ else
+ kcpsm3_status(1 to 4) := "NZ, ";
+ end if;
+ if sel_carry(3)='1' then
+ kcpsm3_status(5 to 6) := " C";
+ else
+ kcpsm3_status(5 to 6) := "NC";
+ end if;
+ end if;
+ end if;
+
+ --simulation of register contents
+ if register_enable='1' then
+ case instruction(11 downto 8) is
+ when "0000" => s0_contents := alu_result;
+ when "0001" => s1_contents := alu_result;
+ when "0010" => s2_contents := alu_result;
+ when "0011" => s3_contents := alu_result;
+ when "0100" => s4_contents := alu_result;
+ when "0101" => s5_contents := alu_result;
+ when "0110" => s6_contents := alu_result;
+ when "0111" => s7_contents := alu_result;
+ when "1000" => s8_contents := alu_result;
+ when "1001" => s9_contents := alu_result;
+ when "1010" => sa_contents := alu_result;
+ when "1011" => sb_contents := alu_result;
+ when "1100" => sc_contents := alu_result;
+ when "1101" => sd_contents := alu_result;
+ when "1110" => se_contents := alu_result;
+ when "1111" => sf_contents := alu_result;
+ when others => null;
+ end case;
+ end if;
+
+ --simulation of scratch pad memory contents
+ if memory_enable='1' then
+ case second_operand(5 downto 0) is
+ when "000000" => spm00_contents := sx;
+ when "000001" => spm01_contents := sx;
+ when "000010" => spm02_contents := sx;
+ when "000011" => spm03_contents := sx;
+ when "000100" => spm04_contents := sx;
+ when "000101" => spm05_contents := sx;
+ when "000110" => spm06_contents := sx;
+ when "000111" => spm07_contents := sx;
+ when "001000" => spm08_contents := sx;
+ when "001001" => spm09_contents := sx;
+ when "001010" => spm0a_contents := sx;
+ when "001011" => spm0b_contents := sx;
+ when "001100" => spm0c_contents := sx;
+ when "001101" => spm0d_contents := sx;
+ when "001110" => spm0e_contents := sx;
+ when "001111" => spm0f_contents := sx;
+ when "010000" => spm10_contents := sx;
+ when "010001" => spm11_contents := sx;
+ when "010010" => spm12_contents := sx;
+ when "010011" => spm13_contents := sx;
+ when "010100" => spm14_contents := sx;
+ when "010101" => spm15_contents := sx;
+ when "010110" => spm16_contents := sx;
+ when "010111" => spm17_contents := sx;
+ when "011000" => spm18_contents := sx;
+ when "011001" => spm19_contents := sx;
+ when "011010" => spm1a_contents := sx;
+ when "011011" => spm1b_contents := sx;
+ when "011100" => spm1c_contents := sx;
+ when "011101" => spm1d_contents := sx;
+ when "011110" => spm1e_contents := sx;
+ when "011111" => spm1f_contents := sx;
+ when "100000" => spm20_contents := sx;
+ when "100001" => spm21_contents := sx;
+ when "100010" => spm22_contents := sx;
+ when "100011" => spm23_contents := sx;
+ when "100100" => spm24_contents := sx;
+ when "100101" => spm25_contents := sx;
+ when "100110" => spm26_contents := sx;
+ when "100111" => spm27_contents := sx;
+ when "101000" => spm28_contents := sx;
+ when "101001" => spm29_contents := sx;
+ when "101010" => spm2a_contents := sx;
+ when "101011" => spm2b_contents := sx;
+ when "101100" => spm2c_contents := sx;
+ when "101101" => spm2d_contents := sx;
+ when "101110" => spm2e_contents := sx;
+ when "101111" => spm2f_contents := sx;
+ when "110000" => spm30_contents := sx;
+ when "110001" => spm31_contents := sx;
+ when "110010" => spm32_contents := sx;
+ when "110011" => spm33_contents := sx;
+ when "110100" => spm34_contents := sx;
+ when "110101" => spm35_contents := sx;
+ when "110110" => spm36_contents := sx;
+ when "110111" => spm37_contents := sx;
+ when "111000" => spm38_contents := sx;
+ when "111001" => spm39_contents := sx;
+ when "111010" => spm3a_contents := sx;
+ when "111011" => spm3b_contents := sx;
+ when "111100" => spm3c_contents := sx;
+ when "111101" => spm3d_contents := sx;
+ when "111110" => spm3e_contents := sx;
+ when "111111" => spm3f_contents := sx;
+ when others => null;
+ end case;
+ end if;
+
+ end if;
+
+ end process simulation;
+
+ --synthesis translate on
+--
+--**********************************************************************************
+-- End of simulation code.
+--**********************************************************************************
+--
+--
+end low_level_definition;
+--
+------------------------------------------------------------------------------------
+--
+-- END OF FILE KCPSM3.VHD
+--
+------------------------------------------------------------------------------------
diff --git a/kcuart_rx.vhd b/kcuart_rx.vhd
new file mode 100644
index 0000000..7c22540
--- /dev/null
+++ b/kcuart_rx.vhd
@@ -0,0 +1,352 @@
+-- Constant (K) Compact UART Receiver
+--
+-- Version : 1.10
+-- Version Date : 3rd December 2003
+-- Reason : '--translate' directives changed to '--synthesis translate' directives
+--
+-- Version : 1.00
+-- Version Date : 16th October 2002
+--
+-- Start of design entry : 16th October 2002
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Futhermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for KCUART_RX
+--
+entity kcuart_rx is
+ Port ( serial_in : in std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ data_strobe : out std_logic;
+ en_16_x_baud : in std_logic;
+ clk : in std_logic);
+ end kcuart_rx;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for KCUART_RX
+--
+architecture low_level_definition of kcuart_rx is
+--
+------------------------------------------------------------------------------------
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in KCUART_RX
+--
+------------------------------------------------------------------------------------
+--
+signal sync_serial : std_logic;
+signal stop_bit : std_logic;
+signal data_int : std_logic_vector(7 downto 0);
+signal data_delay : std_logic_vector(7 downto 0);
+signal start_delay : std_logic;
+signal start_bit : std_logic;
+signal edge_delay : std_logic;
+signal start_edge : std_logic;
+signal decode_valid_char : std_logic;
+signal valid_char : std_logic;
+signal decode_purge : std_logic;
+signal purge : std_logic;
+signal valid_srl_delay : std_logic_vector(8 downto 0);
+signal valid_reg_delay : std_logic_vector(8 downto 0);
+signal decode_data_strobe : std_logic;
+--
+--
+------------------------------------------------------------------------------------
+--
+-- Attributes to define LUT contents during implementation
+-- The information is repeated in the generic map for functional simulation--
+--
+------------------------------------------------------------------------------------
+--
+attribute INIT : string;
+attribute INIT of start_srl : label is "0000";
+attribute INIT of edge_srl : label is "0000";
+attribute INIT of valid_lut : label is "0040";
+attribute INIT of purge_lut : label is "54";
+attribute INIT of strobe_lut : label is "8";
+--
+------------------------------------------------------------------------------------
+--
+-- Start of KCUART_RX circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+
+ -- Synchronise input serial data to system clock
+
+ sync_reg: FD
+ port map ( D => serial_in,
+ Q => sync_serial,
+ C => clk);
+
+ stop_reg: FD
+ port map ( D => sync_serial,
+ Q => stop_bit,
+ C => clk);
+
+
+ -- Data delays to capture data at 16 time baud rate
+ -- Each SRL16E is followed by a flip-flop for best timing
+
+ data_loop: for i in 0 to 7 generate
+ begin
+
+ lsbs: if i<7 generate
+ --
+ attribute INIT : string;
+ attribute INIT of delay15_srl : label is "0000";
+ --
+ begin
+
+ delay15_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => data_int(i+1),
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '0',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => data_delay(i) );
+
+ end generate lsbs;
+
+ msb: if i=7 generate
+ --
+ attribute INIT : string;
+ attribute INIT of delay15_srl : label is "0000";
+ --
+ begin
+
+ delay15_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => stop_bit,
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '0',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => data_delay(i) );
+
+ end generate msb;
+
+ data_reg: FDE
+ port map ( D => data_delay(i),
+ Q => data_int(i),
+ CE => en_16_x_baud,
+ C => clk);
+
+ end generate data_loop;
+
+ -- Assign internal signals to outputs
+
+ data_out <= data_int;
+
+ -- Data delays to capture start bit at 16 time baud rate
+
+ start_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => data_int(0),
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '0',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => start_delay );
+
+ start_reg: FDE
+ port map ( D => start_delay,
+ Q => start_bit,
+ CE => en_16_x_baud,
+ C => clk);
+
+
+ -- Data delays to capture start bit leading edge at 16 time baud rate
+ -- Delay ensures data is captured at mid-bit position
+
+ edge_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => start_bit,
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '1',
+ A1 => '0',
+ A2 => '1',
+ A3 => '0',
+ Q => edge_delay );
+
+ edge_reg: FDE
+ port map ( D => edge_delay,
+ Q => start_edge,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Detect a valid character
+
+ valid_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0040")
+ --synthesis translate_on
+ port map( I0 => purge,
+ I1 => stop_bit,
+ I2 => start_edge,
+ I3 => edge_delay,
+ O => decode_valid_char );
+
+ valid_reg: FDE
+ port map ( D => decode_valid_char,
+ Q => valid_char,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Purge of data status
+
+ purge_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"54")
+ --synthesis translate_on
+ port map( I0 => valid_reg_delay(8),
+ I1 => valid_char,
+ I2 => purge,
+ O => decode_purge );
+
+ purge_reg: FDE
+ port map ( D => decode_purge,
+ Q => purge,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Delay of valid_char pulse of length equivalent to the time taken
+ -- to purge data shift register of all data which has been used.
+ -- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
+ -- up to 16 delays and utilising the dedicated flip flop in each stage.
+
+ valid_loop: for i in 0 to 8 generate
+ begin
+
+ lsb: if i=0 generate
+ --
+ attribute INIT : string;
+ attribute INIT of delay15_srl : label is "0000";
+ --
+ begin
+
+ delay15_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => valid_char,
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '0',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => valid_srl_delay(i) );
+
+ end generate lsb;
+
+ msbs: if i>0 generate
+ --
+ attribute INIT : string;
+ attribute INIT of delay16_srl : label is "0000";
+ --
+ begin
+
+ delay16_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => valid_reg_delay(i-1),
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '1',
+ A1 => '1',
+ A2 => '1',
+ A3 => '1',
+ Q => valid_srl_delay(i) );
+
+ end generate msbs;
+
+ data_reg: FDE
+ port map ( D => valid_srl_delay(i),
+ Q => valid_reg_delay(i),
+ CE => en_16_x_baud,
+ C => clk);
+
+ end generate valid_loop;
+
+ -- Form data strobe
+
+ strobe_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"8")
+ --synthesis translate_on
+ port map( I0 => valid_char,
+ I1 => en_16_x_baud,
+ O => decode_data_strobe );
+
+ strobe_reg: FD
+ port map ( D => decode_data_strobe,
+ Q => data_strobe,
+ C => clk);
+
+end low_level_definition;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE KCUART_RX.VHD
+--
+------------------------------------------------------------------------------------
+
+
diff --git a/kcuart_tx.vhd b/kcuart_tx.vhd
new file mode 100644
index 0000000..b8fec85
--- /dev/null
+++ b/kcuart_tx.vhd
@@ -0,0 +1,394 @@
+-- Constant (K) Compact UART Transmitter
+--
+-- Version : 1.10
+-- Version Date : 3rd December 2003
+-- Reason : '--translate' directives changed to '--synthesis translate' directives
+--
+-- Version : 1.00
+-- Version Date : 14th October 2002
+--
+-- Start of design entry : 2nd October 2002
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Futhermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for KCUART_TX
+--
+entity kcuart_tx is
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ send_character : in std_logic;
+ en_16_x_baud : in std_logic;
+ serial_out : out std_logic;
+ Tx_complete : out std_logic;
+ clk : in std_logic);
+ end kcuart_tx;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for KCUART_TX
+--
+architecture low_level_definition of kcuart_tx is
+--
+------------------------------------------------------------------------------------
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in KCUART_TX
+--
+------------------------------------------------------------------------------------
+--
+signal data_01 : std_logic;
+signal data_23 : std_logic;
+signal data_45 : std_logic;
+signal data_67 : std_logic;
+signal data_0123 : std_logic;
+signal data_4567 : std_logic;
+signal data_01234567 : std_logic;
+signal bit_select : std_logic_vector(2 downto 0);
+signal next_count : std_logic_vector(2 downto 0);
+signal mask_count : std_logic_vector(2 downto 0);
+signal mask_count_carry : std_logic_vector(2 downto 0);
+signal count_carry : std_logic_vector(2 downto 0);
+signal ready_to_start : std_logic;
+signal decode_Tx_start : std_logic;
+signal Tx_start : std_logic;
+signal decode_Tx_run : std_logic;
+signal Tx_run : std_logic;
+signal decode_hot_state : std_logic;
+signal hot_state : std_logic;
+signal hot_delay : std_logic;
+signal Tx_bit : std_logic;
+signal decode_Tx_stop : std_logic;
+signal Tx_stop : std_logic;
+signal decode_Tx_complete : std_logic;
+--
+--
+------------------------------------------------------------------------------------
+--
+-- Attributes to define LUT contents during implementation
+-- The information is repeated in the generic map for functional simulation--
+--
+------------------------------------------------------------------------------------
+--
+attribute INIT : string;
+attribute INIT of mux1_lut : label is "E4FF";
+attribute INIT of mux2_lut : label is "E4FF";
+attribute INIT of mux3_lut : label is "E4FF";
+attribute INIT of mux4_lut : label is "E4FF";
+attribute INIT of ready_lut : label is "10";
+attribute INIT of start_lut : label is "0190";
+attribute INIT of run_lut : label is "1540";
+attribute INIT of hot_state_lut : label is "94";
+attribute INIT of delay14_srl : label is "0000";
+attribute INIT of stop_lut : label is "0180";
+attribute INIT of complete_lut : label is "8";
+--
+------------------------------------------------------------------------------------
+--
+-- Start of KCUART_TX circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+
+ -- 8 to 1 multiplexer to convert parallel data to serial
+
+ mux1_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"E4FF")
+ --synthesis translate_on
+ port map( I0 => bit_select(0),
+ I1 => data_in(0),
+ I2 => data_in(1),
+ I3 => Tx_run,
+ O => data_01 );
+
+ mux2_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"E4FF")
+ --synthesis translate_on
+ port map( I0 => bit_select(0),
+ I1 => data_in(2),
+ I2 => data_in(3),
+ I3 => Tx_run,
+ O => data_23 );
+
+ mux3_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"E4FF")
+ --synthesis translate_on
+ port map( I0 => bit_select(0),
+ I1 => data_in(4),
+ I2 => data_in(5),
+ I3 => Tx_run,
+ O => data_45 );
+
+ mux4_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"E4FF")
+ --synthesis translate_on
+ port map( I0 => bit_select(0),
+ I1 => data_in(6),
+ I2 => data_in(7),
+ I3 => Tx_run,
+ O => data_67 );
+
+ mux5_muxf5: MUXF5
+ port map( I1 => data_23,
+ I0 => data_01,
+ S => bit_select(1),
+ O => data_0123 );
+
+ mux6_muxf5: MUXF5
+ port map( I1 => data_67,
+ I0 => data_45,
+ S => bit_select(1),
+ O => data_4567 );
+
+ mux7_muxf6: MUXF6
+ port map( I1 => data_4567,
+ I0 => data_0123,
+ S => bit_select(2),
+ O => data_01234567 );
+
+ -- Register serial output and force start and stop bits
+
+ pipeline_serial: FDRS
+ port map ( D => data_01234567,
+ Q => serial_out,
+ R => Tx_start,
+ S => Tx_stop,
+ C => clk);
+
+ -- 3-bit counter
+ -- Counter is clock enabled by en_16_x_baud
+ -- Counter will be reset when 'Tx_start' is active
+ -- Counter will increment when Tx_bit is active
+ -- Tx_run must be active to count
+ -- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow)
+
+ count_width_loop: for i in 0 to 2 generate
+ --
+ attribute INIT : string;
+ attribute INIT of count_lut : label is "8";
+ --
+ begin
+
+ register_bit: FDRE
+ port map ( D => next_count(i),
+ Q => bit_select(i),
+ CE => en_16_x_baud,
+ R => Tx_start,
+ C => clk);
+
+ count_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"8")
+ --synthesis translate_on
+ port map( I0 => bit_select(i),
+ I1 => Tx_run,
+ O => mask_count(i));
+
+ mask_and: MULT_AND
+ port map( I0 => bit_select(i),
+ I1 => Tx_run,
+ LO => mask_count_carry(i));
+
+ lsb_count: if i=0 generate
+ begin
+
+ count_muxcy: MUXCY
+ port map( DI => mask_count_carry(i),
+ CI => Tx_bit,
+ S => mask_count(i),
+ O => count_carry(i));
+
+ count_xor: XORCY
+ port map( LI => mask_count(i),
+ CI => Tx_bit,
+ O => next_count(i));
+
+ end generate lsb_count;
+
+ upper_count: if i>0 generate
+ begin
+
+ count_muxcy: MUXCY
+ port map( DI => mask_count_carry(i),
+ CI => count_carry(i-1),
+ S => mask_count(i),
+ O => count_carry(i));
+
+ count_xor: XORCY
+ port map( LI => mask_count(i),
+ CI => count_carry(i-1),
+ O => next_count(i));
+
+ end generate upper_count;
+
+ end generate count_width_loop;
+
+ -- Ready to start decode
+
+ ready_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"10")
+ --synthesis translate_on
+ port map( I0 => Tx_run,
+ I1 => Tx_start,
+ I2 => send_character,
+ O => ready_to_start );
+
+ -- Start bit enable
+
+ start_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0190")
+ --synthesis translate_on
+ port map( I0 => Tx_bit,
+ I1 => Tx_stop,
+ I2 => ready_to_start,
+ I3 => Tx_start,
+ O => decode_Tx_start );
+
+ Tx_start_reg: FDE
+ port map ( D => decode_Tx_start,
+ Q => Tx_start,
+ CE => en_16_x_baud,
+ C => clk);
+
+
+ -- Run bit enable
+
+ run_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"1540")
+ --synthesis translate_on
+ port map( I0 => count_carry(2),
+ I1 => Tx_bit,
+ I2 => Tx_start,
+ I3 => Tx_run,
+ O => decode_Tx_run );
+
+ Tx_run_reg: FDE
+ port map ( D => decode_Tx_run,
+ Q => Tx_run,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Bit rate enable
+
+ hot_state_lut: LUT3
+ --synthesis translate_off
+ generic map (INIT => X"94")
+ --synthesis translate_on
+ port map( I0 => Tx_stop,
+ I1 => ready_to_start,
+ I2 => Tx_bit,
+ O => decode_hot_state );
+
+ hot_state_reg: FDE
+ port map ( D => decode_hot_state,
+ Q => hot_state,
+ CE => en_16_x_baud,
+ C => clk);
+
+ delay14_srl: SRL16E
+ --synthesis translate_off
+ generic map (INIT => X"0000")
+ --synthesis translate_on
+ port map( D => hot_state,
+ CE => en_16_x_baud,
+ CLK => clk,
+ A0 => '1',
+ A1 => '0',
+ A2 => '1',
+ A3 => '1',
+ Q => hot_delay );
+
+ Tx_bit_reg: FDE
+ port map ( D => hot_delay,
+ Q => Tx_bit,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Stop bit enable
+
+ stop_lut: LUT4
+ --synthesis translate_off
+ generic map (INIT => X"0180")
+ --synthesis translate_on
+ port map( I0 => Tx_bit,
+ I1 => Tx_run,
+ I2 => count_carry(2),
+ I3 => Tx_stop,
+ O => decode_Tx_stop );
+
+ Tx_stop_reg: FDE
+ port map ( D => decode_Tx_stop,
+ Q => Tx_stop,
+ CE => en_16_x_baud,
+ C => clk);
+
+ -- Tx_complete strobe
+
+ complete_lut: LUT2
+ --synthesis translate_off
+ generic map (INIT => X"8")
+ --synthesis translate_on
+ port map( I0 => count_carry(2),
+ I1 => en_16_x_baud,
+ O => decode_Tx_complete );
+
+ Tx_complete_reg: FD
+ port map ( D => decode_Tx_complete,
+ Q => Tx_complete,
+ C => clk);
+
+
+end low_level_definition;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE KCUART_TX.VHD
+--
+------------------------------------------------------------------------------------
+
+
diff --git a/lago_fpga_vhdl.prj b/lago_fpga_vhdl.prj
new file mode 100644
index 0000000..c05344b
--- /dev/null
+++ b/lago_fpga_vhdl.prj
@@ -0,0 +1,19 @@
+vhdl work "kcuart_tx.vhd"
+vhdl work "kcuart_rx.vhd"
+vhdl work "bbfifo_16x8.vhd"
+vhdl work "uart_tx.vhd"
+vhdl work "uart_rx.vhd"
+vhdl work "kcpsm3.vhd"
+vhdl work "ipcore_dir/fifo.vhd"
+vhdl work "HP_LAGO.VHD"
+vhdl work "GPSNFIFO.VHD"
+verilog work "dcm_200mhz.v"
+vhdl work "usb_if_ctrl.vhd"
+vhdl work "trigger.vhd"
+vhdl work "rampa_hv.vhd"
+vhdl work "interfaz_spi.vhd"
+vhdl work "HP03_par_control.vhd"
+vhdl work "GPS_n_fifo.vhd"
+verilog work "clk_40mhz.v"
+vhdl work "baseline.vhd"
+vhdl work "lago_fpga_vhdl.vhd"
diff --git a/lago_fpga_vhdl.ucf b/lago_fpga_vhdl.ucf
new file mode 100755
index 0000000..e7d8f9f
--- /dev/null
+++ b/lago_fpga_vhdl.ucf
@@ -0,0 +1,179 @@
+#
+#Copyright 2011 - Lab DPR (CAB-CNEA). All rights reserved.
+#
+#Redistribution and use in source and binary forms, with or without
+#modification, are permitted provided that the following conditions
+#are met:
+#
+# 1. Redistributions of source code must retain the above
+# copyright notice, this list of conditions and the following
+# disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above
+# copyright notice, this list of conditions and the following
+# disclaimer in the documentation and/or other materials
+# provided with the distribution.
+#
+#THIS SOFTWARE IS PROVIDED BY LAB DPR ''AS IS'' AND ANY EXPRESS OR IMPLIED
+#WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+#MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+#IN NO EVENT SHALL LAB DPR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+#INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+#SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+#HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+#STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+#IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#POSSIBILITY OF SUCH DAMAGE.
+#
+#The views and conclusions contained in the software and documentation
+#are those of the authors and should not be interpreted as representing
+#official policies, either expressed or implied, of Lab DPR.
+#
+#*****************************************************************************
+
+# Clock pin for Nexys 2 Board
+NET "clk_50m" LOC = "B8";
+NET "clk_50m" TNM_NET = clk_50m;
+TIMESPEC TS_clk = PERIOD "clk_50m" 20 ns HIGH 50%;
+
+# USB Interface.
+# CY7C68013A Port A
+NET "U_SLOE" LOC = "V15" | IOSTANDARD = LVCMOS33 ; # has external pull-up
+NET "U_FIFOAD<0>" LOC = "T14" | IOSTANDARD = LVCMOS33 ;
+NET "U_FIFOAD<1>" LOC = "V13" | IOSTANDARD = LVCMOS33 ;
+NET "U_PKTEND" LOC = "V12" | IOSTANDARD = LVCMOS33 ; # no external pull-up
+
+# CY7C68013A Port B
+NET "U_FD<0>" LOC = "R14" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<1>" LOC = "R13" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<2>" LOC = "P13" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<3>" LOC = "T12" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<4>" LOC = "N11" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<5>" LOC = "R11" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<6>" LOC = "P10" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<7>" LOC = "R10" | IOSTANDARD = LVCMOS33 ;
+
+# CY7C68013A Misc
+NET "U_IFCLK" LOC = "T15" | IOSTANDARD = LVCMOS33 | PERIOD = 20.833;
+NET "U_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE; # Xilinx WebPACK version 10+ needs this.
+
+NET "U_FLAGB" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
+NET "U_FLAGC" LOC = "V16" | IOSTANDARD = LVCMOS33 ;
+
+NET "U_SLRD" LOC = "N9" | IOSTANDARD = LVCMOS33 ; # has external pull-up
+NET "U_SLWR" LOC = "V9" | IOSTANDARD = LVCMOS33 ; # has external pull-up
+
+# 7 segment display
+ NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+ NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+ NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+ NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+ NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+ NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+ NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+ NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+#
+ NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+ NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+ NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+ NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+#
+# Leds
+NET "led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+NET "led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+NET "led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+NET "led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+NET "led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+NET "led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+NET "led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+NET "led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+
+# Leds
+#NET "led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+#NET "led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+#NET "led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+#NET "led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+#NET "led<4>" LOC = "R4" ; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+#NET "led<5>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+#NET "led<6>" LOC = "E17"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+
+#PWM Signals
+NET "hv2" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+NET "hv3" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+
+# Buttons
+NET "reset" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+
+# FX2 connector ch1
+NET "adc_clk1" LOC = "B4";
+NET "ch1<9>" LOC = "A4";
+NET "ch1<8>" LOC = "C3";
+NET "ch1<7>" LOC = "C4";
+NET "ch1<6>" LOC = "B6";
+NET "ch1<5>" LOC = "D5";
+NET "ch1<4>" LOC = "C5";
+NET "ch1<3>" LOC = "F7";
+NET "ch1<2>" LOC = "E7";
+NET "ch1<1>" LOC = "A6";
+NET "ch1<0>" LOC = "C7";
+
+# FX2 connector ch2
+NET "adc_clk2" LOC = "F8";
+NET "ch2<9>" LOC = "D7";
+NET "ch2<8>" LOC = "E8";
+NET "ch2<7>" LOC = "E9";
+NET "ch2<6>" LOC = "C9";
+NET "ch2<5>" LOC = "A8";
+NET "ch2<4>" LOC = "G9";
+NET "ch2<3>" LOC = "F9";
+NET "ch2<2>" LOC = "D10";
+NET "ch2<1>" LOC = "A10";
+NET "ch2<0>" LOC = "B10";
+
+# FX2 connector ch3
+NET "adc_clk3" LOC = "A11";
+NET "ch3<9>" LOC = "D11";
+NET "ch3<8>" LOC = "E10";
+NET "ch3<7>" LOC = "B11";
+NET "ch3<6>" LOC = "C11";
+NET "ch3<5>" LOC = "E11";
+NET "ch3<4>" LOC = "F11";
+NET "ch3<3>" LOC = "E12";
+NET "ch3<2>" LOC = "F12";
+NET "ch3<1>" LOC = "A13";
+NET "ch3<0>" LOC = "B13";
+
+# MAX5501 Interface
+NET "cs_e2prom" LOC = "B14";
+NET "cs_max5501" LOC = "A14";
+NET "spi_dout" LOC = "C14";
+NET "spi_sck" LOC = "D14";
+
+# HP03 Interface
+# It is in JB 6 pin expansion connector
+NET "pMCLK" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+NET "pXCLR" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+NET "pSDA" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+NET "pSCL" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+
+# GPS Interface
+# It is in JC 6 pin expansion connector
+NET "tx_uart" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+NET "pps_port" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+NET "rx_uart" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+
+#Para VHP, esto es para que funcione con el cable que armé, NO con la fuente SWITCHING
+#NET "rx_uart" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+#NET "pps_port" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+#NET "tx_uart" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+
+
+# Switches
+NET "GPSen" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+
+#GPS signals extension (for VHP telescope)
+NET "rx_uart_copy" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+NET "pps_port_copy" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
diff --git a/lago_fpga_vhdl.vhd b/lago_fpga_vhdl.vhd
new file mode 100644
index 0000000..3c9fd49
--- /dev/null
+++ b/lago_fpga_vhdl.vhd
@@ -0,0 +1,578 @@
+--
+-- Copyright (C) 2011 Horacio Arnaldi
+-- e-mail: lharnaldi@cab.cnea.gov.ar
+--
+-- Laboratorio de Detección de PartÃculas y Radiación
+-- Centro Atómico Bariloche
+-- Comisión Nacional de EnergÃa Atómica (CNEA)
+-- San Carlos de Bariloche
+-- Date: 26/09/2011
+-- Ver: v1r7 --
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity lago_fpga_vhdl is
+ generic (
+ VER : natural := 2; --Code Version
+ REV : natural := 0; --Code Revision
+ RESET_POLARITY : std_logic := '1'; --Polarity of reset signal
+ W : natural := 5; --Number of addres bits. 2**W = 32 addres for W=5
+ ADCBITS : natural := 10; --Number of ADC bits
+ L_ARRAY_MUESTRAS : natural := 12; --Samples Longitude of
+ L_ARRAY_PPS : natural := 10; --PPS longitude array
+ L_ARRAY_SCALERS : natural := 3; --Scalers longitude array
+ RBITS : natural := 12; -- := 12; -- numero de bits de los registros
+ REFRESH_RATE : natural := 80000; -- := 80000; -- 80000 clk implican un refresh rate de 2ms (80000 * 25 ns = 2ms)
+ NCH : natural := 3 --:= 3 -- numero de canales de la electronica
+ );
+
+ port(
+ -- Main 50 MHz clk
+ clk_50m : in std_logic;
+ -- Reset button (BTN0)
+ reset : in std_logic;
+
+ -- USB interface
+ u_ifclk : in std_logic;
+
+ -- Data & control from the FX2
+ u_flagb : in std_logic; -- EP2 empty, active low
+ u_flagc : in std_logic; -- EP6 full, active low
+ u_fd : inout std_logic_vector(7 downto 0);
+
+ -- Control to the FX2
+ u_fifoad : out std_logic_vector(1 downto 0);
+ u_sloe : out std_logic;
+ u_slrd : out std_logic; -- active low
+ u_slwr : out std_logic; -- active low
+ u_pktend : out std_logic; -- active low
+ -- ADC inputs and clocks
+ ch1 : in std_logic_vector(9 downto 0);
+ ch2 : in std_logic_vector(9 downto 0);
+ ch3 : in std_logic_vector(9 downto 0);
+ adc_clk1 : out std_logic;
+ adc_clk2 : out std_logic;
+ adc_clk3 : out std_logic;
+
+ -- SPI outputs
+ cs_e2prom : out std_logic;
+ cs_max5501 : out std_logic;
+ spi_dout : out std_logic;
+ spi_sck : out std_logic;
+
+ -- PWM outputs
+ hv2 : out std_logic;
+ hv3 : out std_logic;
+
+ -- I2C and HP03 related signals
+ pSDA : inout std_logic;
+ pSCL : out std_logic;
+ pXCLR : out std_logic;
+ pMCLK : out std_logic;
+
+ --GPS realted signals
+ GPSen : in std_logic;
+
+ -- 1PPS signal
+ pps_port : in std_logic;
+
+ --UART ports
+ tx_uart : out std_logic;
+ rx_uart : in std_logic;
+
+ --Copy of GPS received signals to sync two Nexys
+ rx_uart_copy : inout std_logic;
+ pps_port_copy : inout std_logic;
+
+ --BCD leds dirvers
+ an : out std_logic_vector(3 downto 0);
+ seg : out std_logic_vector(6 downto 0);
+ dp : out std_logic;
+
+
+ -- Status signals
+ led : out std_logic_vector(7 downto 0)
+ );
+end lago_fpga_vhdl;
+
+architecture rtl of lago_fpga_vhdl is
+
+ component clk_40mhz
+ port(
+ clk_50mhz : in std_logic;
+ clk_40mhz : out std_logic);
+ end component;
+
+ signal sclk40m : std_logic;
+ -- Trigger related signals
+ signal sT1, sT2, sT3 : std_logic_vector(9 downto 0);
+ -- SubTrigger related signals
+ signal ssubT1, ssubT2, ssubT3 : std_logic_vector(9 downto 0);
+ signal swr_fifo_A, swr_fifo_B : std_logic;
+ signal sBL1, sBL2, sBL3, siHV1 : std_logic_vector(11 downto 0);
+ signal siHV2, siHV3, soHV1, soHV2, soHV3 : std_logic_vector(11 downto 0);
+ signal sfifo_in : std_logic_vector(31 downto 0);
+ signal sfifo_status : std_logic_vector(7 downto 0);
+ signal sstatus_port, srx_data, sout_port : std_logic_vector(7 downto 0);
+ signal swrite_to_fifo, sread_from_fifo : std_logic;
+ --HP03 related signals
+ signal sC1, sC2, sC3, sC4, sC5, sC6, sC7, sD1, sD2 : std_logic_vector(15 downto 0);
+ signal sA, sB, sC, sD : std_logic_vector(7 downto 0);
+ --GPS realted signals
+ signal sutcngps : std_logic;
+ signal smonth : std_logic_vector(7 downto 0);
+ signal sday : std_logic_vector(7 downto 0);
+ signal syear1 : std_logic_vector(7 downto 0);
+ signal syear2 : std_logic_vector(7 downto 0);
+ signal shours : std_logic_vector(7 downto 0);
+ signal sminutes : std_logic_vector(7 downto 0);
+ signal sseconds : std_logic_vector(7 downto 0);
+ signal sfract_sec1 : std_logic_vector(7 downto 0);
+ signal sfract_sec2 : std_logic_vector(7 downto 0);
+ signal sfract_sec3 : std_logic_vector(7 downto 0);
+ signal sfract_sec4 : std_logic_vector(7 downto 0);
+ signal slatitude1 : std_logic_vector(7 downto 0);
+ signal slatitude2 : std_logic_vector(7 downto 0);
+ signal slatitude3 : std_logic_vector(7 downto 0);
+ signal slatitude4 : std_logic_vector(7 downto 0);
+ signal slongitude1 : std_logic_vector(7 downto 0);
+ signal slongitude2 : std_logic_vector(7 downto 0);
+ signal slongitude3 : std_logic_vector(7 downto 0);
+ signal slongitude4 : std_logic_vector(7 downto 0);
+ signal sellipsoid1 : std_logic_vector(7 downto 0);
+ signal sellipsoid2 : std_logic_vector(7 downto 0);
+ signal sellipsoid3 : std_logic_vector(7 downto 0);
+ signal sellipsoid4 : std_logic_vector(7 downto 0);
+ signal svelocity1 : std_logic_vector(7 downto 0);
+ signal svelocity2 : std_logic_vector(7 downto 0);
+ signal sheading1 : std_logic_vector(7 downto 0);
+ signal sheading2 : std_logic_vector(7 downto 0);
+ signal sgeometry2 : std_logic_vector(7 downto 0);
+ signal sDOP_type : std_logic_vector(7 downto 0);
+ signal sNVS : std_logic_vector(7 downto 0);
+ signal sNTS : std_logic_vector(7 downto 0);
+ signal ssat_ID1 : std_logic_vector(7 downto 0);
+ signal schtm1 : std_logic_vector(7 downto 0);
+ signal sCNo1 : std_logic_vector(7 downto 0);
+ signal schsf1 : std_logic_vector(7 downto 0);
+ signal ssat_ID2 : std_logic_vector(7 downto 0);
+ signal schtm2 : std_logic_vector(7 downto 0);
+ signal sCNo2 : std_logic_vector(7 downto 0);
+ signal schsf2 : std_logic_vector(7 downto 0);
+ signal ssat_ID3 : std_logic_vector(7 downto 0);
+ signal schtm3 : std_logic_vector(7 downto 0);
+ signal sCNo3 : std_logic_vector(7 downto 0);
+ signal schsf3 : std_logic_vector(7 downto 0);
+ signal ssat_ID4 : std_logic_vector(7 downto 0);
+ signal schtm4 : std_logic_vector(7 downto 0);
+ signal sCNo4 : std_logic_vector(7 downto 0);
+ signal schsf4 : std_logic_vector(7 downto 0);
+ signal ssat_ID5 : std_logic_vector(7 downto 0);
+ signal schtm5 : std_logic_vector(7 downto 0);
+ signal sCNo5 : std_logic_vector(7 downto 0);
+ signal schsf5 : std_logic_vector(7 downto 0);
+ signal ssat_ID6 : std_logic_vector(7 downto 0);
+ signal schtm6 : std_logic_vector(7 downto 0);
+ signal sCNo6 : std_logic_vector(7 downto 0);
+ signal schsf6 : std_logic_vector(7 downto 0);
+ signal ssat_ID7 : std_logic_vector(7 downto 0);
+ signal schtm7 : std_logic_vector(7 downto 0);
+ signal sCNo7 : std_logic_vector(7 downto 0);
+ signal schsf7 : std_logic_vector(7 downto 0);
+ signal ssat_ID8 : std_logic_vector(7 downto 0);
+ signal schtm8 : std_logic_vector(7 downto 0);
+ signal sCNo8 : std_logic_vector(7 downto 0);
+ signal schsf8 : std_logic_vector(7 downto 0);
+ signal srsf : std_logic_vector(7 downto 0);
+ signal HV1_led, HV2_led, HV3_led : std_logic;
+ signal stick_2ms : std_logic;
+
+begin
+
+ -- BCD drivers
+ an <= (others => '0');
+ seg <= (others => '1');
+ dp <= '1';
+
+ rx_uart_copy <= rx_uart;
+ pps_port_copy <= pps_port;
+ led(0) <= sfifo_status(0);
+ led(1) <= sfifo_status(1);
+ led(2) <= sfifo_status(2);
+ led(4) <= pps_port;
+ led(5) <= HV3_led;
+ led(6) <= HV2_led;
+ led(7) <= HV1_led;
+ adc_clk1 <= sclk40m;
+ adc_clk2 <= sclk40m;
+ adc_clk3 <= sclk40m;
+
+ clk40mgen: clk_40mhz
+ port map(
+ clk_50mhz => clk_50m,
+ clk_40mhz => sclk40m);
+
+ USB_interface: entity work.usb_if_ctrl
+ generic map(
+ VER => VER,
+ REV => REV,
+ RESET_POLARITY => RESET_POLARITY
+ )
+
+ port map(
+ reset => reset,
+ u_ifclk => u_ifclk,
+ u_fd => u_fd,
+ u_flagc => u_flagc,
+ u_flagb => u_flagb,
+ u_sloe => u_sloe,
+ u_slrd => u_slrd,
+ u_slwr => u_slwr,
+ u_fifoad => u_fifoad,
+ u_pktend => u_pktend,
+ T1 => sT1,
+ T2 => sT2,
+ T3 => sT3,
+ subT1 => ssubT1,
+ subT2 => ssubT2,
+ subT3 => ssubT3,
+ BL1 => sBL1,
+ BL2 => sBL2,
+ BL3 => sBL3,
+ HV1 => siHV1,
+ HV2 => siHV2,
+ HV3 => siHV3,
+ clk40m => sclk40m,
+ fifo_A => sfifo_in,
+ we_A => swr_fifo_A,
+--HP03 signals
+ pC1 => sC1,
+ pC2 => sC2,
+ pC3 => sC3,
+ pC4 => sC4,
+ pC5 => sC5,
+ pC6 => sC6,
+ pC7 => sC7,
+ pA => sA,
+ pB => sB,
+ pC => sC,
+ pD => sD,
+ pD1 => sD1,
+ pD2 => sD2,
+--GPS signals
+ UTCnGPS => sutcngps,
+ month_port => smonth,
+ day_port => sday,
+ year1_port => syear1,
+ year2_port => syear2,
+ hours_port => shours,
+ minutes_port => sminutes,
+ seconds_port => sseconds,
+ fract_sec1_port => sfract_sec1,
+ fract_sec2_port => sfract_sec2,
+ fract_sec3_port => sfract_sec3,
+ fract_sec4_port => sfract_sec4,
+ latitude1_port => slatitude1,
+ latitude2_port => slatitude2,
+ latitude3_port => slatitude3,
+ latitude4_port => slatitude4,
+ longitude1_port => slongitude1,
+ longitude2_port => slongitude2,
+ longitude3_port => slongitude3,
+ longitude4_port => slongitude4,
+ ellipsoid1_port => sellipsoid1,
+ ellipsoid2_port => sellipsoid2,
+ ellipsoid3_port => sellipsoid3,
+ ellipsoid4_port => sellipsoid4,
+ velocity1_port => svelocity1,
+ velocity2_port => svelocity2,
+ heading1_port => sheading1,
+ heading2_port => sheading2,
+ geometry2_port => sgeometry2,
+ DOP_type_port => sDOP_type,
+ num_vis_sat_port => sNVS,
+ num_track_sat_port => sNTS,
+
+ sat_ID1_port => ssat_ID1,
+ chtm1_port => schtm1,
+ CNo1_port => sCNo1,
+ chsf1_port => schsf1,
+
+ sat_ID2_port => ssat_ID2,
+ chtm2_port => schtm2,
+ CNo2_port => sCNo2,
+ chsf2_port => schsf2,
+
+ sat_ID3_port => ssat_ID3,
+ chtm3_port => schtm3,
+ CNo3_port => sCNo3,
+ chsf3_port => schsf3,
+
+ sat_ID4_port => ssat_ID4,
+ chtm4_port => schtm4,
+ CNo4_port => sCNo4,
+ chsf4_port => schsf4,
+
+ sat_ID5_port => ssat_ID5,
+ chtm5_port => schtm5,
+ CNo5_port => sCNo5,
+ chsf5_port => schsf5,
+
+ sat_ID6_port => ssat_ID6,
+ chtm6_port => schtm6,
+ CNo6_port => sCNo6,
+ chsf6_port => schsf6,
+
+ sat_ID7_port => ssat_ID7,
+ chtm7_port => schtm7,
+ CNo7_port => sCNo7,
+ chsf7_port => schsf7,
+
+ sat_ID8_port => ssat_ID8,
+ chtm8_port => schtm8,
+ CNo8_port => sCNo8,
+ chsf8_port => schsf8,
+
+ rsf_port => srsf,
+ pfifo_status => sfifo_status);
+
+ ramp_ctrl1: entity work.ramp
+ generic map (
+ N => 18,
+ M => 200000,
+ P => 12
+ )
+ port map(
+ clk => sclk40m,
+ reset => reset,
+ data_in => siHV1,
+ data_out => soHV1,
+ pwm_pulse => open,
+ led_indicador => HV1_led);
+
+ ramp_ctrl2: entity work.ramp
+ generic map (
+ N => 18,
+ M => 200000,
+ P => 12
+ )
+ port map(
+ clk => sclk40m,
+ reset => reset,
+ data_in => siHV2,
+ data_out => open,
+ pwm_pulse => hv2,
+ led_indicador => HV2_led);
+
+ ramp_ctrl3: entity work.ramp
+ generic map (
+ N => 18,
+ M => 200000,
+ P => 12
+ )
+ port map(
+ clk => sclk40m,
+ reset => reset,
+ data_in => siHV3,
+ data_out => open,
+ pwm_pulse => hv3,
+ led_indicador => HV3_led);
+
+ baseline: entity work.baseline_control
+ generic map (
+ W => W,
+ ADCBITS => ADCBITS,
+ RBITS => RBITS,
+ REFRESH_RATE => REFRESH_RATE,
+ NCH => NCH
+ )
+ port map(
+ clk_40mhz => sclk40m,
+ reset => reset,
+ ptick_2ms => stick_2ms,
+ data_adc1 => ch1,
+ data_adc2 => ch2,
+ data_adc3 => ch3,
+ baseline1 => sBL1,
+ baseline2 => sBL2,
+ baseline3 => sBL3);
+
+ spi_controller: entity work.interfaz_spi
+ port map(
+ clk => sclk40m,
+ reset => reset,
+ ptick_2ms => stick_2ms,
+ data_dac1 => sBL3, --"011010001010",
+ data_dac2 => sBL2,--"011010001010",
+ data_dac3 => soHV1,
+ data_dac4 => sBL1,--"011010001010",
+ cs_e2prom => cs_e2prom,
+ spi_csn => cs_max5501,
+ spi_sdo => spi_dout,
+ spi_clk => spi_sck);
+
+ comp_trigger: entity work.trigger_in
+ generic map(
+ W => W,
+ ADCBITS => ADCBITS,
+ L_ARRAY_MUESTRAS => L_ARRAY_MUESTRAS,
+ L_ARRAY_PPS => L_ARRAY_PPS,
+ L_ARRAY_SCALERS => L_ARRAY_SCALERS
+ )
+ port map(
+ clk_40mhz => sclk40m,
+ reset => reset,
+ data_adc1 => ch1,
+ data_adc2 => ch2,
+ data_adc3 => ch3,
+ trigg_set1 => sT1,
+ trigg_set2 => sT2,
+ trigg_set3 => sT3,
+ subtrigg_set1 => ssubT1,
+ subtrigg_set2 => ssubT2,
+ subtrigg_set3 => ssubT3,
+ pwr_enA => swr_fifo_A,
+ data_out => sfifo_in,
+ pfifo_status => sfifo_status(2 downto 0),
+ ptemperatura => sD2,
+ ppresion => sD1,
+ phora => shours,
+ pminutos => sminutes,
+ psegundos => sseconds,
+ pps_signal => pps_port,
+ gpsen => GPSen,
+ pps_falso_led => led(3),
+ latitude1_port => slatitude1,
+ latitude2_port => slatitude2,
+ latitude3_port => slatitude3,
+ latitude4_port => slatitude4,
+ longitude1_port => slongitude1,
+ longitude2_port => slongitude2,
+ longitude3_port => slongitude3,
+ longitude4_port => slongitude4,
+ ellipsoid1_port => sellipsoid1,
+ ellipsoid2_port => sellipsoid2,
+ ellipsoid3_port => sellipsoid3,
+ ellipsoid4_port => sellipsoid4,
+ num_vis_sat_port => sNVS,
+ num_track_sat_port => sNTS,
+ rsf_port => srsf);
+
+ hp03_controller: entity work.HP03_cntrl
+ Port map (
+ clk => clk_50m,
+ SDA => pSDA,
+ SCL => pSCL,
+ XCLR => pXCLR,
+ MCLK => pMCLK,
+ C1 => sC1,
+ C2 => sC2,
+ C3 => sC3,
+ C4 => sC4,
+ C5 => sC5,
+ C6 => sC6,
+ C7 => sC7,
+ A => sA,
+ B => sB,
+ C => sC,
+ D => sD,
+ D1 => sD1,
+ D2 => sD2);
+
+ gps_interface: entity work.Oncore_ctrl
+ port map(
+ clk => clk_50m,
+ tx_female => tx_uart,
+ rx_female => rx_uart,
+ UTCnGPS => sutcngps,
+ month_port => smonth,
+ day_port => sday,
+ year1_port => syear1,
+ year2_port => syear2,
+ hours_port => shours,
+ minutes_port => sminutes,
+ seconds_port => sseconds,
+ fract_sec1_port => sfract_sec1,
+ fract_sec2_port => sfract_sec2,
+ fract_sec3_port => sfract_sec3,
+ fract_sec4_port => sfract_sec4,
+ latitude1_port => slatitude1,
+ latitude2_port => slatitude2,
+ latitude3_port => slatitude3,
+ latitude4_port => slatitude4,
+ longitude1_port => slongitude1,
+ longitude2_port => slongitude2,
+ longitude3_port => slongitude3,
+ longitude4_port => slongitude4,
+ ellipsoid1_port => sellipsoid1,
+ ellipsoid2_port => sellipsoid2,
+ ellipsoid3_port => sellipsoid3,
+ ellipsoid4_port => sellipsoid4,
+ velocity1_port => svelocity1,
+ velocity2_port => svelocity2,
+ heading1_port => sheading1,
+ heading2_port => sheading2,
+ geometry2_port => sgeometry2,
+ DOP_type_port => sDOP_type,
+ num_vis_sat_port => sNVS,
+ num_track_sat_port => sNTS,
+
+ sat_ID1_port => ssat_ID1,
+ chtm1_port => schtm1,
+ CNo1_port => sCNo1,
+ chsf1_port => schsf1,
+
+ sat_ID2_port => ssat_ID2,
+ chtm2_port => schtm2,
+ CNo2_port => sCNo2,
+ chsf2_port => schsf2,
+
+ sat_ID3_port => ssat_ID3,
+ chtm3_port => schtm3,
+ CNo3_port => sCNo3,
+ chsf3_port => schsf3,
+
+ sat_ID4_port => ssat_ID4,
+ chtm4_port => schtm4,
+ CNo4_port => sCNo4,
+ chsf4_port => schsf4,
+
+ sat_ID5_port => ssat_ID5,
+ chtm5_port => schtm5,
+ CNo5_port => sCNo5,
+ chsf5_port => schsf5,
+
+ sat_ID6_port => ssat_ID6,
+ chtm6_port => schtm6,
+ CNo6_port => sCNo6,
+ chsf6_port => schsf6,
+
+ sat_ID7_port => ssat_ID7,
+ chtm7_port => schtm7,
+ CNo7_port => sCNo7,
+ chsf7_port => schsf7,
+
+ sat_ID8_port => ssat_ID8,
+ chtm8_port => schtm8,
+ CNo8_port => sCNo8,
+ chsf8_port => schsf8,
+
+ rsf_port => srsf);
+
+end rtl;
diff --git a/lago_fpga_vhdl.vhd_orig b/lago_fpga_vhdl.vhd_orig
new file mode 100644
index 0000000..82c6339
--- /dev/null
+++ b/lago_fpga_vhdl.vhd_orig
@@ -0,0 +1,699 @@
+--
+-- Copyright (C) 2011 Horacio Arnaldi
+-- e-mail: lharnaldi@cab.cnea.gov.ar
+--
+-- Laboratorio de Detección de PartÃculas y Radiación
+-- Centro Atómico Bariloche
+-- Comisión Nacional de EnergÃa Atómica (CNEA)
+-- San Carlos de Bariloche
+-- Date: 26/09/2011
+-- Ver: v1r7 --
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity lago_fpga_sync is
+ generic (
+ VER : natural := 2;
+ REV : natural := 1;
+ RESET_POLARITY : std_logic := '1';
+ W : natural := 5;
+ ADCBITS : natural := 10;
+ L_ARRAY_MUESTRAS : natural := 12;
+ L_ARRAY_PPS : natural := 10;
+ L_ARRAY_SCALERS : natural := 3,
+ RBITS : natural := 12; -- := 12; -- numero de bits de los registros
+ REFRESH_RATE : natural := 80000; -- := 80000; -- 80000 clk implican un refresh rate de 2ms (80000 * 25 ns = 2ms)
+ NCH : natural := 3 --:= 3 -- numero de canales de la electronica
+ );
+
+ port(
+ -- Main 50 MHz clk
+ clk_50m : in std_logic;
+ -- Reset button (BTN0)
+ reset : in std_logic;
+
+ -- USB interface
+ u_ifclk : in std_logic;
+
+ -- Data & control from the FX2
+ u_flagb : in std_logic; -- EP2 empty, active low
+ u_flagc : in std_logic; -- EP6 full, active low
+ u_fd : inout std_logic_vector(7 downto 0);
+
+ -- Control to the FX2
+ u_fifoad : out std_logic_vector(1 downto 0);
+ u_sloe : out std_logic;
+ u_slrd : out std_logic; -- active low
+ u_slwr : out std_logic; -- active low
+ u_pktend : out std_logic; -- active low
+ -- ADC inputs and clocks
+ ch1 : in std_logic_vector(9 downto 0);
+ ch2 : in std_logic_vector(9 downto 0);
+ ch3 : in std_logic_vector(9 downto 0);
+ adc_clk1 : out std_logic;
+ adc_clk2 : out std_logic;
+ adc_clk3 : out std_logic;
+
+ -- SPI outputs
+ cs_e2prom : out std_logic;
+ cs_max5501 : out std_logic;
+ spi_dout : out std_logic;
+ spi_sck : out std_logic;
+
+ -- PWM outputs
+ hv2 : out std_logic;
+ hv3 : out std_logic;
+
+ -- I2C and HP03 related signals
+ pSDA : inout std_logic;
+ pSCL : out std_logic;
+ pXCLR : out std_logic;
+ pMCLK : out std_logic;
+
+ --GPS realted signals
+ GPSen : in std_logic;
+
+ -- 1PPS signal
+ pps_port : in std_logic;
+
+ --UART ports
+ tx_uart : out std_logic;
+ rx_uart : in std_logic;
+
+ --Copy of GPS received signals to sync two Nexys
+ rx_uart_copy : inout std_logic;
+ pps_port_copy : inout std_logic;
+
+ --BCD leds dirvers
+ an : out std_logic_vector(3 downto 0);
+ seg : out std_logic_vector(6 downto 0);
+ dp : out std_logic;
+
+
+ -- Status signals
+ led : out std_logic_vector(7 downto 0)
+ );
+end lago_fpga_sync;
+
+architecture rtl of lago_fpga_sync is
+
+ component clk_40mhz
+ port(
+ clk_50mhz : in std_logic;
+ clk_40mhz : out std_logic);
+ end component;
+
+ component interfaz_max5501
+ port(
+ fpga_clk : in std_logic;
+ data_dac1 : in std_logic_vector(11 downto 0);
+ data_dac2 : in std_logic_vector(11 downto 0);
+ data_dac3 : in std_logic_vector(11 downto 0);
+ data_dac4 : in std_logic_vector(11 downto 0);
+ cs_e2prom : out std_logic;
+ cs_max5501 : out std_logic;
+ spi_dout : out std_logic;
+ spi_sck : out std_logic);
+ end component;
+
+ component HP03_cntrl is
+ Port (
+ clk : in std_logic;
+ SDA : inout std_logic;
+ SCL : out std_logic;
+ XCLR : out std_logic;
+ MCLK : out std_logic;
+ C1 : out std_logic_vector(15 downto 0);
+ C2 : out std_logic_vector(15 downto 0);
+ C3 : out std_logic_vector(15 downto 0);
+ C4 : out std_logic_vector(15 downto 0);
+ C5 : out std_logic_vector(15 downto 0);
+ C6 : out std_logic_vector(15 downto 0);
+ C7 : out std_logic_vector(15 downto 0);
+ A : out std_logic_vector(7 downto 0);
+ B : out std_logic_vector(7 downto 0);
+ C : out std_logic_vector(7 downto 0);
+ D : out std_logic_vector(7 downto 0);
+ D1 : out std_logic_vector(15 downto 0);
+ D2 : out std_logic_vector(15 downto 0));
+ end component;
+
+ component Oncore_ctrl is
+ Port (
+ clk : in std_logic;
+ tx_female : out std_logic;
+ rx_female : in std_logic;
+ UTCnGPS : in std_logic;
+ month_port : out std_logic_vector(7 downto 0);
+ day_port : out std_logic_vector(7 downto 0);
+ year1_port : out std_logic_vector(7 downto 0);
+ year2_port : out std_logic_vector(7 downto 0);
+ hours_port : out std_logic_vector(7 downto 0);
+ minutes_port : out std_logic_vector(7 downto 0);
+ seconds_port : out std_logic_vector(7 downto 0);
+ fract_sec1_port : out std_logic_vector(7 downto 0);
+ fract_sec2_port : out std_logic_vector(7 downto 0);
+ fract_sec3_port : out std_logic_vector(7 downto 0);
+ fract_sec4_port : out std_logic_vector(7 downto 0);
+ latitude1_port : out std_logic_vector(7 downto 0);
+ latitude2_port : out std_logic_vector(7 downto 0);
+ latitude3_port : out std_logic_vector(7 downto 0);
+ latitude4_port : out std_logic_vector(7 downto 0);
+ longitude1_port : out std_logic_vector(7 downto 0);
+ longitude2_port : out std_logic_vector(7 downto 0);
+ longitude3_port : out std_logic_vector(7 downto 0);
+ longitude4_port : out std_logic_vector(7 downto 0);
+ ellipsoid1_port : out std_logic_vector(7 downto 0);
+ ellipsoid2_port : out std_logic_vector(7 downto 0);
+ ellipsoid3_port : out std_logic_vector(7 downto 0);
+ ellipsoid4_port : out std_logic_vector(7 downto 0);
+ velocity1_port : out std_logic_vector(7 downto 0);
+ velocity2_port : out std_logic_vector(7 downto 0);
+ heading1_port : out std_logic_vector(7 downto 0);
+ heading2_port : out std_logic_vector(7 downto 0);
+ geometry2_port : out std_logic_vector(7 downto 0);
+ DOP_type_port : out std_logic_vector(7 downto 0);
+ num_vis_sat_port : out std_logic_vector(7 downto 0);
+ num_track_sat_port : out std_logic_vector(7 downto 0);
+
+ sat_ID1_port : out std_logic_vector(7 downto 0);
+ chtm1_port : out std_logic_vector(7 downto 0);
+ CNo1_port : out std_logic_vector(7 downto 0);
+ chsf1_port : out std_logic_vector(7 downto 0);
+
+ sat_ID2_port : out std_logic_vector(7 downto 0);
+ chtm2_port : out std_logic_vector(7 downto 0);
+ CNo2_port : out std_logic_vector(7 downto 0);
+ chsf2_port : out std_logic_vector(7 downto 0);
+
+ sat_ID3_port : out std_logic_vector(7 downto 0);
+ chtm3_port : out std_logic_vector(7 downto 0);
+ CNo3_port : out std_logic_vector(7 downto 0);
+ chsf3_port : out std_logic_vector(7 downto 0);
+
+ sat_ID4_port : out std_logic_vector(7 downto 0);
+ chtm4_port : out std_logic_vector(7 downto 0);
+ CNo4_port : out std_logic_vector(7 downto 0);
+ chsf4_port : out std_logic_vector(7 downto 0);
+
+ sat_ID5_port : out std_logic_vector(7 downto 0);
+ chtm5_port : out std_logic_vector(7 downto 0);
+ CNo5_port : out std_logic_vector(7 downto 0);
+ chsf5_port : out std_logic_vector(7 downto 0);
+
+ sat_ID6_port : out std_logic_vector(7 downto 0);
+ chtm6_port : out std_logic_vector(7 downto 0);
+ CNo6_port : out std_logic_vector(7 downto 0);
+ chsf6_port : out std_logic_vector(7 downto 0);
+
+ sat_ID7_port : out std_logic_vector(7 downto 0);
+ chtm7_port : out std_logic_vector(7 downto 0);
+ CNo7_port : out std_logic_vector(7 downto 0);
+ chsf7_port : out std_logic_vector(7 downto 0);
+
+ sat_ID8_port : out std_logic_vector(7 downto 0);
+ chtm8_port : out std_logic_vector(7 downto 0);
+ CNo8_port : out std_logic_vector(7 downto 0);
+ chsf8_port : out std_logic_vector(7 downto 0);
+
+ rsf_port : out std_logic_vector(7 downto 0));
+ end component;
+
+ signal sclk40m : std_logic;
+ -- Trigger related signals
+ signal sT1, sT2, sT3 : std_logic_vector(9 downto 0);
+ -- SubTrigger related signals
+ signal ssubT1, ssubT2, ssubT3 : std_logic_vector(9 downto 0);
+ signal swr_fifo_A, swr_fifo_B : std_logic;
+ signal sBL1, sBL2, sBL3, siHV1 : std_logic_vector(11 downto 0);
+ signal siHV2, siHV3, soHV1, soHV2, soHV3 : std_logic_vector(11 downto 0);
+ signal sfifo_in : std_logic_vector(31 downto 0);
+ signal sfifo_status : std_logic_vector(7 downto 0);
+ signal sstatus_port, srx_data, sout_port : std_logic_vector(7 downto 0);
+ signal swrite_to_fifo, sread_from_fifo : std_logic;
+ --HP03 related signals
+ signal sC1, sC2, sC3, sC4, sC5, sC6, sC7, sD1, sD2 : std_logic_vector(15 downto 0);
+ signal sA, sB, sC, sD : std_logic_vector(7 downto 0);
+ --GPS realted signals
+ signal sutcngps : std_logic;
+ signal smonth : std_logic_vector(7 downto 0);
+ signal sday : std_logic_vector(7 downto 0);
+ signal syear1 : std_logic_vector(7 downto 0);
+ signal syear2 : std_logic_vector(7 downto 0);
+ signal shours : std_logic_vector(7 downto 0);
+ signal sminutes : std_logic_vector(7 downto 0);
+ signal sseconds : std_logic_vector(7 downto 0);
+ signal sfract_sec1 : std_logic_vector(7 downto 0);
+ signal sfract_sec2 : std_logic_vector(7 downto 0);
+ signal sfract_sec3 : std_logic_vector(7 downto 0);
+ signal sfract_sec4 : std_logic_vector(7 downto 0);
+ signal slatitude1 : std_logic_vector(7 downto 0);
+ signal slatitude2 : std_logic_vector(7 downto 0);
+ signal slatitude3 : std_logic_vector(7 downto 0);
+ signal slatitude4 : std_logic_vector(7 downto 0);
+ signal slongitude1 : std_logic_vector(7 downto 0);
+ signal slongitude2 : std_logic_vector(7 downto 0);
+ signal slongitude3 : std_logic_vector(7 downto 0);
+ signal slongitude4 : std_logic_vector(7 downto 0);
+ signal sellipsoid1 : std_logic_vector(7 downto 0);
+ signal sellipsoid2 : std_logic_vector(7 downto 0);
+ signal sellipsoid3 : std_logic_vector(7 downto 0);
+ signal sellipsoid4 : std_logic_vector(7 downto 0);
+ signal svelocity1 : std_logic_vector(7 downto 0);
+ signal svelocity2 : std_logic_vector(7 downto 0);
+ signal sheading1 : std_logic_vector(7 downto 0);
+ signal sheading2 : std_logic_vector(7 downto 0);
+ signal sgeometry2 : std_logic_vector(7 downto 0);
+ signal sDOP_type : std_logic_vector(7 downto 0);
+ signal sNVS : std_logic_vector(7 downto 0);
+ signal sNTS : std_logic_vector(7 downto 0);
+ signal ssat_ID1 : std_logic_vector(7 downto 0);
+ signal schtm1 : std_logic_vector(7 downto 0);
+ signal sCNo1 : std_logic_vector(7 downto 0);
+ signal schsf1 : std_logic_vector(7 downto 0);
+ signal ssat_ID2 : std_logic_vector(7 downto 0);
+ signal schtm2 : std_logic_vector(7 downto 0);
+ signal sCNo2 : std_logic_vector(7 downto 0);
+ signal schsf2 : std_logic_vector(7 downto 0);
+ signal ssat_ID3 : std_logic_vector(7 downto 0);
+ signal schtm3 : std_logic_vector(7 downto 0);
+ signal sCNo3 : std_logic_vector(7 downto 0);
+ signal schsf3 : std_logic_vector(7 downto 0);
+ signal ssat_ID4 : std_logic_vector(7 downto 0);
+ signal schtm4 : std_logic_vector(7 downto 0);
+ signal sCNo4 : std_logic_vector(7 downto 0);
+ signal schsf4 : std_logic_vector(7 downto 0);
+ signal ssat_ID5 : std_logic_vector(7 downto 0);
+ signal schtm5 : std_logic_vector(7 downto 0);
+ signal sCNo5 : std_logic_vector(7 downto 0);
+ signal schsf5 : std_logic_vector(7 downto 0);
+ signal ssat_ID6 : std_logic_vector(7 downto 0);
+ signal schtm6 : std_logic_vector(7 downto 0);
+ signal sCNo6 : std_logic_vector(7 downto 0);
+ signal schsf6 : std_logic_vector(7 downto 0);
+ signal ssat_ID7 : std_logic_vector(7 downto 0);
+ signal schtm7 : std_logic_vector(7 downto 0);
+ signal sCNo7 : std_logic_vector(7 downto 0);
+ signal schsf7 : std_logic_vector(7 downto 0);
+ signal ssat_ID8 : std_logic_vector(7 downto 0);
+ signal schtm8 : std_logic_vector(7 downto 0);
+ signal sCNo8 : std_logic_vector(7 downto 0);
+ signal schsf8 : std_logic_vector(7 downto 0);
+ signal srsf : std_logic_vector(7 downto 0);
+ signal HV1_led, HV2_led, HV3_led : std_logic;
+
+begin
+
+ -- BCD drivers
+ an <= (others => '0');
+ seg <= (others => '1');
+ dp <= '1';
+
+ rx_uart_copy <= rx_uart;
+ pps_port_copy <= pps_port;
+ led(0) <= sfifo_status(0);
+ led(1) <= sfifo_status(1);
+ led(2) <= sfifo_status(2);
+ led(4) <= pps_port;
+ led(5) <= HV3_led;
+ led(6) <= HV2_led;
+ led(7) <= HV1_led;
+ adc_clk1 <= sclk40m;
+ adc_clk2 <= sclk40m;
+ adc_clk3 <= sclk40m;
+
+ clk40mgen: clk_40mhz
+ port map(
+ clk_50mhz => clk_50m,
+ clk_40mhz => sclk40m);
+
+ USB_interface: entity work.usb_if_ctrl
+ generic map(
+ VER => VER,
+ REV => REV,
+ RESET_POLARITY => RESET_POLARITY
+ )
+
+ port map(
+ reset => reset,
+ u_ifclk => u_ifclk,
+ u_fd => u_fd,
+ u_flagc => u_flagc,
+ u_flagb => u_flagb,
+ u_sloe => u_sloe,
+ u_slrd => u_slrd,
+ u_slwr => u_slwr,
+ u_fifoad => u_fifoad,
+ u_pktend => u_pktend,
+ T1 => sT1,
+ T2 => sT2,
+ T3 => sT3,
+ subT1 => ssubT1,
+ subT2 => ssubT2,
+ subT3 => ssubT3,
+ BL1 => sBL1,
+ BL2 => sBL2,
+ BL3 => sBL3,
+ HV1 => siHV1,
+ HV2 => siHV2,
+ HV3 => siHV3,
+ clk40m => sclk40m,
+ fifo_A => sfifo_in,
+ we_A => swr_fifo_A,
+ --HP03 signals
+ pC1 => sC1,
+ pC2 => sC2,
+ pC3 => sC3,
+ pC4 => sC4,
+ pC5 => sC5,
+ pC6 => sC6,
+ pC7 => sC7,
+ pA => sA,
+ pB => sB,
+ pC => sC,
+ pD => sD,
+ pD1 => sD1,
+ pD2 => sD2,
+ --GPS signals
+ UTCnGPS => sutcngps,
+ month_port => smonth,
+ day_port => sday,
+ year1_port => syear1,
+ year2_port => syear2,
+ hours_port => shours,
+ minutes_port => sminutes,
+ seconds_port => sseconds,
+ fract_sec1_port => sfract_sec1,
+ fract_sec2_port => sfract_sec2,
+ fract_sec3_port => sfract_sec3,
+ fract_sec4_port => sfract_sec4,
+ latitude1_port => slatitude1,
+ latitude2_port => slatitude2,
+ latitude3_port => slatitude3,
+ latitude4_port => slatitude4,
+ longitude1_port => slongitude1,
+ longitude2_port => slongitude2,
+ longitude3_port => slongitude3,
+ longitude4_port => slongitude4,
+ ellipsoid1_port => sellipsoid1,
+ ellipsoid2_port => sellipsoid2,
+ ellipsoid3_port => sellipsoid3,
+ ellipsoid4_port => sellipsoid4,
+ velocity1_port => svelocity1,
+ velocity2_port => svelocity2,
+ heading1_port => sheading1,
+ heading2_port => sheading2,
+ geometry2_port => sgeometry2,
+ DOP_type_port => sDOP_type,
+ num_vis_sat_port => sNVS,
+ num_track_sat_port => sNTS,
+
+ sat_ID1_port => ssat_ID1,
+ chtm1_port => schtm1,
+ CNo1_port => sCNo1,
+ chsf1_port => schsf1,
+
+ sat_ID2_port => ssat_ID2,
+ chtm2_port => schtm2,
+ CNo2_port => sCNo2,
+ chsf2_port => schsf2,
+
+ sat_ID3_port => ssat_ID3,
+ chtm3_port => schtm3,
+ CNo3_port => sCNo3,
+ chsf3_port => schsf3,
+
+ sat_ID4_port => ssat_ID4,
+ chtm4_port => schtm4,
+ CNo4_port => sCNo4,
+ chsf4_port => schsf4,
+
+ sat_ID5_port => ssat_ID5,
+ chtm5_port => schtm5,
+ CNo5_port => sCNo5,
+ chsf5_port => schsf5,
+
+ sat_ID6_port => ssat_ID6,
+ chtm6_port => schtm6,
+ CNo6_port => sCNo6,
+ chsf6_port => schsf6,
+
+ sat_ID7_port => ssat_ID7,
+ chtm7_port => schtm7,
+ CNo7_port => sCNo7,
+ chsf7_port => schsf7,
+
+ sat_ID8_port => ssat_ID8,
+ chtm8_port => schtm8,
+ CNo8_port => sCNo8,
+ chsf8_port => schsf8,
+
+ rsf_port => srsf,
+ pfifo_status => sfifo_status);
+
+ ramp_ctrl1: entity work.ramp
+ generic map (
+ N => 18,
+ M => 200000,
+ P => 12
+ )
+ port map(
+ clk => sclk40m,
+ reset => reset,
+ data_in => siHV1,
+ data_out => soHV1,
+ led_indicador => HV1_led);
+
+ ramp_ctrl2: entity work.ramp
+ generic map (
+ N => 18,
+ M => 200000,
+ P => 12
+ )
+ port map(
+ clk => sclk40m,
+ reset => reset,
+ data_in => siHV2,
+ data_out => soHV2,
+ led_indicador => HV2_led);
+
+ ramp_ctrl3: entity work.ramp
+ generic map (
+ N => 18,
+ M => 200000,
+ P => 12
+ )
+ port map(
+ clk => sclk40m,
+ reset => reset,
+ data_in => siHV3,
+ data_out => soHV3,
+ led_indicador => HV3_led);
+
+ baseline: entity work.baseline_control
+ generic map (
+ RESET_POLARITY => RESET_POLARITY,
+ W => W,
+ ADCBITS => ADCBITS,
+ RBITS => RBITS,
+ REFRESH_RATE => REFRESH_RATE,
+ NCH => NCH
+ )
+ port map(
+ clk_40mhz => sclk40m,
+ data_adc1 => ch1,
+ data_adc2 => ch2,
+ data_adc3 => ch3,
+ baseline1 => sBL1,
+ baseline2 => sBL2,
+ baseline3 => sBL3);
+
+ comp_trigger: entity work.trigger_in
+ generic map(
+ W => W,
+ ADCBITS => ADCBITS,
+ L_ARRAY_MUESTRAS => L_ARRAY_MUESTRAS,
+ L_ARRAY_PPS => L_ARRAY_PPS,
+ L_ARRAY_SCALERS => L_ARRAY_SCALERS
+ )
+ port map(
+ clk_40mhz => sclk40m,
+ reset => reset,
+ data_adc1 => ch1,
+ data_adc2 => ch2,
+ data_adc3 => ch3,
+ trigg_set1 => sT1,
+ trigg_set2 => sT2,
+ trigg_set3 => sT3,
+ subtrigg_set1 => ssubT1,
+ subtrigg_set2 => ssubT2,
+ subtrigg_set3 => ssubT3,
+ pwr_enA => swr_fifo_A,
+ data_out => sfifo_in,
+ pfifo_status => sfifo_status(2 downto 0),
+ ptemperatura => sD2,
+ ppresion => sD1,
+ phora => shours,
+ pminutos => sminutes,
+ psegundos => sseconds,
+ pps_signal => pps_port,
+ gpsen => GPSen,
+ pps_falso_led => led(3),
+ latitude1_port => slatitude1,
+ latitude2_port => slatitude2,
+ latitude3_port => slatitude3,
+ latitude4_port => slatitude4,
+ longitude1_port => slongitude1,
+ longitude2_port => slongitude2,
+ longitude3_port => slongitude3,
+ longitude4_port => slongitude4,
+ ellipsoid1_port => sellipsoid1,
+ ellipsoid2_port => sellipsoid2,
+ ellipsoid3_port => sellipsoid3,
+ ellipsoid4_port => sellipsoid4,
+ num_vis_sat_port => sNVS,
+ num_track_sat_port => sNTS,
+ rsf_port => srsf);
+
+ hp03_controller: HP03_cntrl
+ Port map (
+ clk => clk_50m,
+ SDA => pSDA,
+ SCL => pSCL,
+ XCLR => pXCLR,
+ MCLK => pMCLK,
+ C1 => sC1,
+ C2 => sC2,
+ C3 => sC3,
+ C4 => sC4,
+ C5 => sC5,
+ C6 => sC6,
+ C7 => sC7,
+ A => sA,
+ B => sB,
+ C => sC,
+ D => sD,
+ D1 => sD1,
+ D2 => sD2);
+
+ gps_interface: Oncore_ctrl
+ port map(
+ clk => clk_50m,
+ tx_female => tx_uart,
+ rx_female => rx_uart,
+ UTCnGPS => sutcngps,
+ month_port => smonth,
+ day_port => sday,
+ year1_port => syear1,
+ year2_port => syear2,
+ hours_port => shours,
+ minutes_port => sminutes,
+ seconds_port => sseconds,
+ fract_sec1_port => sfract_sec1,
+ fract_sec2_port => sfract_sec2,
+ fract_sec3_port => sfract_sec3,
+ fract_sec4_port => sfract_sec4,
+ latitude1_port => slatitude1,
+ latitude2_port => slatitude2,
+ latitude3_port => slatitude3,
+ latitude4_port => slatitude4,
+ longitude1_port => slongitude1,
+ longitude2_port => slongitude2,
+ longitude3_port => slongitude3,
+ longitude4_port => slongitude4,
+ ellipsoid1_port => sellipsoid1,
+ ellipsoid2_port => sellipsoid2,
+ ellipsoid3_port => sellipsoid3,
+ ellipsoid4_port => sellipsoid4,
+ velocity1_port => svelocity1,
+ velocity2_port => svelocity2,
+ heading1_port => sheading1,
+ heading2_port => sheading2,
+ geometry2_port => sgeometry2,
+ DOP_type_port => sDOP_type,
+ num_vis_sat_port => sNVS,
+ num_track_sat_port => sNTS,
+
+ sat_ID1_port => ssat_ID1,
+ chtm1_port => schtm1,
+ CNo1_port => sCNo1,
+ chsf1_port => schsf1,
+
+ sat_ID2_port => ssat_ID2,
+ chtm2_port => schtm2,
+ CNo2_port => sCNo2,
+ chsf2_port => schsf2,
+
+ sat_ID3_port => ssat_ID3,
+ chtm3_port => schtm3,
+ CNo3_port => sCNo3,
+ chsf3_port => schsf3,
+
+ sat_ID4_port => ssat_ID4,
+ chtm4_port => schtm4,
+ CNo4_port => sCNo4,
+ chsf4_port => schsf4,
+
+ sat_ID5_port => ssat_ID5,
+ chtm5_port => schtm5,
+ CNo5_port => sCNo5,
+ chsf5_port => schsf5,
+
+ sat_ID6_port => ssat_ID6,
+ chtm6_port => schtm6,
+ CNo6_port => sCNo6,
+ chsf6_port => schsf6,
+
+ sat_ID7_port => ssat_ID7,
+ chtm7_port => schtm7,
+ CNo7_port => sCNo7,
+ chsf7_port => schsf7,
+
+ sat_ID8_port => ssat_ID8,
+ chtm8_port => schtm8,
+ CNo8_port => sCNo8,
+ chsf8_port => schsf8,
+
+ rsf_port => srsf);
+
+ spi_controller: interfaz_max5501
+ port map(
+ fpga_clk => clk_50m,
+ data_dac1 => sBL3,
+ data_dac2 => sBL2,
+ data_dac3 => soHV1,
+ data_dac4 => sBL1,
+ cs_e2prom => cs_e2prom,
+ cs_max5501 => cs_max5501,
+ spi_dout => spi_dout,
+ spi_sck => spi_sck);
+
+ hv2_controller: entity work.pwm
+ port map(
+ clk => clk_50m,
+ w => soHV2,
+ pwm_pulse => hv2);
+
+ hv3_controller: entity work.pwm
+ port map(
+ clk => clk_50m,
+ w => soHV3,
+ pwm_pulse => hv3);
+
+end rtl;
diff --git a/lago_fpga_vhdl.xise b/lago_fpga_vhdl.xise
new file mode 100755
index 0000000..cf9c87a
--- /dev/null
+++ b/lago_fpga_vhdl.xise
@@ -0,0 +1,404 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <header>
+ <!-- ISE source project file created by Project Navigator. -->
+ <!-- -->
+ <!-- This file contains project source information including a list of -->
+ <!-- project source files, project and process properties. This file, -->
+ <!-- along with the project source files, is sufficient to open and -->
+ <!-- implement in ISE Project Navigator. -->
+ <!-- -->
+ <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
+ </header>
+
+ <version xil_pn:ise_version="14.3" xil_pn:schema_version="2"/>
+
+ <files>
+ <file xil_pn:name="clk_40mhz.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+ </file>
+ <file xil_pn:name="dcm_200mhz.v" xil_pn:type="FILE_VERILOG">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ </file>
+ <file xil_pn:name="usb_if_ctrl.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ </file>
+ <file xil_pn:name="ipcore_dir/fifo.xco" xil_pn:type="FILE_COREGEN">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ </file>
+ <file xil_pn:name="kcpsm3.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ </file>
+ <file xil_pn:name="kcuart_rx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ </file>
+ <file xil_pn:name="kcuart_tx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ </file>
+ <file xil_pn:name="bbfifo_16x8.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ </file>
+ <file xil_pn:name="uart_rx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ </file>
+ <file xil_pn:name="uart_tx.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ </file>
+ <file xil_pn:name="GPSNFIFO.VHD" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ </file>
+ <file xil_pn:name="GPS_n_fifo.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+ </file>
+ <file xil_pn:name="HP_LAGO.VHD" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ </file>
+ <file xil_pn:name="HP03_par_control.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+ </file>
+ <file xil_pn:name="trigger.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ </file>
+ <file xil_pn:name="rampa_hv.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ </file>
+ <file xil_pn:name="baseline.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+ </file>
+ <file xil_pn:name="lago_fpga_vhdl.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+ </file>
+ <file xil_pn:name="lago_fpga_vhdl.ucf" xil_pn:type="FILE_UCF">
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ </file>
+ <file xil_pn:name="interfaz_spi.vhd" xil_pn:type="FILE_VHDL">
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+ </file>
+ </files>
+
+ <properties>
+ <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
+ <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+ <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+ <property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
+ <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="JTAG Clock" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+ <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|lago_fpga_vhdl|rtl" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top File" xil_pn:value="lago_fpga_vhdl.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/lago_fpga_vhdl" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+ <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+ <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+ <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
+ <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Output File Name" xil_pn:value="lago_ctrl" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Package" xil_pn:value="fg320" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+ <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+ <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="lago_ctrl_map.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="lago_ctrl_timesim.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="lago_ctrl_synthesis.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="lago_ctrl_translate.vhd" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+ <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
+ <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+ <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="lago_ctrl" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+ <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+ <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+ <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
+ <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+ <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+ <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+ <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+ <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+ <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+ <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+ <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+ <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+ <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
+ <!-- -->
+ <!-- The following properties are for internal use only. These should not be modified.-->
+ <!-- -->
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_DesignName" xil_pn:value="lago2" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+ <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-08-24T15:54:48" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5F437351C311185F347F9C92BDA70986" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+ </properties>
+
+ <bindings/>
+
+ <libraries/>
+
+ <autoManagedFiles>
+ <!-- The following files are identified by `include statements in verilog -->
+ <!-- source files and are automatically managed by Project Navigator. -->
+ <!-- -->
+ <!-- Do not hand-edit this section, as it will be overwritten when the -->
+ <!-- project is analyzed based on files automatically identified as -->
+ <!-- include files. -->
+ </autoManagedFiles>
+
+</project>
diff --git a/lago_fpga_vhdl.xst b/lago_fpga_vhdl.xst
new file mode 100644
index 0000000..82a9913
--- /dev/null
+++ b/lago_fpga_vhdl.xst
@@ -0,0 +1,57 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn lago_fpga_vhdl.prj
+-ifmt mixed
+-ofn lago_fpga_vhdl
+-ofmt NGC
+-p xc3s500e-4-fg320
+-top lago_fpga_vhdl
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-sd {"ipcore_dir" }
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-mux_style Auto
+-decoder_extract YES
+-priority_extract Yes
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-rom_style Auto
+-auto_bram_packing NO
+-mux_extract Yes
+-resource_sharing YES
+-async_to_sync NO
+-mult_style Auto
+-iobuf YES
+-max_fanout 500
+-bufg 24
+-register_duplication YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
diff --git a/lago_fpga_vhdl_1200.ucf b/lago_fpga_vhdl_1200.ucf
new file mode 100755
index 0000000..53d159f
--- /dev/null
+++ b/lago_fpga_vhdl_1200.ucf
@@ -0,0 +1,183 @@
+#
+#Copyright 2011 - Lab DPR (CAB-CNEA). All rights reserved.
+#
+#Redistribution and use in source and binary forms, with or without
+#modification, are permitted provided that the following conditions
+#are met:
+#
+# 1. Redistributions of source code must retain the above
+# copyright notice, this list of conditions and the following
+# disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above
+# copyright notice, this list of conditions and the following
+# disclaimer in the documentation and/or other materials
+# provided with the distribution.
+#
+#THIS SOFTWARE IS PROVIDED BY LAB DPR ''AS IS'' AND ANY EXPRESS OR IMPLIED
+#WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+#MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+#IN NO EVENT SHALL LAB DPR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+#INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+#SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+#HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+#STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+#IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+#POSSIBILITY OF SUCH DAMAGE.
+#
+#The views and conclusions contained in the software and documentation
+#are those of the authors and should not be interpreted as representing
+#official policies, either expressed or implied, of Lab DPR.
+#
+#*****************************************************************************
+
+# Clock pin for Nexys 2 Board
+NET "clk_50m" LOC = "B8";
+NET "clk_50m" TNM_NET = clk_50m;
+TIMESPEC TS_clk = PERIOD "clk_50m" 20 ns HIGH 50%;
+
+# USB Interface.
+# CY7C68013A Port A
+NET "U_SLOE" LOC = "V15" | IOSTANDARD = LVCMOS33 ; # has external pull-up
+NET "U_FIFOAD<0>" LOC = "T14" | IOSTANDARD = LVCMOS33 ;
+NET "U_FIFOAD<1>" LOC = "V13" | IOSTANDARD = LVCMOS33 ;
+NET "U_PKTEND" LOC = "V12" | IOSTANDARD = LVCMOS33 ; # no external pull-up
+
+# CY7C68013A Port B
+NET "U_FD<0>" LOC = "R14" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<1>" LOC = "R13" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<2>" LOC = "P13" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<3>" LOC = "T12" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<4>" LOC = "N11" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<5>" LOC = "R11" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<6>" LOC = "P10" | IOSTANDARD = LVCMOS33 ;
+NET "U_FD<7>" LOC = "R10" | IOSTANDARD = LVCMOS33 ;
+
+# CY7C68013A Misc
+NET "U_IFCLK" LOC = "T15" | IOSTANDARD = LVCMOS33 | PERIOD = 20.833;
+NET "U_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE; # Xilinx WebPACK version 10+ needs this.
+
+NET "U_FLAGB" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
+NET "U_FLAGC" LOC = "V16" | IOSTANDARD = LVCMOS33 ;
+
+NET "U_SLRD" LOC = "N9" | IOSTANDARD = LVCMOS33 ; # has external pull-up
+NET "U_SLWR" LOC = "V9" | IOSTANDARD = LVCMOS33 ; # has external pull-up
+
+# 7 segment display
+NET "seg<0>" LOC = "L18"; # Bank = 1, Pin name = IO_L10P_1, Type = I/O, Sch name = CA
+NET "seg<1>" LOC = "F18"; # Bank = 1, Pin name = IO_L19P_1, Type = I/O, Sch name = CB
+NET "seg<2>" LOC = "D17"; # Bank = 1, Pin name = IO_L23P_1/HDC, Type = DUAL, Sch name = CC
+NET "seg<3>" LOC = "D16"; # Bank = 1, Pin name = IO_L23N_1/LDC0, Type = DUAL, Sch name = CD
+NET "seg<4>" LOC = "G14"; # Bank = 1, Pin name = IO_L20P_1, Type = I/O, Sch name = CE
+NET "seg<5>" LOC = "J17"; # Bank = 1, Pin name = IO_L13P_1/A6/RHCLK4/IRDY1, Type = RHCLK/DUAL, Sch name = CF
+NET "seg<6>" LOC = "H14"; # Bank = 1, Pin name = IO_L17P_1, Type = I/O, Sch name = CG
+NET "dp" LOC = "C17"; # Bank = 1, Pin name = IO_L24N_1/LDC2, Type = DUAL, Sch name = DP
+#
+NET "an<0>" LOC = "F17"; # Bank = 1, Pin name = IO_L19N_1, Type = I/O, Sch name = AN0
+NET "an<1>" LOC = "H17"; # Bank = 1, Pin name = IO_L16N_1/A0, Type = DUAL, Sch name = AN1
+NET "an<2>" LOC = "C18"; # Bank = 1, Pin name = IO_L24P_1/LDC1, Type = DUAL, Sch name = AN2
+NET "an<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L21P_1, Type = I/O, Sch name = AN3
+#
+# Leds
+NET "led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+NET "led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+NET "led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+NET "led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+NET "led<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
+NET "led<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
+NET "led<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
+NET "led<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
+#NET "led<4>" LOC = "E17"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD4? s3e500 only
+#NET "led<5>" LOC = "P15"; # Bank = 1, Pin name = IO, Type = I/O, Sch name = LD5? s3e500 only
+#NET "led<6>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+#NET "led<7>" LOC = "R4"; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+
+# Leds
+#NET "led<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
+#NET "led<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
+#NET "led<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
+#NET "led<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
+#NET "led<4>" LOC = "R4" ; # Bank = 3, Pin name = IO/VREF_3, Type = VREF, Sch name = LD7? s3e500 only
+#NET "led<5>" LOC = "F4"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+#NET "led<6>" LOC = "E17"; # Bank = 3, Pin name = IO, Type = I/O, Sch name = LD6? s3e500 only
+
+#PWM Signals
+NET "hv2" LOC = "A16"; # Bank = 0, Pin name = IO_L01N_0, Type = I/O, Sch name = R-IO39
+NET "hv3" LOC = "B16"; # Bank = 0, Pin name = IO_L01P_0, Type = I/O, Sch name = R-IO40
+
+# Buttons
+NET "reset" LOC = "B18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = BTN0
+
+# FX2 connector ch1
+NET "adc_clk1" LOC = "B4";
+NET "ch1<9>" LOC = "A4";
+NET "ch1<8>" LOC = "C3";
+NET "ch1<7>" LOC = "C4";
+NET "ch1<6>" LOC = "B6";
+NET "ch1<5>" LOC = "D5";
+NET "ch1<4>" LOC = "C5";
+NET "ch1<3>" LOC = "F7";
+NET "ch1<2>" LOC = "E7";
+NET "ch1<1>" LOC = "A6";
+NET "ch1<0>" LOC = "C7";
+
+# FX2 connector ch2
+NET "adc_clk2" LOC = "F8";
+NET "ch2<9>" LOC = "D7";
+NET "ch2<8>" LOC = "E8";
+NET "ch2<7>" LOC = "E9";
+NET "ch2<6>" LOC = "C9";
+NET "ch2<5>" LOC = "A8";
+NET "ch2<4>" LOC = "G9";
+NET "ch2<3>" LOC = "F9";
+NET "ch2<2>" LOC = "D10";
+NET "ch2<1>" LOC = "A10";
+NET "ch2<0>" LOC = "B10";
+
+# FX2 connector ch3
+NET "adc_clk3" LOC = "A11";
+NET "ch3<9>" LOC = "D11";
+NET "ch3<8>" LOC = "E10";
+NET "ch3<7>" LOC = "B11";
+NET "ch3<6>" LOC = "C11";
+NET "ch3<5>" LOC = "E11";
+NET "ch3<4>" LOC = "F11";
+NET "ch3<3>" LOC = "E12";
+NET "ch3<2>" LOC = "F12";
+NET "ch3<1>" LOC = "A13";
+NET "ch3<0>" LOC = "B13";
+
+# MAX5501 Interface
+NET "cs_e2prom" LOC = "B14";
+NET "cs_max5501" LOC = "A14";
+NET "spi_dout" LOC = "C14";
+NET "spi_sck" LOC = "D14";
+
+# HP03 Interface
+# It is in JB 6 pin expansion connector
+NET "pMCLK" LOC = "R18"; # Bank = 1, Pin name = IO_L02P_1/A14, Type = DUAL, Sch name = JB2
+NET "pXCLR" LOC = "R16"; # Bank = 1, Pin name = IO_L03N_1/VREF_1, Type = VREF, Sch name = JB8
+NET "pSDA" LOC = "T18"; # Bank = 1, Pin name = IO_L02N_1/A13, Type = DUAL, Sch name = JB9
+NET "pSCL" LOC = "U18"; # Bank = 1, Pin name = IO_L01P_1/A16, Type = DUAL, Sch name = JB10
+
+# GPS Interface
+# It is in JC 6 pin expansion connector
+NET "tx_uart" LOC = "G15"; # Bank = 1, Pin name = IO_L18P_1, Type = I/O, Sch name = JC1
+NET "pps_port" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+NET "rx_uart" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+
+#Para VHP, esto es para que funcione con el cable que armé, NO con la fuente SWITCHING
+#NET "rx_uart" LOC = "G13"; # Bank = 1, Pin name = IO_L20N_1, Type = I/O, Sch name = JC3
+#NET "pps_port" LOC = "H16"; # Bank = 1, Pin name = IO_L16P_1, Type = I/O, Sch name = JC4
+#NET "tx_uart" LOC = "F14"; # Bank = 1, Pin name = IO_L21N_1, Type = I/O, Sch name = JC8
+
+
+# Switches
+NET "GPSen" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW7
+
+#GPS signals extension (for VHP telescope)
+NET "rx_uart_copy" LOC = "J13"; # Bank = 1, Pin name = IO_L15N_1/A1, Type = DUAL, Sch name = JD1
+NET "pps_port_copy" LOC = "M18"; # Bank = 1, Pin name = IO_L08N_1, Type = I/O, Sch name = JD2
+#NET "JD<2>" LOC = "N18"; # Bank = 1, Pin name = IO_L08P_1, Type = I/O, Sch name = JD3
+#NET "JD<3>" LOC = "P18"; # Bank = 1, Pin name = IO_L06N_1, Type = I/O, Sch name = JD4
diff --git a/nexys2_1200.batch b/nexys2_1200.batch
new file mode 100644
index 0000000..d20e9f4
--- /dev/null
+++ b/nexys2_1200.batch
@@ -0,0 +1,6 @@
+setMode -bs
+setCable -port xsvf -file lago_fpga_sync.xsvf
+addDevice -p 1 -file lago_fpga_sync.bit
+addDevice -p 2 -file ${XILINX}/xcf/data/xcf04s.bsd
+program -p 1
+quit
diff --git a/nexys2_500.batch b/nexys2_500.batch
new file mode 100644
index 0000000..9ffe28b
--- /dev/null
+++ b/nexys2_500.batch
@@ -0,0 +1,7 @@
+setMode -bs
+setCable -port xsvf -file lago_fpga_vhdl.xsvf
+addDevice -p 1 -file lago_fpga_vhdl.bit
+addDevice -p 2 -file ${XILINX}/xcf/data/xcf04s.bsd
+program -p 1
+quit
+
diff --git a/rampa_hv.vhd b/rampa_hv.vhd
new file mode 100644
index 0000000..9ada580
--- /dev/null
+++ b/rampa_hv.vhd
@@ -0,0 +1,107 @@
+--
+-- Copyright (C) 2012 Horacio Arnaldi
+-- e-mail: lharnaldi@cab.cnea.gov.ar
+--
+-- Laboratorio de Detección de PartÃculas y Radiación
+-- Centro Atómico Bariloche
+-- Comisión Nacional de EnergÃa Atómica (CNEA)
+-- San Carlos de Bariloche
+-- Date: 12/02/2012
+-- Ver: v0r2 --
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ramp is
+ generic(
+ N: integer := 18; -- numero de bits del contador
+ M: integer := 200000; -- mod-M
+ P: integer := 12); -- numero de bits para los datos
+ port(
+ -- Main clock
+ clk : in std_logic;
+ reset : in std_logic;
+ data_in : in std_logic_vector(P-1 downto 0);
+ data_out : out std_logic_vector(P-1 downto 0);
+ pwm_pulse : out std_logic;
+ led_indicador : out std_logic);
+end ramp;
+
+architecture rtl of ramp is
+ signal count_reg, count_next : unsigned(N-1 downto 0);
+ signal in_reg, in_next : unsigned(P-1 downto 0);
+ signal r_reg, r_next : unsigned(P-1 downto 0);
+ signal out_reg, out_next : unsigned(P-1 downto 0);
+ signal buff_reg, buff_next : std_logic;
+ signal max_tick : std_logic;
+
+begin
+ -- Drive inputs
+ in_next <= unsigned(data_in);
+
+ --registers
+ process (clk, reset)
+ begin
+ if (reset = '1') then
+ count_reg <= (others => '0');
+ in_reg <= (others => '0');
+ out_reg <= (others => '0');
+ r_reg <= (others => '0');
+ buff_reg <= '0';
+
+ elsif (clk'event and clk = '1') then
+ count_reg <= count_next;
+ r_reg <= r_next;
+ buff_reg <= buff_next;
+ in_reg <= in_next;
+ out_reg <= out_next;
+ end if;
+ end process;
+ --next-state logic for counter
+ count_next <= (others => '0') when count_reg = (M-1) else
+ count_reg + 1;
+
+ buff_next <= '1' when (r_reg < out_reg) else '0';
+
+ r_next <= r_reg + 1;
+
+ --output logic
+ max_tick <= '1' when count_reg = (M-1) else '0';
+
+ process(max_tick, in_reg, out_reg)
+ begin
+ if (max_tick = '1') then
+ if (in_reg > out_reg) then
+ out_next <= out_reg + 1;
+ elsif (in_reg < out_reg) then
+ out_next <= out_reg - 1;
+ else
+ out_next <= out_reg; -- default
+ end if;
+ else
+ out_next <= out_reg;
+ end if;
+ end process;
+
+ --next-state logic for output
+ data_out <= std_logic_vector(out_reg);
+ led_indicador <= '0' when (out_reg = 0) else
+ '1';
+ pwm_pulse <= buff_reg;
+
+end rtl;
diff --git a/spi_dac.vhd b/spi_dac.vhd
new file mode 100644
index 0000000..c7572a2
--- /dev/null
+++ b/spi_dac.vhd
@@ -0,0 +1,178 @@
+--****************************************************************************
+-- SPI_DAC.vhd
+--
+-- Horacio Arnaldi <lharnaldi@gmail.com>
+-- 20/11/2013
+--
+-- For MAX5501 DAC control.
+--
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-------------------------------------------------------------------------------
+
+entity spi_dac is -- MSB first
+ generic (
+ iCLK : boolean := false;
+ iCNV : boolean := false;
+ iDIN : boolean := false;
+ iDOU : boolean := false;
+ NB : positive := 16; -- number of bits of DAC
+ NDIV : positive := 10); -- divide the clock to get the spi clock
+ port (
+ clk : in std_logic;
+ srst : in std_logic;
+ valid : in std_logic;
+ din : in std_logic_vector(NB-1 downto 0);
+ rdy : out std_logic;
+
+ busy : out std_logic;
+
+ spi_sdo : out std_logic;
+ spi_clk : out std_logic;
+ spi_csn : out std_logic);
+end spi_dac;
+
+-------------------------------------------------------------------------------
+
+architecture arch of spi_dac is
+
+
+
+ signal bits : integer range 0 to NB-1;
+ signal bcnt : integer range 0 to NDIV-1;
+
+-- 12 data bits and 4 configuration bit.
+-- Bit 15 should be 0
+-- Bit 14 Vref 1 buffered, 0 unbuffered
+-- Bit 13 Gain 1 1x , 0 2x
+-- Bit 12 Gain 1 output enables, 0 output disabled
+
+ type sm_type is (idle, clk0, clk1, finish);
+
+ signal sm : sm_type;
+
+ signal dac : std_logic_vector(NB-1 downto 0);
+
+ signal din_i : std_logic_vector(NB-1 downto 0);
+ signal spi_cnv_i : std_logic;
+ signal spi_clk_i : std_logic;
+ signal busy_i : std_logic;
+ signal start : std_logic;
+ signal shift_out : std_logic;
+
+begin
+-- -- Data selector
+-- process (din)
+-- begin
+-- case din is --MSB - LSB
+-- when "0000" => din_i <= "0111000000000000";
+-- when "0001" => din_i <= "0111000000000001";
+-- when "0010" => din_i <= "0111000000000111";
+-- when "0011" => din_i <= "0111000000001111";
+-- when "0100" => din_i <= "0111000000011111";
+-- when "0101" => din_i <= "0111000000111111";
+-- when "0110" => din_i <= "0111000001111111";
+-- when "0111" => din_i <= "0111000011111111";
+-- when "1000" => din_i <= "0111000111111111";
+-- when "1001" => din_i <= "0111001111111111";
+-- when "1010" => din_i <= "0111011111111111";
+-- when "1011" => din_i <= "0111111111111111";
+-- when "1100" => din_i <= "0111111111110000";
+-- when "1101" => din_i <= "0111111111100000";
+-- when "1110" => din_i <= "0111111111000000";
+-- when "1111" => din_i <= "0111111110000000";
+-- when others => din_i <= "0111111100000000";
+-- end case;
+-- end process;
+
+ -- write to the DAC shift register, only if not busy!
+ -- else shift
+ process(clk)
+ begin
+ if clk'event and clk = '1' then
+ start <= '0';
+ -- write the new values to the dac registers
+ if valid = '1' and busy_i = '0' then
+ --dac <= din_i;
+ dac <= din;
+ start <= '1';
+ busy_i <= '1';
+ else
+ if shift_out = '1' then
+ dac <= dac(dac'high-1 downto 0) & dac(dac'high);
+ end if;
+ end if;
+
+ if start = '1' then
+ busy_i <= '1';
+ elsif sm = idle then
+ busy_i <= '0';
+ end if;
+
+ end if;
+ end process;
+
+ spi_sdo <= not dac(dac'high) when iDOU else dac(dac'high);
+ busy <= busy_i;
+
+ process(clk)
+ begin
+ if clk'event and clk = '1' then
+ shift_out <= '0';
+ spi_clk_i <= '1';
+ spi_cnv_i <= '1';
+ rdy <= '0';
+ if srst = '1' then
+ sm <= idle;
+ bcnt <= NDIV - 1;
+ bits <= NB-1;
+ else
+ case sm is
+ when idle =>
+ bcnt <= NDIV - 1;
+ bits <= NB - 1;
+
+ if start = '1' then
+ sm <= clk0;
+ end if;
+ when clk0 =>
+ bcnt <= bcnt - 1;
+ spi_clk_i <= '0';
+ spi_cnv_i <= '0';
+
+ if bcnt = Ndiv/2 then
+ sm <= clk1;
+ end if;
+ when clk1 =>
+ spi_cnv_i <= '0';
+ if bcnt = 0 then
+ bcnt <= Ndiv - 1;
+ if bits = 0 then
+ sm <= finish;
+ rdy <= '1';
+ else
+ sm <= clk0;
+ shift_out <= '1';
+ bits <= bits - 1;
+ end if;
+ else
+ bcnt <= bcnt - 1;
+ end if;
+
+ when finish =>
+ if bcnt = 0 then
+ sm <= idle;
+ else
+ bcnt <= bcnt - 1;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process;
+
+ spi_clk <= not spi_clk_i when iCLK else spi_clk_i;
+ spi_csn <= not spi_cnv_i when iCNV else spi_cnv_i;
+end arch;
diff --git a/trigger.vhd b/trigger.vhd
new file mode 100644
index 0000000..56081c9
--- /dev/null
+++ b/trigger.vhd
@@ -0,0 +1,455 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+--
+entity trigger_in is
+ generic(
+ W : natural; --:=5; -- numero de bits de direcciones. 2**W = 32 direcciones para W=5
+ ADCBITS : natural; -- := 10; -- numero de bits en los datos
+ L_ARRAY_MUESTRAS : natural; -- := 12;
+ L_ARRAY_PPS : natural; -- := 10;
+ L_ARRAY_SCALERS : natural --:= 3
+ );
+
+ port(
+ clk_40mhz : in std_logic;
+ reset : in std_logic;
+ data_adc1 : in std_logic_vector(ADCBITS-1 downto 0);
+ data_adc2 : in std_logic_vector(ADCBITS-1 downto 0);
+ data_adc3 : in std_logic_vector(ADCBITS-1 downto 0);
+ trigg_set1 : in std_logic_vector(ADCBITS-1 downto 0);
+ trigg_set2 : in std_logic_vector(ADCBITS-1 downto 0);
+ trigg_set3 : in std_logic_vector(ADCBITS-1 downto 0);
+ subtrigg_set1 : in std_logic_vector(ADCBITS-1 downto 0);
+ subtrigg_set2 : in std_logic_vector(ADCBITS-1 downto 0);
+ subtrigg_set3 : in std_logic_vector(ADCBITS-1 downto 0);
+ pwr_enA : out std_logic;
+ data_out : out std_logic_vector(2**W-1 downto 0);
+ pfifo_status : in std_logic_vector(2 downto 0);
+ ptemperatura : in std_logic_vector(15 downto 0);
+ ppresion : in std_logic_vector(15 downto 0);
+ phora : in std_logic_vector(7 downto 0);
+ pminutos : in std_logic_vector(7 downto 0);
+ psegundos : in std_logic_vector(7 downto 0);
+ pps_signal : in std_logic;
+ gpsen : in std_logic;
+ pps_falso_led : out std_logic;
+ latitude1_port : in std_logic_vector(7 downto 0);
+ latitude2_port : in std_logic_vector(7 downto 0);
+ latitude3_port : in std_logic_vector(7 downto 0);
+ latitude4_port : in std_logic_vector(7 downto 0);
+ longitude1_port : in std_logic_vector(7 downto 0);
+ longitude2_port : in std_logic_vector(7 downto 0);
+ longitude3_port : in std_logic_vector(7 downto 0);
+ longitude4_port : in std_logic_vector(7 downto 0);
+ ellipsoid1_port : in std_logic_vector(7 downto 0);
+ ellipsoid2_port : in std_logic_vector(7 downto 0);
+ ellipsoid3_port : in std_logic_vector(7 downto 0);
+ ellipsoid4_port : in std_logic_vector(7 downto 0);
+ num_vis_sat_port : in std_logic_vector(7 downto 0);
+ num_track_sat_port : in std_logic_vector(7 downto 0);
+ rsf_port : in std_logic_vector(7 downto 0)
+ );
+end trigger_in;
+
+architecture rtl of trigger_in is
+
+ type array_muestras_adc_type is array (L_ARRAY_MUESTRAS-1 downto 0) of
+ std_logic_vector(ADCBITS-1 downto 0);
+ signal muestras_adc1_reg, muestras_adc1_next : array_muestras_adc_type;
+ signal muestras_adc2_reg, muestras_adc2_next : array_muestras_adc_type;
+ signal muestras_adc3_reg, muestras_adc3_next : array_muestras_adc_type;
+
+ type array_pps_type is array (L_ARRAY_PPS-1 downto 0) of
+ std_logic_vector(2**W-1 downto 0);
+ signal array_pps_reg, array_pps_next : array_pps_type;
+
+ type array_scalers_type is array (L_ARRAY_SCALERS-1 downto 0) of
+ std_logic_vector(2**W-1 downto 0);
+ signal array_scalers_reg, array_scalers_next : array_scalers_type;
+
+ signal clk_para_pps_falso_reg, clk_para_pps_falso_next : unsigned(2**W-1 downto 0); -- contador para falso pps
+ signal cont_pps_reg, cont_pps_next : unsigned(15 downto 0); -- contador para pps
+ signal cont_clk_entre_pps_reg, cont_clk_entre_pps_next : unsigned(29 downto 0); -- contador de pulsos de clock entre cada PPS, se resetea en cada pps
+ signal pps, pps_falso : std_logic;
+
+ type statepps_type is (zero, edge, one);
+ signal statepps_reg, statepps_next: statepps_type;
+ signal one_clk_pps : std_logic;
+
+ signal s_tr1, s_tr2, s_tr3, s_tr : std_logic; --Triggers
+ signal s_subtr1, s_subtr2, s_subtr3, s_subtr : std_logic; --Sub-Triggers
+
+ signal tr_status_reg, tr_status_next : std_logic_vector(2**W-1 downto 0);
+ signal ctr_status_reg, ctr_status_next : std_logic_vector(2**W-1 downto 0);
+
+ signal cont_trigger_reg, cont_trigger_next : unsigned(29 downto 0); -- contador de triggers
+ signal cont_bines_reg, cont_bines_next : unsigned(2**W-1 downto 0); -- contador de bines
+
+ signal charge1_reg, charge1_next : unsigned(ADCBITS-1 downto 0);
+ signal charge2_reg, charge2_next : unsigned(ADCBITS-1 downto 0);
+ signal charge3_reg, charge3_next : unsigned(ADCBITS-1 downto 0);
+
+ type state_type is (STATE_IDLE,
+ STATE_ATT_TR,
+ STATE_SEND_TR_STATUS,
+ STATE_SEND_CTR_STATUS,
+ STATE_ATT_SUBTR,
+ STATE_ATT_PPS);
+ signal state_reg, state_next: state_type;
+
+ signal wr_count_reg, wr_count_next : unsigned(7 downto 0);
+ signal data_to_fifo_reg, data_to_fifo_next : std_logic_vector(2**W-1 downto 0);
+ signal wr_fifo_en_reg, wr_fifo_en_next : std_logic;
+ signal status : std_logic_vector(2 downto 0);
+
+begin
+
+--------------------------------------------------------------------------
+ -- PPS falso
+ -- registers
+ process(clk_40mhz, reset)
+ begin
+ if (reset = '1') then
+ clk_para_pps_falso_reg <= (others => '0'); -- Contador de clocks entre PPS's
+ cont_pps_reg <= (others => '0'); -- Contador de PPS's
+ cont_clk_entre_pps_reg <= (others => '0'); -- Contador de muestras adquiridas entre cada PPS
+ elsif (clk_40mhz'event and clk_40mhz = '1') then
+ clk_para_pps_falso_reg <= clk_para_pps_falso_next;
+ cont_pps_reg <= cont_pps_next;
+ cont_clk_entre_pps_reg <= cont_clk_entre_pps_next;
+ end if;
+ end process;
+ --next state logic
+ clk_para_pps_falso_next <= (others => '0') when (clk_para_pps_falso_reg = 39999999) else
+ clk_para_pps_falso_reg + 1;
+
+ pps_falso <= '1' when (clk_para_pps_falso_reg < 8000000) else
+ '0';
+
+ cont_pps_next <= cont_pps_reg + 1 when (one_clk_pps = '1') else
+ cont_pps_reg;
+
+ cont_clk_entre_pps_next <= (others => '0') when (one_clk_pps = '1') else
+ cont_clk_entre_pps_reg + 1;
+
+---------------------------------------------------------------------------
+
+---------------------------------------------------------------------------
+ --MUX de PPS
+ pps <= pps_falso when (gpsen = '1') else
+ pps_signal;
+
+ pps_falso_led <= pps_falso when (gpsen = '1') else
+ '0';
+---------------------------------------------------------------------------
+
+---------------------------------------------------------------------------
+ -- one clock pps: en cada pps se mantiene en alto la bandera one_clk_pps durante un ciclo de reloj de 40MHz
+ -- detector de flancos
+ -- state register
+ process(clk_40mhz,reset)
+ begin
+ if (reset='1') then
+ statepps_reg <= zero;
+ elsif (clk_40mhz'event and clk_40mhz='1') then
+ statepps_reg <= statepps_next;
+ end if;
+ end process;
+ -- next-state/output logic
+ process(statepps_reg,pps)
+ begin
+ statepps_next <= statepps_reg;
+ one_clk_pps <= '0';
+ case statepps_reg is
+ when zero=>
+ if pps= '1' then
+ statepps_next <= edge;
+ end if;
+ when edge =>
+ one_clk_pps <= '1';
+ if pps= '1' then
+ statepps_next <= one;
+ else
+ statepps_next <= zero;
+ end if;
+ when one =>
+ if pps= '0' then
+ statepps_next <= zero;
+ end if;
+ end case;
+ end process;
+
+-----------------------------------------------------------------------------
+
+-----------------------------------------------------------------------------
+
+ -- registros de datos por segundo
+ process(clk_40mhz, reset)
+ begin
+ for i in L_ARRAY_PPS-1 downto 0 loop
+ if (reset = '1') then
+ array_pps_reg(i) <= (others => '0');
+ elsif (clk_40mhz'event and clk_40mhz = '1') then
+ array_pps_reg(i) <= array_pps_next(i);
+ end if;
+ end loop;
+ end process;
+ --next state logic
+ array_pps_next(L_ARRAY_PPS-10)<= x"FFFFFFFF" when (one_clk_pps = '1') else array_pps_reg(L_ARRAY_PPS-10);
+ array_pps_next(L_ARRAY_PPS-9)<= "11" & "000" & std_logic_vector(cont_clk_entre_pps_reg(26 downto 0)) when (one_clk_pps = '1') else array_pps_reg(L_ARRAY_PPS-9);
+ array_pps_next(L_ARRAY_PPS-8)<= "11" & "001" & "00000000000" & ptemperatura when (one_clk_pps = '1') else array_pps_reg(L_ARRAY_PPS-8);
+ array_pps_next(L_ARRAY_PPS-7)<= "11" & "010" & "00000000000" & ppresion when (one_clk_pps = '1') else array_pps_reg(L_ARRAY_PPS-7);
+ array_pps_next(L_ARRAY_PPS-6)<= "11" & "011" & "000" & phora & pminutos & psegundos when (one_clk_pps = '1') else array_pps_reg(L_ARRAY_PPS-6);
+ array_pps_next(L_ARRAY_PPS-5)<= "11" & "100" & "000" & latitude1_port & latitude2_port & latitude3_port when (one_clk_pps = '1') else array_pps_reg(L_ARRAY_PPS-5);
+ array_pps_next(L_ARRAY_PPS-4)<= "11" & "100" & "001" & longitude1_port & longitude2_port & latitude4_port when (one_clk_pps = '1') else array_pps_reg(L_ARRAY_PPS-4);
+ array_pps_next(L_ARRAY_PPS-3)<= "11" & "100" & "010" & ellipsoid1_port & longitude3_port & longitude4_port when (one_clk_pps = '1') else array_pps_reg(L_ARRAY_PPS-3);
+ array_pps_next(L_ARRAY_PPS-2)<= "11" & "100" & "011" & ellipsoid2_port & ellipsoid3_port & ellipsoid4_port when (one_clk_pps = '1') else array_pps_reg(L_ARRAY_PPS-2);
+ array_pps_next(L_ARRAY_PPS-1)<= "11" & "100" & "100" & num_track_sat_port & num_vis_sat_port & rsf_port when (one_clk_pps = '1') else array_pps_reg(L_ARRAY_PPS-1);
+
+------------------------------------------------------------------------------------------------------
+
+------------------------------------------------------------------------------------------------------
+ --adquisicion de las muestras de los canales
+ process(clk_40mhz, reset)
+ begin
+ for i in (L_ARRAY_MUESTRAS-1) downto 0 loop
+ if (reset='1') then
+ muestras_adc1_reg(i) <= (others=>'0');
+ muestras_adc2_reg(i) <= (others=>'0');
+ muestras_adc3_reg(i) <= (others=>'0');
+ elsif (clk_40mhz'event and clk_40mhz='1') then
+ muestras_adc1_reg(i) <= muestras_adc1_next(i);
+ muestras_adc2_reg(i) <= muestras_adc2_next(i);
+ muestras_adc3_reg(i) <= muestras_adc3_next(i);
+ end if;
+ -- next state logic
+ if (i = (L_ARRAY_MUESTRAS-1)) then
+ muestras_adc1_next(i) <= data_adc1;
+ muestras_adc2_next(i) <= data_adc2;
+ muestras_adc3_next(i) <= data_adc3;
+ else
+ muestras_adc1_next(i) <= muestras_adc1_reg(i+1);
+ muestras_adc2_next(i) <= muestras_adc2_reg(i+1);
+ muestras_adc3_next(i) <= muestras_adc3_reg(i+1);
+ end if;
+ end loop;
+ end process;
+
+-----------------------------------------------------------------------------------------------------
+
+-----------------------------------------------------------------------------------------------------
+ --trigger
+ process(clk_40mhz, reset)
+ begin
+ if (reset='1') then
+ tr_status_reg <= (others => '0');
+ ctr_status_reg <= (others => '0');
+ cont_trigger_reg <= (others => '0');
+ elsif (clk_40mhz'event and clk_40mhz='1') then
+ tr_status_reg <= tr_status_next;
+ ctr_status_reg <= ctr_status_next;
+ cont_trigger_reg <= cont_trigger_next;
+ end if;
+ end process;
+ -- El trigger lo hago en el bin 4 porque luego pierdo un clock en la maquina de estados
+ -- next state logic
+ s_tr1 <= '1' when ((unsigned(muestras_adc1_reg(4)) >= unsigned(subtrigg_set1)) and
+ (unsigned(muestras_adc1_reg(3)) >= unsigned(trigg_set1)) and
+ (unsigned(muestras_adc1_reg(2)) < unsigned(trigg_set1)) and
+ (unsigned(muestras_adc1_reg(1)) < unsigned(trigg_set1)) ) else
+ '0';
+ s_tr2 <= '1' when ((unsigned(muestras_adc2_reg(4)) >= unsigned(subtrigg_set2)) and
+ (unsigned(muestras_adc2_reg(3)) >= unsigned(trigg_set2)) and
+ (unsigned(muestras_adc2_reg(2)) < unsigned(trigg_set2)) and
+ (unsigned(muestras_adc2_reg(1)) < unsigned(trigg_set2)) ) else
+ '0';
+ s_tr3 <= '1' when ((unsigned(muestras_adc3_reg(4)) >= unsigned(subtrigg_set3)) and
+ (unsigned(muestras_adc3_reg(3)) >= unsigned(trigg_set3)) and
+ (unsigned(muestras_adc3_reg(2)) < unsigned(trigg_set3)) and
+ (unsigned(muestras_adc3_reg(1)) < unsigned(trigg_set3)) ) else
+ '0';
+ s_tr <= '1' when ((s_tr1 = '1') or
+ (s_tr2 = '1') or
+ (s_tr3 = '1') ) else
+ '0';
+
+ tr_status_next <= "01" & s_tr3 & s_tr2 & s_tr1 & std_logic_vector(cont_clk_entre_pps_reg(26 downto 0)) when (s_tr = '1') else
+ tr_status_reg;
+ ctr_status_next <= "10" & std_logic_vector(cont_trigger_reg) when (s_tr = '1') else
+ ctr_status_reg;
+
+ cont_trigger_next <= cont_trigger_reg + 1 when (s_tr = '1') else
+ cont_trigger_reg;
+
+----------------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------------
+ --scalers
+ -- sub-trigger: se controla que tengamos un subtrigger y que no tengamos un trigger en los proximos dos clocks
+ process(clk_40mhz, reset)
+ begin
+ if (reset='1') then
+ charge1_reg <= (others => '0');
+ charge2_reg <= (others => '0');
+ charge3_reg <= (others => '0');
+ array_scalers_reg(L_ARRAY_SCALERS-1) <= (others => '0');
+ array_scalers_reg(L_ARRAY_SCALERS-2) <= (others => '0');
+ array_scalers_reg(L_ARRAY_SCALERS-3) <= (others => '0');
+ elsif (clk_40mhz'event and clk_40mhz='1') then
+ charge1_reg <= charge1_next;
+ charge2_reg <= charge2_next;
+ charge3_reg <= charge3_next;
+ array_scalers_reg(L_ARRAY_SCALERS-1) <= array_scalers_reg(L_ARRAY_SCALERS-1);
+ array_scalers_reg(L_ARRAY_SCALERS-2) <= array_scalers_reg(L_ARRAY_SCALERS-2);
+ array_scalers_reg(L_ARRAY_SCALERS-3) <= array_scalers_reg(L_ARRAY_SCALERS-3);
+ end if;
+ end process;
+ -- next state logic
+ --s_subtr1 <= '1' when unsigned(muestras_adc1_reg(2)) >= unsigned(subtrigg_set1) and
+ s_subtr1 <= '1' when unsigned(muestras_adc1_reg(2)) > to_unsigned(1023, muestras_adc1_reg'length) and
+ unsigned(muestras_adc1_reg(1)) < unsigned(muestras_adc1_reg(2)) and
+ (unsigned(muestras_adc1_reg(3)) < unsigned(muestras_adc1_reg(2)) or
+ (unsigned(muestras_adc1_reg(3)) = unsigned(muestras_adc1_reg(2)) and
+ unsigned(muestras_adc1_reg(4)) < unsigned(muestras_adc1_reg(2)))) and
+ unsigned(muestras_adc1_reg(2)) < unsigned(trigg_set1) and
+ unsigned(muestras_adc1_reg(3)) < unsigned(trigg_set1) and
+ unsigned(muestras_adc1_reg(4)) < unsigned(trigg_set1) else
+ '0';
+ --s_subtr2 <= '1' when unsigned(muestras_adc2_reg(2)) >= unsigned(subtrigg_set2) and
+ s_subtr2 <= '1' when unsigned(muestras_adc2_reg(2)) > to_unsigned(1023, muestras_adc2_reg'length) and
+ unsigned(muestras_adc2_reg(1)) < unsigned(muestras_adc2_reg(2)) and
+ (unsigned(muestras_adc2_reg(3)) < unsigned(muestras_adc2_reg(2)) or
+ (unsigned(muestras_adc2_reg(3)) = unsigned(muestras_adc2_reg(2)) and
+ unsigned(muestras_adc2_reg(4)) < unsigned(muestras_adc2_reg(2)))) and
+ unsigned(muestras_adc2_reg(2)) < unsigned(trigg_set2) and
+ unsigned(muestras_adc2_reg(3)) < unsigned(trigg_set2) and
+ unsigned(muestras_adc2_reg(4)) < unsigned(trigg_set2) else
+ '0';
+ --s_subtr3 <= '1' when unsigned(muestras_adc3_reg(2)) >= unsigned(subtrigg_set3) and
+ s_subtr3 <= '1' when unsigned(muestras_adc3_reg(2)) > to_unsigned(1023, muestras_adc3_reg'length) and
+ unsigned(muestras_adc3_reg(1)) < unsigned(muestras_adc3_reg(2)) and
+ (unsigned(muestras_adc3_reg(3)) < unsigned(muestras_adc3_reg(2)) or
+ (unsigned(muestras_adc3_reg(3)) = unsigned(muestras_adc3_reg(2)) and
+ unsigned(muestras_adc3_reg(4)) < unsigned(muestras_adc3_reg(2)))) and
+ unsigned(muestras_adc3_reg(2)) < unsigned(trigg_set3) and
+ unsigned(muestras_adc3_reg(3)) < unsigned(trigg_set3) and
+ unsigned(muestras_adc3_reg(4)) < unsigned(trigg_set3) else
+ '0';
+ s_subtr <= '1' when ( (s_subtr1 = '1') or (s_subtr2 = '1') or (s_subtr3 = '1') ) else
+ '0';
+ charge1_next <= charge1_reg + muestras_adc1_reg'left - muestras_adc1_reg'right;
+ charge2_next <= charge2_reg + muestras_adc2_reg'left - muestras_adc2_reg'right;
+ charge3_next <= charge3_reg + muestras_adc3_reg'left - muestras_adc3_reg'right;
+
+ array_scalers_next(L_ARRAY_SCALERS-1) <= "01" & s_subtr3 & s_subtr2 & s_subtr1 & std_logic_vector(cont_clk_entre_pps_reg(26 downto 0)) when (s_subtr = '1') else
+ array_scalers_reg(L_ARRAY_SCALERS-1);
+ array_scalers_next(L_ARRAY_SCALERS-2) <= "00" & std_logic_vector(charge1_reg) & std_logic_vector(charge2_reg) & std_logic_vector(charge3_reg) when (s_subtr = '1') else
+ array_scalers_reg(L_ARRAY_SCALERS-2); --valores de carga por canal
+ array_scalers_next(L_ARRAY_SCALERS-3) <= "00" & muestras_adc1_reg(2) & muestras_adc2_reg(2) & muestras_adc3_reg(2) when (s_subtr = '1') else
+ array_scalers_reg(L_ARRAY_SCALERS-3); --se manda el maximo del pulso tambien
+
+----------------------------------------------------------------------------------------------------------------
+
+----------------------------------------------------------------------------------------------------------------
+ -- FSM que controla todo
+ --================================================================
+-- state and data registers
+--================================================================
+ process (clk_40mhz, reset)
+ begin
+ if (reset = '1') then
+ state_reg <= STATE_IDLE;
+ wr_fifo_en_reg <= '0';
+ wr_count_reg <= (others => '0');
+ data_to_fifo_reg <= (others => '0');
+ elsif (clk_40mhz'event and clk_40mhz = '1') then
+ state_reg <= state_next;
+ wr_fifo_en_reg <= wr_fifo_en_next;
+ wr_count_reg <= wr_count_next;
+ data_to_fifo_reg <= data_to_fifo_next;
+ end if;
+ end process;
+--=================================================================
+--next-state logic & data path functional units/routing
+--=================================================================
+ --process(state_reg, s_tr, s_subtr, one_clk_pps, wr_count_reg, pfifo_status)
+ process(state_reg, status, wr_count_reg, pfifo_status)
+ begin
+ state_next <= state_reg; -- default volver al estado inicial
+ wr_fifo_en_next <= '0'; -- default deshabilitar la escritura en la fifo
+ wr_count_next <= (others => '0');
+ data_to_fifo_next <= data_to_fifo_reg; --default mantener el valor
+ case state_reg is
+ when STATE_IDLE =>
+ if (pfifo_status(2) = '0') then -- si la FIFO no esta llena pfifo_status <= full & pfull & empy
+ case status is
+ when "001" | "011" | "101" | "111" => -- le doy prioridad a la escritura de los datos pps cada segundo
+ state_next <= STATE_ATT_PPS;
+ when "100" | "110" =>
+ state_next <= STATE_ATT_TR;
+ when "010" =>
+ state_next <= STATE_ATT_SUBTR;
+ when others => --"000"
+ state_next <= STATE_IDLE;
+ end case;
+-- if s_tr = '1' then
+-- state_next <= STATE_ATT_TR;
+-- elsif s_subtr = '1' then
+-- state_next <= STATE_ATT_SUBTR;
+-- elsif one_clk_pps = '1' then
+-- state_next <= STATE_ATT_PPS;
+-- end if;
+ else
+ state_next <= STATE_IDLE;
+ end if;
+
+ when STATE_ATT_TR =>
+ wr_fifo_en_next <= '1';
+ wr_count_next <= wr_count_reg + 1;
+ data_to_fifo_next <= "00" & muestras_adc1_reg(0) & muestras_adc2_reg(0) & muestras_adc3_reg(0);
+ if (wr_count_reg = (L_ARRAY_MUESTRAS - 1)) then
+ state_next <= STATE_SEND_TR_STATUS;
+ else
+ state_next <= STATE_ATT_TR;
+ end if;
+
+ when STATE_SEND_TR_STATUS =>
+ wr_fifo_en_next <= '1';
+ data_to_fifo_next <= tr_status_reg;
+ state_next <= STATE_SEND_CTR_STATUS;
+
+ when STATE_SEND_CTR_STATUS =>
+ wr_fifo_en_next <= '1';
+ data_to_fifo_next <= ctr_status_reg;
+ state_next <= STATE_IDLE;
+
+ when STATE_ATT_SUBTR =>
+ wr_fifo_en_next <= '1';
+ wr_count_next <= wr_count_reg + 1;
+ data_to_fifo_next <= array_scalers_reg(to_integer(wr_count_reg));
+ if (wr_count_reg = (L_ARRAY_SCALERS - 1)) then
+ state_next <= STATE_IDLE;
+ else
+ state_next <= STATE_ATT_SUBTR;
+ end if;
+
+ when STATE_ATT_PPS =>
+ wr_fifo_en_next <= '1';
+ wr_count_next <= wr_count_reg + 1;
+ data_to_fifo_next <= array_pps_reg(to_integer(wr_count_reg));
+ if (wr_count_reg = (L_ARRAY_PPS - 1)) then
+ state_next <= STATE_IDLE;
+ else
+ state_next <= STATE_ATT_PPS;
+ end if;
+ end case;
+ end process;
+
+ status <= s_tr & s_subtr & one_clk_pps;
+ data_out <= data_to_fifo_reg;
+ pwr_enA <= wr_fifo_en_reg;
+
+
+end architecture rtl;
+
diff --git a/uart_rx.vhd b/uart_rx.vhd
new file mode 100644
index 0000000..b1374e6
--- /dev/null
+++ b/uart_rx.vhd
@@ -0,0 +1,146 @@
+-- UART Receiver with integral 16 byte FIFO buffer
+--
+-- 8 bit, no parity, 1 stop bit
+--
+-- Version : 1.00
+-- Version Date : 16th October 2002
+--
+-- Start of design entry : 16th October 2002
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Futhermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for UART_RX
+--
+entity uart_rx is
+ Port ( serial_in : in std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ read_buffer : in std_logic;
+ reset_buffer : in std_logic;
+ en_16_x_baud : in std_logic;
+ buffer_data_present : out std_logic;
+ buffer_full : out std_logic;
+ buffer_half_full : out std_logic;
+ clk : in std_logic);
+ end uart_rx;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for UART_RX
+--
+architecture macro_level_definition of uart_rx is
+--
+------------------------------------------------------------------------------------
+--
+-- Components used in UART_RX and defined in subsequent entities.
+--
+------------------------------------------------------------------------------------
+--
+-- Constant (K) Compact UART Receiver
+--
+component kcuart_rx
+ Port ( serial_in : in std_logic;
+ data_out : out std_logic_vector(7 downto 0);
+ data_strobe : out std_logic;
+ en_16_x_baud : in std_logic;
+ clk : in std_logic);
+ end component;
+--
+-- 'Bucket Brigade' FIFO
+--
+component bbfifo_16x8
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ reset : in std_logic;
+ write : in std_logic;
+ read : in std_logic;
+ full : out std_logic;
+ half_full : out std_logic;
+ data_present : out std_logic;
+ clk : in std_logic);
+ end component;
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in UART_RX
+--
+------------------------------------------------------------------------------------
+--
+signal uart_data_out : std_logic_vector(7 downto 0);
+signal fifo_write : std_logic;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of UART_RX circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+
+ -- 8 to 1 multiplexer to convert parallel data to serial
+
+ kcuart: kcuart_rx
+ port map ( serial_in => serial_in,
+ data_out => uart_data_out,
+ data_strobe => fifo_write,
+ en_16_x_baud => en_16_x_baud,
+ clk => clk );
+
+
+ buf: bbfifo_16x8
+ port map ( data_in => uart_data_out,
+ data_out => data_out,
+ reset => reset_buffer,
+ write => fifo_write,
+ read => read_buffer,
+ full => buffer_full,
+ half_full => buffer_half_full,
+ data_present => buffer_data_present,
+ clk => clk);
+
+end macro_level_definition;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE UART_RX.VHD
+--
+------------------------------------------------------------------------------------
+
+
diff --git a/uart_tx.vhd b/uart_tx.vhd
new file mode 100644
index 0000000..4018c92
--- /dev/null
+++ b/uart_tx.vhd
@@ -0,0 +1,148 @@
+-- UART Transmitter with integral 16 byte FIFO buffer
+--
+-- 8 bit, no parity, 1 stop bit
+--
+-- Version : 1.00
+-- Version Date : 14th October 2002
+--
+-- Start of design entry : 14th October 2002
+--
+-- Ken Chapman
+-- Xilinx Ltd
+-- Benchmark House
+-- 203 Brooklands Road
+-- Weybridge
+-- Surrey KT13 ORH
+-- United Kingdom
+--
+-- chapman@xilinx.com
+--
+------------------------------------------------------------------------------------
+--
+-- NOTICE:
+--
+-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
+-- third parties. By providing this core as one possible implementation of a standard,
+-- Xilinx is making no representation that the provided implementation of this standard
+-- is free from any claims of infringement by any third party. Xilinx expressly
+-- disclaims any warranty with respect to the adequacy of the implementation, including
+-- but not limited to any warranty or representation that the implementation is free
+-- from claims of any third party. Futhermore, Xilinx is providing this core as a
+-- courtesy to you and suggests that you contact all third parties to obtain the
+-- necessary rights to use this implementation.
+--
+------------------------------------------------------------------------------------
+--
+-- Library declarations
+--
+-- The Unisim Library is used to define Xilinx primitives. It is also used during
+-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
+--
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+library unisim;
+use unisim.vcomponents.all;
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for UART_TX
+--
+entity uart_tx is
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ write_buffer : in std_logic;
+ reset_buffer : in std_logic;
+ en_16_x_baud : in std_logic;
+ serial_out : out std_logic;
+ buffer_full : out std_logic;
+ buffer_half_full : out std_logic;
+ clk : in std_logic);
+ end uart_tx;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of Main Architecture for UART_TX
+--
+architecture macro_level_definition of uart_tx is
+--
+------------------------------------------------------------------------------------
+--
+-- Components used in UART_TX and defined in subsequent entities.
+--
+------------------------------------------------------------------------------------
+--
+-- Constant (K) Compact UART Transmitter
+--
+component kcuart_tx
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ send_character : in std_logic;
+ en_16_x_baud : in std_logic;
+ serial_out : out std_logic;
+ Tx_complete : out std_logic;
+ clk : in std_logic);
+ end component;
+--
+-- 'Bucket Brigade' FIFO
+--
+component bbfifo_16x8
+ Port ( data_in : in std_logic_vector(7 downto 0);
+ data_out : out std_logic_vector(7 downto 0);
+ reset : in std_logic;
+ write : in std_logic;
+ read : in std_logic;
+ full : out std_logic;
+ half_full : out std_logic;
+ data_present : out std_logic;
+ clk : in std_logic);
+ end component;
+--
+------------------------------------------------------------------------------------
+--
+-- Signals used in UART_TX
+--
+------------------------------------------------------------------------------------
+--
+signal fifo_data_out : std_logic_vector(7 downto 0);
+signal fifo_data_present : std_logic;
+signal fifo_read : std_logic;
+--
+------------------------------------------------------------------------------------
+--
+-- Start of UART_TX circuit description
+--
+------------------------------------------------------------------------------------
+--
+begin
+
+ -- 8 to 1 multiplexer to convert parallel data to serial
+
+ kcuart: kcuart_tx
+ port map ( data_in => fifo_data_out,
+ send_character => fifo_data_present,
+ en_16_x_baud => en_16_x_baud,
+ serial_out => serial_out,
+ Tx_complete => fifo_read,
+ clk => clk);
+
+
+ buf: bbfifo_16x8
+ port map ( data_in => data_in,
+ data_out => fifo_data_out,
+ reset => reset_buffer,
+ write => write_buffer,
+ read => fifo_read,
+ full => buffer_full,
+ half_full => buffer_half_full,
+ data_present => fifo_data_present,
+ clk => clk);
+
+end macro_level_definition;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE UART_TX.VHD
+--
+------------------------------------------------------------------------------------
+
+
diff --git a/usb_if_ctrl.vhd b/usb_if_ctrl.vhd
new file mode 100644
index 0000000..7a9b952
--- /dev/null
+++ b/usb_if_ctrl.vhd
@@ -0,0 +1,1144 @@
+--
+-- Copyright (C) 2011 Horacio Arnaldi
+-- e-mail: lharnaldi@cab.cnea.gov.ar
+--
+-- Laboratorio de Detección de PartÃculas y Radiación
+-- Centro Atómico Bariloche
+-- Comisión Nacional de EnergÃa Atómica (CNEA)
+-- San Carlos de Bariloche
+-- Date: 25/09/2011
+-- Ver: v2r0 --
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity usb_if_ctrl is
+ generic(
+ VER : natural;
+ REV : natural;
+ RESET_POLARITY : std_logic);
+ port(
+ -- Reset button (BTN0)
+ reset : in std_logic;
+
+ u_ifclk : in std_logic;
+
+ -- Data & control from the FX2
+ u_fd : inout std_logic_vector(7 downto 0);
+ u_flagc : in std_logic; -- FLAGC=EF (active-low), so '1' when there's data
+ u_flagb : in std_logic; -- FLAGB=FF (active-low), so '1' when there's room
+
+ -- Control to the FX2
+ u_sloe : out std_logic; -- PA2
+ u_slrd : out std_logic;
+ u_slwr : out std_logic;
+ u_fifoad : out std_logic_vector(1 downto 0); -- PA4 & PA5
+ u_pktend : out std_logic; -- PA6
+
+ -- Lago Board interface
+ -- Ports for settings
+ T1, T2, T3 : out std_logic_vector(9 downto 0);
+ subT1, subT2, subT3 : out std_logic_vector(9 downto 0);
+ BL1, BL2, BL3 : in std_logic_vector(11 downto 0); -- DAC
+ HV1 : out std_logic_vector(11 downto 0); -- DAC
+ HV2, HV3 : out std_logic_vector(11 downto 0); --PWM
+
+ -- Inputs for data
+ clk40m : in std_logic; --fifo's in clk
+ fifo_A : in std_logic_vector(31 downto 0);
+ -- Enables for fifos
+ we_A : in std_logic;
+ -- Data input for HP03
+ pC1, pC2, pC3, pC4, pC5 : in std_logic_vector(15 downto 0);
+ pC6, pC7, pD1, pD2 : in std_logic_vector(15 downto 0);
+ pA, pB, pC, pD : in std_logic_vector(7 downto 0);
+
+ -- GPS receiver data
+ UTCnGPS : out std_logic;
+ month_port : in std_logic_vector(7 downto 0);
+ day_port : in std_logic_vector(7 downto 0);
+ year1_port : in std_logic_vector(7 downto 0);
+ year2_port : in std_logic_vector(7 downto 0);
+ hours_port : in std_logic_vector(7 downto 0);
+ minutes_port : in std_logic_vector(7 downto 0);
+ seconds_port : in std_logic_vector(7 downto 0);
+ fract_sec1_port : in std_logic_vector(7 downto 0);
+ fract_sec2_port : in std_logic_vector(7 downto 0);
+ fract_sec3_port : in std_logic_vector(7 downto 0);
+ fract_sec4_port : in std_logic_vector(7 downto 0);
+ latitude1_port : in std_logic_vector(7 downto 0);
+ latitude2_port : in std_logic_vector(7 downto 0);
+ latitude3_port : in std_logic_vector(7 downto 0);
+ latitude4_port : in std_logic_vector(7 downto 0);
+ longitude1_port : in std_logic_vector(7 downto 0);
+ longitude2_port : in std_logic_vector(7 downto 0);
+ longitude3_port : in std_logic_vector(7 downto 0);
+ longitude4_port : in std_logic_vector(7 downto 0);
+ ellipsoid1_port : in std_logic_vector(7 downto 0);
+ ellipsoid2_port : in std_logic_vector(7 downto 0);
+ ellipsoid3_port : in std_logic_vector(7 downto 0);
+ ellipsoid4_port : in std_logic_vector(7 downto 0);
+ velocity1_port : in std_logic_vector(7 downto 0);
+ velocity2_port : in std_logic_vector(7 downto 0);
+ heading1_port : in std_logic_vector(7 downto 0);
+ heading2_port : in std_logic_vector(7 downto 0);
+ geometry2_port : in std_logic_vector(7 downto 0);
+ DOP_type_port : in std_logic_vector(7 downto 0);
+ num_vis_sat_port : in std_logic_vector(7 downto 0);
+ num_track_sat_port: in std_logic_vector(7 downto 0);
+
+ sat_ID1_port : in std_logic_vector(7 downto 0);
+ chtm1_port : in std_logic_vector(7 downto 0);
+ CNo1_port : in std_logic_vector(7 downto 0);
+ chsf1_port : in std_logic_vector(7 downto 0);
+
+ sat_ID2_port : in std_logic_vector(7 downto 0);
+ chtm2_port : in std_logic_vector(7 downto 0);
+ CNo2_port : in std_logic_vector(7 downto 0);
+ chsf2_port : in std_logic_vector(7 downto 0);
+
+ sat_ID3_port : in std_logic_vector(7 downto 0);
+ chtm3_port : in std_logic_vector(7 downto 0);
+ CNo3_port : in std_logic_vector(7 downto 0);
+ chsf3_port : in std_logic_vector(7 downto 0);
+
+ sat_ID4_port : in std_logic_vector(7 downto 0);
+ chtm4_port : in std_logic_vector(7 downto 0);
+ CNo4_port : in std_logic_vector(7 downto 0);
+ chsf4_port : in std_logic_vector(7 downto 0);
+
+ sat_ID5_port : in std_logic_vector(7 downto 0);
+ chtm5_port : in std_logic_vector(7 downto 0);
+ CNo5_port : in std_logic_vector(7 downto 0);
+ chsf5_port : in std_logic_vector(7 downto 0);
+
+ sat_ID6_port : in std_logic_vector(7 downto 0);
+ chtm6_port : in std_logic_vector(7 downto 0);
+ CNo6_port : in std_logic_vector(7 downto 0);
+ chsf6_port : in std_logic_vector(7 downto 0);
+
+ sat_ID7_port : in std_logic_vector(7 downto 0);
+ chtm7_port : in std_logic_vector(7 downto 0);
+ CNo7_port : in std_logic_vector(7 downto 0);
+ chsf7_port : in std_logic_vector(7 downto 0);
+
+ sat_ID8_port : in std_logic_vector(7 downto 0);
+ chtm8_port : in std_logic_vector(7 downto 0);
+ CNo8_port : in std_logic_vector(7 downto 0);
+ chsf8_port : in std_logic_vector(7 downto 0);
+
+ rsf_port : in std_logic_vector(7 downto 0);
+
+ --Fifo status port
+ pfifo_status : out std_logic_vector(7 downto 0)
+ );
+end usb_if_ctrl;
+
+architecture sync of usb_if_ctrl is
+
+ component fifo
+ port(
+ din : in std_logic_vector(31 downto 0);
+ rd_clk : in std_logic;
+ rd_en : in std_logic;
+ wr_clk : in std_logic;
+ wr_en : in std_logic;
+ dout : out std_logic_vector(7 downto 0);
+ rst : in std_logic;
+ empty : out std_logic;
+ full : out std_logic;
+ prog_full: OUT std_logic);
+ end component;
+
+ attribute box_type : string;
+ attribute box_type of fifo : component is "black_box";
+
+ type StateType is (
+ STATE_IDLE,
+ STATE_GET_COUNT0,
+ STATE_GET_COUNT1,
+ STATE_GET_COUNT2,
+ STATE_GET_COUNT3,
+ STATE_BEGIN_WRITE,
+ STATE_WRITE,
+ STATE_END_WRITE_ALIGNED,
+ STATE_END_WRITE_NONALIGNED,
+ STATE_READ);
+
+ signal state, state_next : StateType;
+ signal count, count_next : unsigned(31 downto 0); -- Read/Write count
+ signal addr, addr_next : std_logic_vector(6 downto 0);
+ signal isWrite, isWrite_next : std_logic;
+ signal isAligned, isAligned_next: std_logic;
+ signal fifoOp : std_logic_vector(2 downto 0);
+ constant FIFO_READ : std_logic_vector(2 downto 0) := "100"; -- assert u_slrd & u_sloe
+ constant FIFO_WRITE : std_logic_vector(2 downto 0) := "011"; -- assert u_slwr
+ constant FIFO_NOP : std_logic_vector(2 downto 0) := "111"; -- assert nothing
+ constant OUT_FIFO : std_logic_vector(1 downto 0) := "10"; -- EP6OUT
+ constant IN_FIFO : std_logic_vector(1 downto 0) := "11"; -- EP8IN
+
+ -- FIFO read/write enables, and data to be mux'd back to host
+ signal iReadEnable_A : std_logic;
+ signal iFifoData_A : std_logic_vector(7 downto 0);
+
+ -- HP03 inputs
+ signal sC1_msb, sNext_sC1_msb : std_logic_vector(7 downto 0);
+ signal sC1_lsb, sNext_sC1_lsb : std_logic_vector(7 downto 0);
+ signal sC2_msb, sNext_sC2_msb : std_logic_vector(7 downto 0);
+ signal sC2_lsb, sNext_sC2_lsb : std_logic_vector(7 downto 0);
+ signal sC3_msb, sNext_sC3_msb : std_logic_vector(7 downto 0);
+ signal sC3_lsb, sNext_sC3_lsb : std_logic_vector(7 downto 0);
+ signal sC4_msb, sNext_sC4_msb : std_logic_vector(7 downto 0);
+ signal sC4_lsb, sNext_sC4_lsb : std_logic_vector(7 downto 0);
+ signal sC5_msb, sNext_sC5_msb : std_logic_vector(7 downto 0);
+ signal sC5_lsb, sNext_sC5_lsb : std_logic_vector(7 downto 0);
+ signal sC6_msb, sNext_sC6_msb : std_logic_vector(7 downto 0);
+ signal sC6_lsb, sNext_sC6_lsb : std_logic_vector(7 downto 0);
+ signal sC7_msb, sNext_sC7_msb : std_logic_vector(7 downto 0);
+ signal sC7_lsb, sNext_sC7_lsb : std_logic_vector(7 downto 0);
+ signal sA, sNext_sA : std_logic_vector(7 downto 0);
+ signal sB, sNext_sB : std_logic_vector(7 downto 0);
+ signal sC, sNext_sC : std_logic_vector(7 downto 0);
+ signal sD, sNext_sD : std_logic_vector(7 downto 0);
+ signal sD1_msb, sNext_sD1_msb : std_logic_vector(7 downto 0);
+ signal sD1_lsb, sNext_sD1_lsb : std_logic_vector(7 downto 0);
+ signal sD2_msb, sNext_sD2_msb : std_logic_vector(7 downto 0);
+ signal sD2_lsb, sNext_sD2_lsb : std_logic_vector(7 downto 0);
+
+ -- GPS fifo signals
+ signal smonth, sNext_month : std_logic_vector(7 downto 0);
+ signal sday, sNext_day : std_logic_vector(7 downto 0);
+ signal syear1, sNext_year1 : std_logic_vector(7 downto 0);
+ signal syear2, sNext_year2 : std_logic_vector(7 downto 0);
+ signal shours, sNext_hours : std_logic_vector(7 downto 0);
+ signal sminutes, sNext_minutes : std_logic_vector(7 downto 0);
+ signal sseconds, sNext_seconds : std_logic_vector(7 downto 0);
+ signal sfract_sec1, sNext_fract_sec1 : std_logic_vector(7 downto 0);
+ signal sfract_sec2, sNext_fract_sec2 : std_logic_vector(7 downto 0);
+ signal sfract_sec3, sNext_fract_sec3 : std_logic_vector(7 downto 0);
+ signal sfract_sec4, sNext_fract_sec4 : std_logic_vector(7 downto 0);
+ signal slatitude1, sNext_latitude1 : std_logic_vector(7 downto 0);
+ signal slatitude2, sNext_latitude2 : std_logic_vector(7 downto 0);
+ signal slatitude3, sNext_latitude3 : std_logic_vector(7 downto 0);
+ signal slatitude4, sNext_latitude4 : std_logic_vector(7 downto 0);
+ signal slongitude1, sNext_longitude1 : std_logic_vector(7 downto 0);
+ signal slongitude2, sNext_longitude2 : std_logic_vector(7 downto 0);
+ signal slongitude3, sNext_longitude3 : std_logic_vector(7 downto 0);
+ signal slongitude4, sNext_longitude4 : std_logic_vector(7 downto 0);
+ signal sellipsoid1, sNext_ellipsoid1 : std_logic_vector(7 downto 0);
+ signal sellipsoid2, sNext_ellipsoid2 : std_logic_vector(7 downto 0);
+ signal sellipsoid3, sNext_ellipsoid3 : std_logic_vector(7 downto 0);
+ signal sellipsoid4, sNext_ellipsoid4 : std_logic_vector(7 downto 0);
+ signal svelocity1, sNext_velocity1 : std_logic_vector(7 downto 0);
+ signal svelocity2, sNext_velocity2 : std_logic_vector(7 downto 0);
+ signal sheading1, sNext_heading1 : std_logic_vector(7 downto 0);
+ signal sheading2, sNext_heading2 : std_logic_vector(7 downto 0);
+ signal sgeometry2, sNext_geometry2 : std_logic_vector(7 downto 0);
+ signal sDOP_type, sNext_DOP_type : std_logic_vector(7 downto 0);
+ signal sNVS, sNext_NVS : std_logic_vector(7 downto 0);
+ signal sNTS, sNext_NTS : std_logic_vector(7 downto 0);
+ signal ssat_ID1, sNext_sat_ID1 : std_logic_vector(7 downto 0);
+ signal schtm1, sNext_chtm1 : std_logic_vector(7 downto 0);
+ signal sCNo1, sNext_CNo1 : std_logic_vector(7 downto 0);
+ signal schsf1, sNext_chsf1 : std_logic_vector(7 downto 0);
+ signal ssat_ID2, sNext_sat_ID2 : std_logic_vector(7 downto 0);
+ signal schtm2, sNext_chtm2 : std_logic_vector(7 downto 0);
+ signal sCNo2, sNext_CNo2 : std_logic_vector(7 downto 0);
+ signal schsf2, sNext_chsf2 : std_logic_vector(7 downto 0);
+ signal ssat_ID3, sNext_sat_ID3 : std_logic_vector(7 downto 0);
+ signal schtm3, sNext_chtm3 : std_logic_vector(7 downto 0);
+ signal sCNo3, sNext_CNo3 : std_logic_vector(7 downto 0);
+ signal schsf3, sNext_chsf3 : std_logic_vector(7 downto 0);
+ signal ssat_ID4, sNext_sat_ID4 : std_logic_vector(7 downto 0);
+ signal schtm4, sNext_chtm4 : std_logic_vector(7 downto 0);
+ signal sCNo4, sNext_CNo4 : std_logic_vector(7 downto 0);
+ signal schsf4, sNext_chsf4 : std_logic_vector(7 downto 0);
+ signal ssat_ID5, sNext_sat_ID5 : std_logic_vector(7 downto 0);
+ signal schtm5, sNext_chtm5 : std_logic_vector(7 downto 0);
+ signal sCNo5, sNext_CNo5 : std_logic_vector(7 downto 0);
+ signal schsf5, sNext_chsf5 : std_logic_vector(7 downto 0);
+ signal ssat_ID6, sNext_sat_ID6 : std_logic_vector(7 downto 0);
+ signal schtm6, sNext_chtm6 : std_logic_vector(7 downto 0);
+ signal sCNo6, sNext_CNo6 : std_logic_vector(7 downto 0);
+ signal schsf6, sNext_chsf6 : std_logic_vector(7 downto 0);
+ signal ssat_ID7, sNext_sat_ID7 : std_logic_vector(7 downto 0);
+ signal schtm7, sNext_chtm7 : std_logic_vector(7 downto 0);
+ signal sCNo7, sNext_CNo7 : std_logic_vector(7 downto 0);
+ signal schsf7, sNext_chsf7 : std_logic_vector(7 downto 0);
+ signal ssat_ID8, sNext_sat_ID8 : std_logic_vector(7 downto 0);
+ signal schtm8, sNext_chtm8 : std_logic_vector(7 downto 0);
+ signal sCNo8, sNext_CNo8 : std_logic_vector(7 downto 0);
+ signal schsf8, sNext_chsf8 : std_logic_vector(7 downto 0);
+ signal srsf, sNext_rsf : std_logic_vector(7 downto 0);
+ signal sutcngps, sNextutcngps : std_logic_vector(7 downto 0);
+
+
+ -- Registers
+ signal iR0, iNextR0 : std_logic_vector(7 downto 0); --reserved
+ signal iT1_msb, iNext_T1_msb : std_logic_vector(7 downto 0); --1
+ signal iT1_lsb, iNext_T1_lsb : std_logic_vector(7 downto 0); --2
+ signal iT2_msb, iNext_T2_msb : std_logic_vector(7 downto 0); --3
+ signal iT2_lsb, iNext_T2_lsb : std_logic_vector(7 downto 0); --4
+ signal iT3_msb, iNext_T3_msb : std_logic_vector(7 downto 0); --5
+ signal iT3_lsb, iNext_T3_lsb : std_logic_vector(7 downto 0); --6
+ signal isubT1_msb, iNext_subT1_msb : std_logic_vector(7 downto 0); --7
+ signal isubT1_lsb, iNext_subT1_lsb : std_logic_vector(7 downto 0); --8
+ signal isubT2_msb, iNext_subT2_msb : std_logic_vector(7 downto 0); --9
+ signal isubT2_lsb, iNext_subT2_lsb : std_logic_vector(7 downto 0); --10
+ signal isubT3_msb, iNext_subT3_msb : std_logic_vector(7 downto 0); --11
+ signal isubT3_lsb, iNext_subT3_lsb : std_logic_vector(7 downto 0); --12
+ signal iBL1_msb, iNext_BL1_msb : std_logic_vector(7 downto 0); --13
+ signal iBL1_lsb, iNext_BL1_lsb : std_logic_vector(7 downto 0); --14
+ signal iBL2_msb, iNext_BL2_msb : std_logic_vector(7 downto 0); --15
+ signal iBL2_lsb, iNext_BL2_lsb : std_logic_vector(7 downto 0); --16
+ signal iBL3_msb, iNext_BL3_msb : std_logic_vector(7 downto 0); --17
+ signal iBL3_lsb, iNext_BL3_lsb : std_logic_vector(7 downto 0); --18
+ signal iHV1_msb, iNext_HV1_msb : std_logic_vector(7 downto 0); --19
+ signal iHV1_lsb, iNext_HV1_lsb : std_logic_vector(7 downto 0); --20
+ signal iHV2_msb, iNext_HV2_msb : std_logic_vector(7 downto 0); --21
+ signal iHV2_lsb, iNext_HV2_lsb : std_logic_vector(7 downto 0); --22
+ signal iHV3_msb, iNext_HV3_msb : std_logic_vector(7 downto 0); --23
+ signal iHV3_lsb, iNext_HV3_lsb : std_logic_vector(7 downto 0); --24
+ signal irstatus, iNext_rstatus : std_logic_vector(7 downto 0); --25
+
+ -- HP03 fifo status
+ signal iVerID, iNext_iVerID : std_logic_vector(7 downto 0); --26
+ -- GPS fifo status
+ signal iRevID, iNext_iRevID : std_logic_vector(7 downto 0); --27
+ signal sfull_A : std_logic;
+ signal sempty_A : std_logic;
+ signal spf_A : std_logic; -- prog full A and B
+
+begin
+
+ -- Drive mixed signals...
+ pfifo_status <= "00000" & sfull_A & spf_A & sempty_A;
+ iNext_rstatus <= spf_A & "0" & sfull_A & "000" & sempty_A & "0";
+ iNext_iVerID <= std_logic_vector(to_unsigned(VER, 8)); -- Actual Soft Version
+ iNext_iRevID <= std_logic_vector(to_unsigned(REV, 8)); -- Actual Soft Revision
+ UTCnGPS <= sutcngps(0);
+ -- Drive module outputs
+ -- Trigger levels
+ T1 <= iT1_msb(1 downto 0) & iT1_lsb;
+ T2 <= iT2_msb(1 downto 0) & iT2_lsb;
+ T3 <= iT3_msb(1 downto 0) & iT3_lsb;
+ -- subTrigger levels
+ subT1 <= isubT1_msb(1 downto 0) & isubT1_lsb;
+ subT2 <= isubT2_msb(1 downto 0) & isubT2_lsb;
+ subT3 <= isubT3_msb(1 downto 0) & isubT3_lsb;
+ iNext_BL1_msb <= x"0" & BL1(11 downto 8);
+ iNext_BL1_lsb <= BL1(7 downto 0);
+ iNext_BL2_msb <= x"0" & BL2(11 downto 8);
+ iNext_BL2_lsb <= BL2(7 downto 0);
+ iNext_BL3_msb <= x"0" & BL3(11 downto 8);
+ iNext_BL3_lsb <= BL3(7 downto 0);
+
+ -- High Voltages
+ HV1 <= iHV1_msb(3 downto 0) & iHV1_lsb;
+ HV2 <= iHV2_msb(3 downto 0) & iHV2_lsb;
+ HV3 <= iHV3_msb(3 downto 0) & iHV3_lsb;
+
+ -- Drive HP03 inputs
+ sNext_sC1_msb <= pC1(15 downto 8);
+ sNext_sC1_lsb <= pC1(7 downto 0);
+ sNext_sC2_msb <= pC2(15 downto 8);
+ sNext_sC2_lsb <= pC2(7 downto 0);
+ sNext_sC3_msb <= pC3(15 downto 8);
+ sNext_sC3_lsb <= pC3(7 downto 0);
+ sNext_sC4_msb <= pC4(15 downto 8);
+ sNext_sC4_lsb <= pC4(7 downto 0);
+ sNext_sC5_msb <= pC5(15 downto 8);
+ sNext_sC5_lsb <= pC5(7 downto 0);
+ sNext_sC6_msb <= pC6(15 downto 8);
+ sNext_sC6_lsb <= pC6(7 downto 0);
+ sNext_sC7_msb <= pC7(15 downto 8);
+ sNext_sC7_lsb <= pC7(7 downto 0);
+ sNext_sA <= pA;
+ sNext_sB <= pB;
+ sNext_sC <= pC;
+ sNext_sD <= pD;
+ sNext_sD1_msb <= pD1(15 downto 8);
+ sNext_sD1_lsb <= pD1(7 downto 0);
+ sNext_sD2_msb <= pD2(15 downto 8);
+ sNext_sD2_lsb <= pD2(7 downto 0);
+
+ -- Drive GPS inputs
+ sNext_month <= month_port;
+ sNext_day <= day_port;
+ sNext_year1 <= year1_port;
+ sNext_year2 <= year2_port;
+ sNext_hours <= hours_port;
+ sNext_minutes <= minutes_port;
+ sNext_seconds <= seconds_port;
+ sNext_fract_sec1<= fract_sec1_port;
+ sNext_fract_sec2<= fract_sec2_port;
+ sNext_fract_sec3<= fract_sec3_port;
+ sNext_fract_sec4<= fract_sec4_port;
+ sNext_latitude1 <= latitude1_port;
+ sNext_latitude2 <= latitude2_port;
+ sNext_latitude3 <= latitude3_port;
+ sNext_latitude4 <= latitude4_port;
+ sNext_longitude1<= longitude1_port;
+ sNext_longitude2<= longitude2_port;
+ sNext_longitude3<= longitude3_port;
+ sNext_longitude4<= longitude4_port;
+ sNext_ellipsoid1<= ellipsoid1_port;
+ sNext_ellipsoid2<= ellipsoid2_port;
+ sNext_ellipsoid3<= ellipsoid3_port;
+ sNext_ellipsoid4<= ellipsoid4_port;
+ sNext_velocity1 <= velocity1_port;
+ sNext_velocity2 <= velocity2_port;
+ sNext_heading1 <= heading1_port;
+ sNext_heading2 <= heading2_port;
+ sNext_geometry2 <= geometry2_port;
+ sNext_DOP_type <= DOP_type_port;
+ sNext_NVS <= num_vis_sat_port;
+ sNext_NTS <= num_track_sat_port;
+ sNext_sat_ID1 <= sat_ID1_port;
+ sNext_chtm1 <= chtm1_port;
+ sNext_CNo1 <= CNo1_port;
+ sNext_chsf1 <= chsf1_port;
+ sNext_sat_ID2 <= sat_ID2_port;
+ sNext_chtm2 <= chtm2_port;
+ sNext_CNo2 <= CNo2_port;
+ sNext_chsf2 <= chsf2_port;
+ sNext_sat_ID3 <= sat_ID3_port;
+ sNext_chtm3 <= chtm3_port;
+ sNext_CNo3 <= CNo3_port;
+ sNext_chsf3 <= chsf3_port;
+ sNext_sat_ID4 <= sat_ID4_port;
+ sNext_chtm4 <= chtm4_port;
+ sNext_CNo4 <= CNo4_port;
+ sNext_chsf4 <= chsf4_port;
+ sNext_sat_ID5 <= sat_ID5_port;
+ sNext_chtm5 <= chtm5_port;
+ sNext_CNo5 <= CNo5_port;
+ sNext_chsf5 <= chsf5_port;
+ sNext_sat_ID6 <= sat_ID6_port;
+ sNext_chtm6 <= chtm6_port;
+ sNext_CNo6 <= CNo6_port;
+ sNext_chsf6 <= chsf6_port;
+ sNext_sat_ID7 <= sat_ID7_port;
+ sNext_chtm7 <= chtm7_port;
+ sNext_CNo7 <= CNo7_port;
+ sNext_chsf7 <= chsf7_port;
+ sNext_sat_ID8 <= sat_ID8_port;
+ sNext_chtm8 <= chtm8_port;
+ sNext_CNo8 <= CNo8_port;
+ sNext_chsf8 <= chsf8_port;
+ sNext_rsf <= rsf_port;
+ --End of GPS signals
+
+ --FIFO's
+ fifoA : fifo
+ port map(
+ din => fifo_A,
+ rd_clk => u_ifclk,
+ rd_en => iReadEnable_A,
+ wr_clk => clk40m,
+ wr_en => we_A,
+ dout => iFifoData_A,
+ rst => reset,
+ empty => sempty_A,
+ full => sfull_A,
+ prog_full => spf_A
+ );
+
+ -- Infer registers
+ process(u_ifclk, reset)
+ begin
+ if ( reset = RESET_POLARITY) then
+ state <= STATE_IDLE;
+ count <= (others => '0');
+ addr <= (others => '0');
+ isWrite <= '0';
+ isAligned <= '0';
+ iR0 <= (others => '0');
+ iT1_msb <= x"03";
+ iT1_lsb <= x"E8";
+ iT2_msb <= x"03";
+ iT2_lsb <= x"E8";
+ iT3_msb <= x"03";
+ iT3_lsb <= x"E8";
+ isubT1_msb <= x"03";
+ isubT1_lsb <= x"E8";
+ isubT2_msb <= x"03";
+ isubT2_lsb <= x"E8";
+ isubT3_msb <= x"03";
+ isubT3_lsb <= x"E8";
+ iBL1_msb <= (others => '0');
+ iBL1_lsb <= (others => '0');
+ iBL2_msb <= (others => '0');
+ iBL2_lsb <= (others => '0');
+ iBL3_msb <= (others => '0');
+ iBL3_lsb <= (others => '0');
+ iHV1_msb <= (others => '0');
+ iHV1_lsb <= (others => '0');
+ iHV2_msb <= (others => '0');
+ iHV2_lsb <= (others => '0');
+ iHV3_msb <= (others => '0');
+ iHV3_lsb <= (others => '0');
+ irstatus <= (others => '0');
+ --HP03 signals
+ sC1_msb <= (others => '0');
+ sC1_lsb <= (others => '0');
+ sC2_msb <= (others => '0');
+ sC2_lsb <= (others => '0');
+ sC3_msb <= (others => '0');
+ sC3_lsb <= (others => '0');
+ sC4_msb <= (others => '0');
+ sC4_lsb <= (others => '0');
+ sC5_msb <= (others => '0');
+ sC5_lsb <= (others => '0');
+ sC6_msb <= (others => '0');
+ sC6_lsb <= (others => '0');
+ sC7_msb <= (others => '0');
+ sC7_lsb <= (others => '0');
+ sA <= (others => '0');
+ sB <= (others => '0');
+ sC <= (others => '0');
+ sD <= (others => '0');
+ sD1_msb <= (others => '0');
+ sD1_lsb <= (others => '0');
+ sD2_msb <= (others => '0');
+ sD2_lsb <= (others => '0');
+ --GPS signals
+ smonth <= (others => '0');
+ sday <= (others => '0');
+ syear1 <= (others => '0');
+ syear2 <= (others => '0');
+ shours <= (others => '0');
+ sminutes <= (others => '0');
+ sseconds <= (others => '0');
+ sfract_sec1 <= (others => '0');
+ sfract_sec2 <= (others => '0');
+ sfract_sec3 <= (others => '0');
+ sfract_sec4 <= (others => '0');
+ slatitude1 <= (others => '0');
+ slatitude2 <= (others => '0');
+ slatitude3 <= (others => '0');
+ slatitude4 <= (others => '0');
+ slongitude1 <= (others => '0');
+ slongitude2 <= (others => '0');
+ slongitude3 <= (others => '0');
+ slongitude4 <= (others => '0');
+ sellipsoid1 <= (others => '0');
+ sellipsoid2 <= (others => '0');
+ sellipsoid3 <= (others => '0');
+ sellipsoid4 <= (others => '0');
+ svelocity1 <= (others => '0');
+ svelocity2 <= (others => '0');
+ sheading1 <= (others => '0');
+ sheading2 <= (others => '0');
+ sgeometry2 <= (others => '0');
+ sDOP_type <= (others => '0');
+ sNVS <= (others => '0');
+ sNTS <= (others => '0');
+ ssat_ID1 <= (others => '0');
+ schtm1 <= (others => '0');
+ sCNo1 <= (others => '0');
+ schsf1 <= (others => '0');
+ ssat_ID2 <= (others => '0');
+ schtm2 <= (others => '0');
+ sCNo2 <= (others => '0');
+ schsf2 <= (others => '0');
+ ssat_ID3 <= (others => '0');
+ schtm3 <= (others => '0');
+ sCNo3 <= (others => '0');
+ schsf3 <= (others => '0');
+ ssat_ID4 <= (others => '0');
+ schtm4 <= (others => '0');
+ sCNo4 <= (others => '0');
+ schsf4 <= (others => '0');
+ ssat_ID5 <= (others => '0');
+ schtm5 <= (others => '0');
+ sCNo5 <= (others => '0');
+ schsf5 <= (others => '0');
+ ssat_ID6 <= (others => '0');
+ schtm6 <= (others => '0');
+ sCNo6 <= (others => '0');
+ schsf6 <= (others => '0');
+ ssat_ID7 <= (others => '0');
+ schtm7 <= (others => '0');
+ sCNo7 <= (others => '0');
+ schsf7 <= (others => '0');
+ ssat_ID8 <= (others => '0');
+ schtm8 <= (others => '0');
+ sCNo8 <= (others => '0');
+ schsf8 <= (others => '0');
+ srsf <= (others => '0');
+ sutcngps <= (others => '0');
+
+ elsif rising_edge(u_ifclk) then
+ state <= state_next;
+ count <= count_next;
+ addr <= addr_next;
+ isWrite <= isWrite_next;
+ isAligned <= isAligned_next;
+ iR0 <= iNextR0;
+ iT1_msb <= iNext_T1_msb;
+ iT1_lsb <= iNext_T1_lsb;
+ iT2_msb <= iNext_T2_msb;
+ iT2_lsb <= iNext_T2_lsb;
+ iT3_msb <= iNext_T3_msb;
+ iT3_lsb <= iNext_T3_lsb;
+ isubT1_msb <= iNext_subT1_msb;
+ isubT1_lsb <= iNext_subT1_lsb;
+ isubT2_msb <= iNext_subT2_msb;
+ isubT2_lsb <= iNext_subT2_lsb;
+ isubT3_msb <= iNext_subT3_msb;
+ isubT3_lsb <= iNext_subT3_lsb;
+ iBL1_msb <= iNext_BL1_msb;
+ iBL1_lsb <= iNext_BL1_lsb;
+ iBL2_msb <= iNext_BL2_msb;
+ iBL2_lsb <= iNext_BL2_lsb;
+ iBL3_msb <= iNext_BL3_msb;
+ iBL3_lsb <= iNext_BL3_lsb;
+ iHV1_msb <= iNext_HV1_msb;
+ iHV1_lsb <= iNext_HV1_lsb;
+ iHV2_msb <= iNext_HV2_msb;
+ iHV2_lsb <= iNext_HV2_lsb;
+ iHV3_msb <= iNext_HV3_msb;
+ iHV3_lsb <= iNext_HV3_lsb;
+ irstatus <= iNext_rstatus;
+ --HP03 signals
+ sC1_msb <= sNext_sC1_msb;
+ sC1_lsb <= sNext_sC1_lsb;
+ sC2_msb <= sNext_sC2_msb;
+ sC2_lsb <= sNext_sC2_lsb;
+ sC3_msb <= sNext_sC3_msb;
+ sC3_lsb <= sNext_sC3_lsb;
+ sC4_msb <= sNext_sC4_msb;
+ sC4_lsb <= sNext_sC4_lsb;
+ sC5_msb <= sNext_sC5_msb;
+ sC5_lsb <= sNext_sC5_lsb;
+ sC6_msb <= sNext_sC6_msb;
+ sC6_lsb <= sNext_sC6_lsb;
+ sC7_msb <= sNext_sC7_msb;
+ sC7_lsb <= sNext_sC7_lsb;
+ sA <= sNext_sA;
+ sB <= sNext_sB;
+ sC <= sNext_sC;
+ sD <= sNext_sD;
+ sD1_msb <= sNext_sD1_msb;
+ sD1_lsb <= sNext_sD1_lsb;
+ sD2_msb <= sNext_sD2_msb;
+ sD2_lsb <= sNext_sD2_lsb;
+ --GPS signals
+ smonth <= sNext_month;
+ sday <= sNext_day;
+ syear1 <= sNext_year1;
+ syear2 <= sNext_year2;
+ shours <= sNext_hours;
+ sminutes <= sNext_minutes;
+ sseconds <= sNext_seconds;
+ sfract_sec1 <= sNext_fract_sec1;
+ sfract_sec2 <= sNext_fract_sec2;
+ sfract_sec3 <= sNext_fract_sec3;
+ sfract_sec4 <= sNext_fract_sec4;
+ slatitude1 <= sNext_latitude1;
+ slatitude2 <= sNext_latitude2;
+ slatitude3 <= sNext_latitude3;
+ slatitude4 <= sNext_latitude4;
+ slongitude1 <= sNext_longitude1;
+ slongitude2 <= sNext_longitude2;
+ slongitude3 <= sNext_longitude3;
+ slongitude4 <= sNext_longitude4;
+ sellipsoid1 <= sNext_ellipsoid1;
+ sellipsoid2 <= sNext_ellipsoid2;
+ sellipsoid3 <= sNext_ellipsoid3;
+ sellipsoid4 <= sNext_ellipsoid4;
+ svelocity1 <= sNext_velocity1;
+ svelocity2 <= sNext_velocity2;
+ sheading1 <= sNext_heading1;
+ sheading2 <= sNext_heading2;
+ sgeometry2 <= sNext_geometry2;
+ sDOP_type <= sNext_DOP_type;
+ sNVS <= sNext_NVS;
+ sNTS <= sNext_NTS;
+ ssat_ID1 <= sNext_sat_ID1;
+ schtm1 <= sNext_chtm1;
+ sCNo1 <= sNext_CNo1;
+ schsf1 <= sNext_chsf1;
+ ssat_ID2 <= sNext_sat_ID2;
+ schtm2 <= sNext_chtm2;
+ sCNo2 <= sNext_CNo2;
+ schsf2 <= sNext_chsf2;
+ ssat_ID3 <= sNext_sat_ID3;
+ schtm3 <= sNext_chtm3;
+ sCNo3 <= sNext_CNo3;
+ schsf3 <= sNext_chsf3;
+ ssat_ID4 <= sNext_sat_ID4;
+ schtm4 <= sNext_chtm4;
+ sCNo4 <= sNext_CNo4;
+ schsf4 <= sNext_chsf4;
+ ssat_ID5 <= sNext_sat_ID5;
+ schtm5 <= sNext_chtm5;
+ sCNo5 <= sNext_CNo5;
+ schsf5 <= sNext_chsf5;
+ ssat_ID6 <= sNext_sat_ID6;
+ schtm6 <= sNext_chtm6;
+ sCNo6 <= sNext_CNo6;
+ schsf6 <= sNext_chsf6;
+ ssat_ID7 <= sNext_sat_ID7;
+ schtm7 <= sNext_chtm7;
+ sCNo7 <= sNext_CNo7;
+ schsf7 <= sNext_chsf7;
+ ssat_ID8 <= sNext_sat_ID8;
+ schtm8 <= sNext_chtm8;
+ sCNo8 <= sNext_CNo8;
+ schsf8 <= sNext_chsf8;
+ srsf <= sNext_rsf;
+ sutcngps <= sNextutcngps;
+ iVerID <= iNext_iVerID;
+ iRevID <= iNext_iRevID;
+ end if;
+ end process;
+
+ -- Next state logic
+ process(
+ state, u_fd, u_flagc, u_flagb, count, isAligned, isWrite, addr,
+
+ iR0, iT1_msb, iT1_lsb, iT2_msb, iT2_lsb, iT3_msb, iT3_lsb,
+ isubT1_msb, isubT1_lsb, isubT2_msb, isubT2_lsb, isubT3_msb,
+ isubT3_lsb, iBL1_msb, iBL1_lsb, iBL2_msb, iBL2_lsb, iBL3_msb,
+ iBL3_lsb, iHV1_msb, iHV1_lsb, iHV2_msb, iHV2_lsb, iHV3_msb,
+ iHV3_lsb, irstatus, iVerID, iRevID, sutcngps)
+ begin
+ state_next <= state;
+ count_next <= count;
+ addr_next <= addr;
+ isWrite_next <= isWrite;
+ isAligned_next <= isAligned; -- does this FIFO write end on a block (512-byte) boundary?
+ u_fd <= (others => 'Z'); -- Tristated unless explicitly driven
+ fifoOp <= FIFO_READ; -- read the FX2LP FIFO by default
+ u_pktend <= '1'; -- inactive: FPGA does not commit a short packet.
+
+ iNextR0 <= iR0;
+ iNext_T1_msb <= iT1_msb;
+ iNext_T1_lsb <= iT1_lsb;
+ iNext_T2_msb <= iT2_msb;
+ iNext_T2_lsb <= iT2_lsb;
+ iNext_T3_msb <= iT3_msb;
+ iNext_T3_lsb <= iT3_lsb;
+ iNext_subT1_msb <= isubT1_msb;
+ iNext_subT1_lsb <= isubT1_lsb;
+ iNext_subT2_msb <= isubT2_msb;
+ iNext_subT2_lsb <= isubT2_lsb;
+ iNext_subT3_msb <= isubT3_msb;
+ iNext_subT3_lsb <= isubT3_lsb;
+ iNext_HV1_msb <= iHV1_msb;
+ iNext_HV1_lsb <= iHV1_lsb;
+ iNext_HV2_msb <= iHV2_msb;
+ iNext_HV2_lsb <= iHV2_lsb;
+ iNext_HV3_msb <= iHV3_msb;
+ iNext_HV3_lsb <= iHV3_lsb;
+ sNextutcngps <= sutcngps;
+ -- No read from FIFO
+ iReadEnable_A <= '0';
+
+ case state is
+ when STATE_IDLE =>
+ u_fifoad <= OUT_FIFO; -- Reading from FX2LP
+ if ( u_flagc = '1' ) then
+ -- The read/write flag and a seven-bit register address
+ -- will be available on the next clock edge.
+ addr_next <= u_fd(6 downto 0);
+ isWrite_next <= u_fd(7);
+ state_next <= STATE_GET_COUNT0;
+ end if;
+
+ when STATE_GET_COUNT0 =>
+ u_fifoad <= OUT_FIFO; -- Reading from FX2LP
+ if ( u_flagc = '1' ) then
+ -- The count high word high byte will be available on the
+ -- next clock edge.
+ count_next(31 downto 24) <= unsigned(u_fd);
+ state_next <= STATE_GET_COUNT1;
+ end if;
+
+ when STATE_GET_COUNT1 =>
+ u_fifoad <= OUT_FIFO; -- Reading from FX2LP
+ if ( u_flagc = '1' ) then
+ -- The count high word low byte will be available on the
+ -- next clock edge.
+ count_next(23 downto 16) <= unsigned(u_fd);
+ state_next <= STATE_GET_COUNT2;
+ end if;
+
+ when STATE_GET_COUNT2 =>
+ u_fifoad <= OUT_FIFO; -- Reading from FX2LP
+ if ( u_flagc = '1' ) then
+ -- The count low word high byte will be available on the
+ -- next clock edge.
+ count_next(15 downto 8) <= unsigned(u_fd);
+ state_next <= STATE_GET_COUNT3;
+ end if;
+
+ when STATE_GET_COUNT3 =>
+ u_fifoad <= OUT_FIFO; -- Reading from FX2LP
+ if ( u_flagc = '1' ) then
+ -- The count low word low byte will be available on the
+ -- next clock edge.
+ count_next(7 downto 0) <= unsigned(u_fd);
+ if ( isWrite = '1' ) then
+ state_next <= STATE_BEGIN_WRITE;
+ else
+ state_next <= STATE_READ;
+ end if;
+ end if;
+
+ when STATE_BEGIN_WRITE =>
+ u_fifoad <= IN_FIFO; -- Writing to FX2LP
+ fifoOp <= FIFO_NOP;
+ isAligned_next <= not(count(0) or count(1) or count(2) or count(3)
+ or count(4) or count(5) or count(6) or count(7)
+ or count(8));
+ state_next <= STATE_WRITE;
+
+ when STATE_WRITE =>
+ u_fifoad <= IN_FIFO; -- Writing to FX2LP
+ if ( u_flagb = '1' ) then
+ fifoOp <= FIFO_WRITE;
+ case addr is
+ when "0000000" => --reserved
+ u_fd <= iR0;
+ when "0000001" => --1
+ u_fd <= iT1_msb;
+ when "0000010" => --2
+ u_fd <= iT1_lsb;
+ when "0000011" => --3
+ u_fd <= iT2_msb;
+ when "0000100" => --4
+ u_fd <= iT2_lsb;
+ when "0000101" => --5
+ u_fd <= iT3_msb;
+ when "0000110" => --6
+ u_fd <= iT3_lsb;
+ when "0000111" => --7
+ u_fd <= isubT1_msb;
+ when "0001000" => --8
+ u_fd <= isubT1_lsb;
+ when "0001001" => --9
+ u_fd <= isubT2_msb;
+ when "0001010" => --10
+ u_fd <= isubT2_lsb;
+ when "0001011" => --11
+ u_fd <= isubT3_msb;
+ when "0001100" => --12
+ u_fd <= isubT3_lsb;
+ when "0001101" => --13
+ u_fd <= iBL1_msb;
+ when "0001110" => --14
+ u_fd <= iBL1_lsb;
+ when "0001111" => --15
+ u_fd <= iBL2_msb;
+ when "0010000" => --16
+ u_fd <= iBL2_lsb;
+ when "0010001" => --17
+ u_fd <= iBL3_msb;
+ when "0010010" => --18
+ u_fd <= iBL3_lsb;
+ when "0010011" => --19
+ u_fd <= iHV1_msb;
+ when "0010100" => --20
+ u_fd <= iHV1_lsb;
+ when "0010101" => --21
+ u_fd <= iHV2_msb;
+ when "0010110" => --22
+ u_fd <= iHV2_lsb;
+ when "0010111" => --23
+ u_fd <= iHV3_msb;
+ when "0011000" => --24
+ u_fd <= iHV3_lsb;
+ when "0011001" => --25
+ u_fd <= sutcngps;
+ when "0011010" => --26
+ u_fd <= irstatus;
+ when "0011011" => --27
+ iReadEnable_A <= '1'; -- Enable read FIFO
+ u_fd <= iFifoData_A; -- Read FIFO A when addr=1B
+ --HP03 signals
+ when "0011101" => --29
+ u_fd <= sC1_msb;
+ when "0011110" => --30
+ u_fd <= sC1_lsb;
+ when "0011111" => --31
+ u_fd <= sC2_msb;
+ when "0100000" => --32
+ u_fd <= sC2_lsb;
+ when "0100001" => --33
+ u_fd <= sC3_msb;
+ when "0100010" => --34
+ u_fd <= sC3_lsb;
+ when "0100011" => --35
+ u_fd <= sC4_msb;
+ when "0100100" => --36
+ u_fd <= sC4_lsb;
+ when "0100101" => --37
+ u_fd <= sC5_msb;
+ when "0100110" => --38
+ u_fd <= sC5_lsb;
+ when "0100111" => --39
+ u_fd <= sC6_msb;
+ when "0101000" => --40
+ u_fd <= sC6_lsb;
+ when "0101001" => --41
+ u_fd <= sC7_msb;
+ when "0101010" => --42
+ u_fd <= sC7_lsb;
+ when "0101011" => --43
+ u_fd <= sA;
+ when "0101100" => --44
+ u_fd <= sB;
+ when "0101101" => --45
+ u_fd <= sC;
+ when "0101110" => --46
+ u_fd <= sD;
+ when "0101111" => --47
+ u_fd <= sD1_msb;
+ when "0110000" => --48
+ u_fd <= sD1_lsb;
+ when "0110001" => --49
+ u_fd <= sD2_msb;
+ when "0110010" => --50
+ u_fd <= sD2_lsb;
+ --GPS signals
+ when "0110011" => --51
+ u_fd <= smonth;
+ when "0110100" => --52
+ u_fd <= sday;
+ when "0110101" => --53
+ u_fd <= syear1;
+ when "0110110" => --54
+ u_fd <= syear2;
+ when "0110111" => --55
+ u_fd <= shours;
+ when "0111000" => --56
+ u_fd <= sminutes;
+ when "0111001" => --57
+ u_fd <= sseconds;
+ when "0111010" => --58
+ u_fd <= sfract_sec1;
+ when "0111011" => --59
+ u_fd <= sfract_sec2;
+ when "0111100" => --60
+ u_fd <= sfract_sec3;
+ when "0111101" => --61
+ u_fd <= sfract_sec4;
+ when "0111110" => --62
+ u_fd <= slatitude1;
+ when "0111111" => --63
+ u_fd <= slatitude2;
+ when "1000000" => --64
+ u_fd <= slatitude3;
+ when "1000001" => --65
+ u_fd <= slatitude4;
+ when "1000010" => --66
+ u_fd <= slongitude1;
+ when "1000011" => --67
+ u_fd <= slongitude2;
+ when "1000100" => --68
+ u_fd <= slongitude3;
+ when "1000101" => --69
+ u_fd <= slongitude4;
+ when "1000110" => --70
+ u_fd <= sellipsoid1;
+ when "1000111" => --71
+ u_fd <= sellipsoid2;
+ when "1001000" => --72
+ u_fd <= sellipsoid3;
+ when "1001001" => --73
+ u_fd <= sellipsoid4;
+ when "1001010" => --74
+ u_fd <= svelocity1;
+ when "1001011" => --75
+ u_fd <= svelocity2;
+ when "1001100" => --76
+ u_fd <= sheading1;
+ when "1001101" => --77
+ u_fd <= sheading2;
+ when "1001110" => --78
+ u_fd <= sgeometry2;
+ when "1001111" => --79
+ u_fd <= sDOP_type;
+ when "1010000" => --80
+ u_fd <= sNVS;
+ when "1010001" => --81
+ u_fd <= sNTS;
+ when "1010010" => --82
+ u_fd <= ssat_ID1;
+ when "1010011" => --83
+ u_fd <= schtm1;
+ when "1010100" => --84
+ u_fd <= sCNo1;
+ when "1010101" => --85
+ u_fd <= schsf1;
+ when "1010110" => --86
+ u_fd <= ssat_ID2;
+ when "1010111" => --87
+ u_fd <= schtm2;
+ when "1011000" => --88
+ u_fd <= sCNo2;
+ when "1011001" => --89
+ u_fd <= schsf2;
+ when "1011010" => --90
+ u_fd <= ssat_ID3;
+ when "1011011" => --91
+ u_fd <= schtm3;
+ when "1011100" => --92
+ u_fd <= sCNo3;
+ when "1011101" => --93
+ u_fd <= schsf3;
+ when "1011110" => --94
+ u_fd <= ssat_ID4;
+ when "1011111" => --95
+ u_fd <= schtm4;
+ when "1100000" => --96
+ u_fd <= sCNo4;
+ when "1100001" => --97
+ u_fd <= schsf4;
+ when "1100010" => --98
+ u_fd <= ssat_ID5;
+ when "1100011" => --99
+ u_fd <= schtm5;
+ when "1100100" => --100
+ u_fd <= sCNo5;
+ when "1100101" => --101
+ u_fd <= schsf5;
+ when "1100110" => --102
+ u_fd <= ssat_ID6;
+ when "1100111" => --103
+ u_fd <= schtm6;
+ when "1101000" => --104
+ u_fd <= sCNo6;
+ when "1101001" => --105
+ u_fd <= schsf6;
+ when "1101010" => --106
+ u_fd <= ssat_ID7;
+ when "1101011" => --107
+ u_fd <= schtm7;
+ when "1101100" => --108
+ u_fd <= sCNo7;
+ when "1101101" => --109
+ u_fd <= schsf7;
+ when "1101110" => --110
+ u_fd <= ssat_ID8;
+ when "1101111" => --111
+ u_fd <= schtm8;
+ when "1110000" => --112
+ u_fd <= sCNo8;
+ when "1110001" => --113
+ u_fd <= schsf8;
+ when "1110010" => --114
+ u_fd <= srsf;
+ when "1110011" => --115
+ u_fd <= iVerID;
+ when "1110100" => --116
+ u_fd <= iRevID;
+ when others =>
+ u_fd <= "00000000";
+ end case;
+ count_next <= count - 1;
+ if ( count = 1 ) then
+ if ( isAligned = '1' ) then
+ state_next <= STATE_END_WRITE_ALIGNED; -- don't assert u_pktend
+ else
+ state_next <= STATE_END_WRITE_NONALIGNED; -- assert u_pktend to commit small packet
+ end if;
+ end if;
+ else
+ fifoOp <= FIFO_NOP;
+ end if;
+
+ when STATE_END_WRITE_ALIGNED =>
+ u_fifoad <= IN_FIFO; -- Writing to FX2LP
+ fifoOp <= FIFO_NOP;
+ state_next <= STATE_IDLE;
+
+ when STATE_END_WRITE_NONALIGNED =>
+ u_fifoad <= IN_FIFO; -- Writing to FX2LP
+ fifoOp <= FIFO_NOP;
+ u_pktend <= '0'; -- Active: FPGA commits the packet.
+ state_next <= STATE_IDLE;
+
+ when STATE_READ =>
+ u_fifoad <= OUT_FIFO; -- Reading from FX2LP
+ if ( u_flagc = '1' ) then
+ -- A data byte will be available on the next clock edge
+ case addr is
+ when "0000000" =>
+ iNextR0 <= u_fd;
+ when "0000001" =>
+ iNext_T1_msb <= u_fd;
+ when "0000010" =>
+ iNext_T1_lsb <= u_fd;
+ when "0000011" =>
+ iNext_T2_msb <= u_fd;
+ when "0000100" =>
+ iNext_T2_lsb <= u_fd;
+ when "0000101" =>
+ iNext_T3_msb <= u_fd;
+ when "0000110" =>
+ iNext_T3_lsb <= u_fd;
+ when "0000111" =>
+ iNext_subT1_msb <= u_fd;
+ when "0001000" =>
+ iNext_subT1_lsb <= u_fd;
+ when "0001001" =>
+ iNext_subT2_msb <= u_fd;
+ when "0001010" =>
+ iNext_subT2_lsb <= u_fd;
+ when "0001011" =>
+ iNext_subT3_msb <= u_fd;
+ when "0001100" =>
+ iNext_subT3_lsb <= u_fd;
+ when "0001101" =>
+ iNext_HV1_msb <= u_fd;
+ when "0001110" =>
+ iNext_HV1_lsb <= u_fd;
+ when "0001111" =>
+ iNext_HV2_msb <= u_fd;
+ when "0010000" =>
+ iNext_HV2_lsb <= u_fd;
+ when "0010001" =>
+ iNext_HV3_msb <= u_fd;
+ when "0010010" =>
+ iNext_HV3_lsb <= u_fd;
+ when "0010011" => --19
+ --Do nothing, this is for c code
+ when "0010100" => --20
+ sNextutcngps <= u_fd;
+
+ when others =>
+
+ end case;
+ count_next <= count - 1;
+ if ( count = 1 ) then
+ state_next <= STATE_IDLE;
+ end if;
+ end if;
+ end case;
+ end process;
+
+ -- Breakout fifoOp
+ u_sloe <= fifoOp(0);
+ u_slrd <= fifoOp(1);
+ u_slwr <= fifoOp(2);
+
+end sync;
--
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